MCX W72 Secure and Ultra-Low-Power MCUs for Bluetooth LE, Channel Sounding, Matter, Thread, Zigbee

MCX-W72
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  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information please contact your sales representative.

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The MCX W72 family features a 96 MHz Arm® Cortex®-M33 core coupled with a multiprotocol radio subsystem supporting Matter, Thread, Zigbee and Bluetooth LE. The independent radio subsystem, with a dedicated core and memory, offloads the main CPU, preserving it for the primary application and allowing firmware updates to support future wireless standards. The MCX W72 also offers advanced security with an integrated EdgeLock® Secure Enclave Core Profile and will be supported by NXP's EdgeLock 2GO cloud services for credential sharing.

The MCX W72 family includes Bluetooth Channel Sounding capabilities, with a dedicated on-chip Localization Compute Engine to reduce ranging latency. It incorporates additional memory to support application-specific code, connectivity stacks and over-the-air firmware updates. In addition, the radio subsystem can run the full Thread or Zigbee stack alongside the Bluetooth Low Energy stack. This delivers reliable wireless performance, as the real-time activities of the radio run on a separate core from the application.

Building on NXP's strong history of providing industrial edge solutions, the MCX W series offers a wide operating temperature range from -40 °C to 125 °C and peripherals for industrial applications, including an optional CAN interface and will be part of NXP's 15-year Product Longevity program to support long-term industrial use.

The MCX W series is supported by the MCUXpresso Developer Experience to optimize, ease and help accelerate embedded system development.

The MCX W72 is in pre-production, developers can get started today with the MCX W71x, which is pin and software compatible.

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MCX W72

MCX-W72 Series

MCX W72 Architecture

MCX W72 Architecture Block Diagram
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Features

Core Platform

  • Arm Cortex-M33 up to 96 MHz
  • Nested vectored interrupt controller (NVIC)
  • Wake-up interrupt controller (WIC)

Memory

  • 2 MB program Flash with ECC
  • 264 kB SRAM with ECC and parity

Radio Subsystem

  • Dedicated Arm Cortex-M33 core
  • Dedicated 512 kB flash and controller for secure, authenticated NXP 15.4 and Bluetooth LE firmware
  • 171 kB dedicated SRAM
  • IEEE 802.15.4-2015 compliant radio
    • 101 dBm 250 kbps receive sensitivity
    • Improved enhanced ACK timing support in the 802.15.4 hardware
    • Dual PAN support
  • 2.4 GHz Bluetooth Low Energy Version 6 upgradeable radio supporting up to 24 simultaneous hardware connections in any central/peripheral combination
    • 106 dBm 125 kbit/s long range receive sensitivity
    • 102 dBm 500 kbit/s long range receive sensitivity
    • 97.5 dBm 1 Mbit/s receive sensitivity
    • 95 dBm 2 Mbit/s receiver sensitivity
  • Support for Bluetooth Channel Sounding
    • Integrated Localization Compute Engine (LCE) reduces ranging latency
  • Programmable transmit output power up to +10 dBm
  • Data rates: 125 kbit/s, 500 kbit/s, 1 Mbit/s and 2 Mbit/s
  • Modulation types: 2 level FSK, GFSK, MSK, GMSK
  • On-chip balun with single ended bidirectional RF port

Peripherals

  • Analog
    • 16-bit single ended SAR analog-to-digital converter (ADC) up to 2 Msps
    • Two high-speed analog comparators (CMP) with 8-bit digital-to-analog converter (DAC)
    • 1.0 V to 2.1 V voltage reference (Vref)
  • Timers
    • Two 6-channel 32-bit timers (TPM) with PWM capability and DMA support
    • Two 32-bit low-power timers (LPTMR) or pulse counters with compare features
    • 4-channel 32-bit low-power periodic interrupt timer (LPIT) with DMA support
    • One 56-bit timestamp timer
    • 32-bit seconds real time counter (RTC) with 32-bit alarm and independent power supply
    • Signal frequency analyzer (SFA) provides facilities for measurement of clock period/frequency as well as time between triggers
  • Communication Interfaces
    • Two low-power UART (LPUART) modules
    • Two low-power SPI modules and one MIPI-I3C module
    • Two low-power I²C (LPI2C) modules supporting the system management bus (SMBus) specification, version 2
    • Two optional FlexCANs with CAN and CAN FD supporting the full implementation of the CAN Specification Version 2.0, Part B. FD Support
    • One programmable FlexIO module supporting emulation of UART, I²C, SPI, Camera IF, LCD RGB, PWM/ waveform generation
    • 29 GPIO (48QFN)
  • System Peripherals
    • DC/DC converter supporting buck and bypass operating modes
    • Asynchronous DMA controller with per channel access permissions (secure/non-secure)
    • Wake-up unit for power-down modes

Security

  • EdgeLock secure enclave, core profile
    • Support for Edgelock 2GO cloud based certificate deployment and management
    • Secure boot and debug
    • Symmetric key encryption - AES-128/192/256 and ECB, CBC, CTR, GCM, CMAC and CCM modes
    • Asymmetric key encryption - ECC NIST P–192/224/256/384/521, Curve25519
    • Key exchange algorithms - ECDH(E), SPAKE2+, JPAKE
    • Secure key generation, storage and management
    • Flash access protection and optional encryption on-the-fly decryption using a PRINCE XEX block cipher mode

MCUXpresso Developer Experience

  • MCUXpresso ecosystem support
    • Selection of IDE choices
    • Pin, clock, peripheral, security and memory config tools
    • Security programming and provisioning tools
    • Software development kit (SDK)
    • MCUXpresso software development kit (SDK) with connectivity stacks and examples

Packaging

  • 48QFN, 7x7 mm, 29 GPIO

Operating Characteristics

  • Temperature range (ambient): -40 °C to 125 °C
  • Temperature range (junction): -40 °C to 125 °C
  • DC/DC voltage range: 1.8 V to 3.6 V
  • Bypass voltage range: 1.8 V to 3.6 V
  • AEC-Q100 qual with Industrial grade

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