i.MX537 Processors|HD Video

The i.MX53 family of processors represents NXP’s next generation of advanced multimedia and power-efficient implementation of the Arm^® Cortex^®-A8 core. With core processing speeds up to 800 MHz, the i.MX537 is optimized for both performance and power to meet the demands of high-end, advanced applications. Integrated display controller, 1080p HD video decode and 720p video encode, enhanced graphics and connectivity features make the i.MX537 ideal for a wide range of applications such as Human Machine Interfaces (HMI) and patient monitors which require rich user interfaces with high color displays and user interaction.

The i.MX537 provides key environmental differentiators for the industrial market. These include 3.3V I/O support, a 0.8 mm pitch package to reduce PCB and manufacturing costs, extended temperature coverage for harsh environments, industrial qualification for extended reliability and a formal long product supply guarantee to support product life spans.

The i.MX537 is supported by a companion NXP power management IC (PMIC), MC34709.

データシート

リファレンス・マニュアル

製品詳細

ブロック図

i.MX537 Multimedia Applications Processor Block Diagram

図を取得する PDF

Features

CPU Complex

800 MHz Cortex-A8 CPU
32 KB instruction and data caches
Unified 256 KB L2 cache
NEON SIMD media accelerator
Vector floating point coprocessor

Multimedia

Independent OpenGL^® ES 2.0 and OpenVG™ 1.1 hardware accelerators
Multi-format HD 1080p video decoder and HD 720p video encoder hardware engine
Dual display capable with multiple display options including TFT LCD, LVDS, analog TV-formats (composite, component, RGB) and standard VGA
Hardware accelerated image post-processing, display quality enhancement, and video and graphics combining
Two simultaneous camera inputs with hardware pre-processing

External Memory Interface

Up to 2 GB LP-DDR2, LV-DDR2, DDR2-800, and DDR3-800 SDRAM, 16/32-bit
Managed NAND Flash Support with eMMC 4.4/SDIO
Raw NAND with up to 16-bit ECC

Advanced Power Management

Multiple independent power domains
Dynamic voltage and frequency scaling

Connectivity

High-Speed USB 2.0 OTG with PHY
High-Speed USB 2.0 Host with PHY
Two additional High-Speed USB controllers (ULPI)
Integrated LVDS display interface supporting up to 2 channels each with 4 data pairs and 1 clock pair
Wide array of serial interfaces, including SDIO, SPI, I2C and UART
I2S and S/PDIF audio interfaces
10/100 Ethernet controller with IEEE1588 time stamping
SATA controller and PHY up to 1.5Gbps
Dual CAN interfaces

Security

Advanced security supporting High Assurance Boot, cryptographic cipher engines, random number generator, and tamper detection

Package

19mm x 19mm 529-ball TE-BGA
0.8mm pitch

Product Longevity

This product is included in NXP’s product longevity program, with assured supply for a minimum of 15 years after launch

設計・リソース

設計・ファイル

2 設計・ファイル

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i.MX53 SABRE Board Schematics

ZIP改訂 DJun 14, 2012 00:00:007.0 MBIMX53_SABRE_BOARD_SCHEMATICS
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MCIMX53-START i.MX53 QS Board Schematics

ZIP改訂 3May 12, 2011 00:00:006.6 MBIMX53_QS_BOARD_SCHEMATICS
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