i.MX534 Processors|Advance Performance

The i.MX534 applications processor offers advanced performance, connectivity and graphical user interface functionality necessary to drive next generation automotive instrument cluster and navigation systems. The i.MX534 processor is ideal for applications that require high performance user interfaces with 2D and 3D graphics, single or dual high resolution displays, and a high level of system integration. Building on the success of the i.MX535 in the consumer market, the automotive family of i.MX53 processors will bring advanced consumer electronics user experiences and device connectivity into the vehicles of the future. Currently sampling to high volume customers.

The i.MX534 is supported by a companion NXP^® power management IC (PMIC), MC34709.

データシート

リファレンス・マニュアル

製品詳細

ブロック図

i.MX534 Multimedia Applications Processor Block Diagram

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Features

CPU Complex

800 MHz Arm^{^®} Cortex^®-A8 CPU with AEC-Q100 qualification
32 KB instruction and data caches
Unified 256 KB L2 cache
NEON SIMD media accelerator
Vector floating point coprocessor

Multimedia

Independent OpenGL^® ES 2.0 and OpenVG™ 1.1 hardware accelerators
Dual display capable with multiple display options including TFT LCD, LVDS, analog TV-formats (composite, component, RGB) and standard VGA
Hardware accelerated image post-processing, display quality enhancement, and video and graphics combining
Two simultaneous camera inputs with hardware pre-processing

External Memory Interface

Up to 2 GB LP-DDR2, LV-DDR2, DDR2-800, and DDR3-800 SDRAM, 16/32-bit
Managed NAND Flash Support with eMMC 4.4/SDIO
Raw NAND with up to 16-bit ECC

Advanced Power Management

Multiple independent power domains
Dynamic voltage and frequency scaling

Connectivity

High-Speed USB 2.0 OTG with PHY
High-Speed USB 2.0 Host with PHY
Two additional High-Speed USB 2.0 controllers (ULPI)
Integrated LVDS display interface supporting up to 2 channels each with 4 data pairs and 1 clock pair
Wide array of serial interfaces, including SDIO, SPI, I2C and UART
I2S and S/PDIF audio interfaces
10/100 Ethernet controller
SATA controller and PHY up to 1.5Gbps
Dual CAN interfaces
MLB50 interface for MOST connectivity
Enhanced Serial Audio Interface (ESAI) to support multichannel audio
Hardware Asynchronous Sample Rate Converter (ASRC) for conversion of multiple audio I/O to common sample rates

Security

Advanced security supporting High Assurance Boot, cryptographic cipher engines, random number generator, and tamper detection

Package

19mm x 19mm 529-ball TE-BGA
0.8mm pitch

Product Longevity

This product is included in NXP^{^®}.s product longevity program, with assured supply for a minimum of 15 years after launch

設計・リソース

設計・ファイル

2 設計・ファイル

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i.MX53 SABRE Board Schematics

ZIP改訂 DJun 14, 2012 00:00:007.0 MBIMX53_SABRE_BOARD_SCHEMATICS
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MCIMX53-START i.MX53 QS Board Schematics

ZIP改訂 3May 12, 2011 00:00:006.6 MBIMX53_QS_BOARD_SCHEMATICS
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