Full NFC Frontend




MFRC522 Block diagram

MFRC522 Block diagram


  • Includes NXP’s intellectual property licensing rights (required for ISO/IEC 14443A implementation)
  • Fast and cost-efficient NFC design startup
  • Highly integrated analog circuitry to demodulate and decode responses
  • Buffered output drivers for connecting an antenna with the minimum number of external components
  • Integrated RF Level detector
  • Integrated data mode detector
  • Supports ISO/IEC 14443 A/MIFARE
  • Supports ISO/IEC 14443 B Read/Write modes
  • Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning
  • Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna size and tuning and power supply
  • Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation mode of about 100 mm depending on the antenna size and tuning and the external field strength
  • Supports MIFARE Classic encryption in Reader/Writer mode
  • ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
  • Contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s
  • Integrated RF interface for NFCIP-1 up to 424 kbit/s
  • S²C interface
  • Additional power supply to directly supply the smart card IC connected via S²C
  • Supported host interfaces:
    • SPI up to 10 Mbit/s
    • I²C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
    • RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply
    • 8-bit parallel interface with and without Address Latch Enable
  • FIFO buffer handles 64 byte send and receive
  • Flexible interrupt modes
  • Hard reset with low power function
  • Power-down mode per software
  • Programmable timer
  • Internal oscillator for connection to 27.12 MHz quartz crystal
  • 2.5 V to 3.6 V power supply
  • CRC coprocessor
  • Programmable I/O pins
  • Internal self-test


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