LS1020A

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The LS1 family, which includes the LS1020A and LS1022A communications processors, is built on Layerscape architecture, the industry’s first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.

Members of the value-performance tier, the LS1020A and LS1022A processors provide extensive integration and power efficiency for fanless, small form factor enterprise and consumer networking applications. Incorporating dual Arm^® Cortex^®-A7 cores running up to 1.2 GHz, the LS1020A and LS1022A processors deliver pre-silicon CoreMark^® performance of over 7,000, as well as virtualization support, advanced security features and broadest array of high-speed interconnects and optimized peripheral features ever offered in a sub-3 W processor (LS1022A processor is sub-2W typical).

The LS1020A and LS1022A processors features support for multiple industrial protocols, DDR3L/4 running up to 1600 MHz, integrated hardware-based security engine and QUICC Engine^®. and ECC protection on both L1 and L2 caches. The LS1020 and LS1022A processors are pin- and software-compatible with the LS1021A processor.

Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.

データシート

リファレンス・マニュアル

製品詳細

ブロック図

図を選択する。:

29841_LS1022A_BD
29841_LS1020A_BD

29841_LS1022A_BD

NXP Layerscape 1022A Processor block diagram

29841_LS1020A_BD

NXP Layerscape 1020A Processor block diagram

図を取得する PDF

Features

Core Complex

Dual Arm^{^®} v7 Cortex^®-A7 32-bit cores, each supporting dual precision floating point and NEONSIMD module running up to 1.2 GHz (LS1020A) or 600 MHz (LS1022A)
32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both instruction and data caches
Up to 512 KB coherent L2 cache with single bit error detection and correction, ECC protection

Networking Elements

SerDes
- 4 lane at up to 6 GHz (LS1020A)
  - Supports SGMII, PCIe and SATA
  - Ethernet
- 1 lane at up to 5 GHz (LS1022A)
  - Supports PCIe^{^®}
Three virtualized enhanced triple-speed Ethernet controllers (VeTSEC) supporting SGMII (up to 2),RGMII, RMII, MII (LS1020A)
- Support IEEE^® 1588
Two virtualized enhanced triple-speed Ethernet controllers (VeTSEC) supporting RGMII, RMII, MII
- Support IEEE 1588
Two PCIe Gen2 controllers (LS1020A)
- Supporting up to 5G/tps in 1-lane, 2-lane, or 4-lane (with a single controller)
- MSI supported
One PCIe Gen2 controller
- Supporting up to 5G/tps in 1-lane
- MSI supported

Accelerators and Memory Control

DDR memory controller supports DDR3L and DDR4 at up to 1600 MHz (LS1020A)
- 8-bit, 16-bit, 32-bit memory supported, with ECC support
DDR memory controller supports DDR3L at up to 1000 MHz
- 8-bit, 16-bit memory supported, with ECC support
Security Engine (SEC5.4) features five cryptographic hardware acceleration modules, true random number generator, hashing and CRC unit.

Basic Peripherals and Interconnect

Arm Cache Coherent Interconnect (CCI400)
Arm AMBA4 MPCore Virtualization
Integrated Flash controller supporting 16-bit interface
QuadSPI Flash controller
USB3.0 superspeed controller with integrated PHY, supporting OTG, Host and Device modes (LS1020A)
USB2.0 controller supporting OTG, Host and Device modes
SD/MMC controller
SATA3 controller supporting 6G/tps
3x I²C
2x SPI

比較表

	LS1021A	LS1020A	LS1022A
Cores	2	2	2
Core Frequency	Up to 1.2 GHz	Up to 1.2 GHz	Up to 600 MHz
SerDes	4 Lanes	4 Lanes	1 Lanes
Security	SEC 5.4	SEC 5.4	SEC 5.4
DDR 4	Yes	Yes	No
USB 3.0	Yes	Yes	No
LCD Support	Yes	No	No

We recommend the following Power Management IC for LS1020A and LS1022A Processors

Select the specifications below to find the perfect fit for your design

PMIC Part Number	Description	External Memory Voltage (V)	Ambient Operating Temperature (Min-Max) (°C)	Qualification Tier

MC34VR500V1ES	Regulator, Buck, Quad with up to 4.5A Output and Triple User-programmable LDOs, QFN 56	1.35	-40 to 105	Industrial
MC34VR500V2ES	Regulator, Buck, Quad with up to 4.5A Output and Factory programmed LDOs, QFN 56	1.35	-40 to 105	Industrial

ドキュメンテーション

クイック・リファレンスドキュメンテーションの種類.

1-5 の 31 ドキュメント

^{ファクト・シート}
Layerscape 1020A and LS1022A - Fact Sheet注目

PDF改訂 3Feb 27, 2020348.9 KBLS1020ALS1022AFSEnglish, 中文
^{ホワイト・ペーパ}
Machine-to-Machine (M2M) Gateway: Trusted and Connected Intelligence - White Paper注目

PDF改訂 0Oct 17, 2013302.0 KBM2MGATEWAYWPEnglish
^{ホワイト・ペーパ}
Networking for Industrial and IoT Applications - White Paper注目

PDF改訂 0Aug 19, 2014339.4 KBQORIQINDIOTWPEnglish, 中文
^{データ・シート}
LS1022A Data Sheet

PDF改訂 7Jun 27, 20191.8 MBLS1022AEnglish
サインインが必要です
^{データ・シート}
LS1020A Data Sheet

PDF改訂 8Jun 27, 20192.2 MBLS1020AEnglish
サインインが必要です
^{リファレンス・マニュアル}
LS1021A Reference Manual

PDF改訂 3.1Feb 28, 202034.2 MBLS1021ARMEnglish
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^{リファレンス・マニュアル}
QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual

PDF改訂 9May 3, 201813.4 MBQEIWRMEnglish
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^{アプリケーション・ノート}
AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note

PDF改訂 1Sep 1, 20226.5 MBAN13656English
^{アプリケーション・ノート}
Thermal Management Unit Usage

PDF改訂 0Apr 27, 2022241.6 KBAN12310English
^{アプリケーション・ノート}
PBL Configuration using QCVS Application Note

PDF改訂 1Nov 30, 20201.0 MBAN5260English, 中文
^{アプリケーション・ノート}
AN4878, LS1021A Design Checklist

PDF改訂 6Nov 26, 2019774.6 KBAN4878English
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^{アプリケーション・ノート}
AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces - Application Note

PDF改訂 2Jul 10, 20191.5 MBAN5097English
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^{アプリケーション・ノート}
AN12270, Bringing up Layerscape devices using CCS script and DRAM boot

PDF改訂 0Jan 30, 2019907.3 KBAN12270English, 中文
^{アプリケーション・ノート}
AN5376, How Does QuadSPI Work with a Serial NAND - Application Note

PDF改訂 0Sep 26, 2017359.4 KBAN5376English
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^{アプリケーション・ノート}
General soldering Temperature Process Guidelines

PDF改訂 1Aug 16, 2017281.6 KBAN3300English
^{アプリケーション・ノート}
AN5085, Powering the LS102xA with the MC34VR500 Power Management Interface Chip - Application Note

PDF改訂 0Jul 18, 2017281.9 KBAN5085English
^{アプリケーション・ノート}
AN4893, Understanding Endianness on Layerscape LS1021A - Application Note

PDF改訂 0Jul 12, 2017905.4 KBAN4893English
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^{アプリケーション・ノート}
AN5089, Programming RCW and U-Boot on LS1021A-TWR - Application Note

PDF改訂 0Mar 14, 20171.3 MBAN5089English
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^{アプリケーション・ノート}
AN5077, Migrating from Power Architecture to Arm^® Architecture

PDF改訂 0Jul 28, 2016768.7 KBAN5077English
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^{アプリケーション・ノート}
Using an External GCC Toolchain with CodeWarrior for Arm^®v7 Application Note

PDF改訂 4Jan 15, 2016824.8 KBAN5048English
^{アプリケーション・ノート}
AN5125, Introduction to Device Trees - Application Note

PDF改訂 0Sep 3, 2015566.4 KBAN5125English
^{アプリケーション・ノート}
Adding Custom Registers to the CodeWarrior for Power Architecture Processors

PDF改訂 0Jul 15, 2015147.2 KBAN5065English
^{アプリケーション・ノート}
AN4877, PROFIBUS on QUICC Engine Block

PDF改訂 1Dec 15, 2014450.8 KBAN4877English
^{アプリケーション・ノート}
AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note

PDF改訂 4Nov 11, 2014468.7 KBAN4039English
^{アプリケーション・ノート}
SerDes Reference Clock Interfacing and HSSI Measurements Recommendations

PDF改訂 Rev. 0May 13, 2011577.2 KBAN4311English
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DDR Interleaving for PowerQUICC and QorIQ Processors

PDF改訂 1Jun 30, 2010717.3 KBAN3939English
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^{アプリケーション・ノート}
Solder Joint Temperature and Package Peak Temperature

PDF改訂 0Aug 2, 2006151.6 KBAN3298English
^製品概要
LS1020/22A Family Communications Processor Product Brief

PDF改訂 1Jan 18, 2017958.8 KBLS1020APBEnglish
サインインが必要です
^{サポート情報}
FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP^® Cryptographic Accelerators - White Paper

PDF改訂 1.9Oct 28, 2016303.5 KBFSLNISTCAVPEnglish
^{サポート情報}
LS1020A_21A_22A Family Customer Export Control Information

PDF改訂 1Oct 5, 201617.6 KBLS1020A_21A_22A-PECIEnglish
^{ホワイト・ペーパ}
QORIQPMWP, QorIQ Power Management - White Paper

PDF改訂 0Mar 30, 20171.4 MBQORIQPMWPEnglish