QorIQ® P2040/P2041 Multicore Communications Processors with Data Path

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NXP QorIQ P2040 Communication Processor Block Diagram

NXP QorIQ P4020 Communication Processor Block Diagram


Core Complex

  • Quad e500mc cores to 1.2 GHz (P2040) and 1.5 GHz (P2041) with 32 KB I/D L1
    • 128 KB L2 cache per core (P2041 only)
  • CoreNet® fabric with 1 MB CoreNet platform cache

Networking Elements

  • 10 SerDes lanes up to 5 GHz, supporting 3x PCI Express® 2.0, 2x Serial RapidIO® (1.3+2.1), 5x SGMII, 4x 2.5 Gb/s SGMII, XAUI (P2041 only), 2x Serial ATA 2.0, Aurora debug port

Accelerators and Memory Control

  • 64-bit (72-bit with ECC) DDR3/3L memory controller to 1.2 GHz (P2040) and 1.3 GHz (P2041) data rate
  • Hardware acceleration
    • Frame manager for packet parsing, classification, and policing
    • Queue manager for scheduling, and workload distribution
    • Pattern matching engine for regular expression searches
    • Security block for crypto algorithm acceleration
    • RapidIO message manager for type nine and 11 messaging

Basic Peripherals and Interconnect

  • SD/MMC, 2x DUART, 4x I²C, SPI, 2x RGMII, 2x USB 2.0 with integrated PHY, 16-bit local bus
  • 783-pin FCPBGA package, 23 mm x 23 mm

Additional Features

  • Hardware hypervisor for safe partitioning of operating systems between cores
  • Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered

部品番号: P2040NSE7HLC, P2040NSE7MMC, P2040NSN7FLC, P2040NSN7HLC, P2040NSN7KLC, P2040NSN7MMC, P2040NXE7MMC, P2040NXN7MMC, P2041NSE7MMC, P2041NSE7NNC, P2041NSE7PNAC, P2041NSE7PNC, P2041NSN7MMC, P2041NSN7NNC, P2041NSN7PNAC, P2041NSN7PNC, P2041NXE7MMC, P2041NXE7NNC, P2041NXE7PNC, P2041NXN7MMC, P2041NXN7NNC, P2041NXN7PNC.


P2040 P2041
Cores 4 4
Core Frequency 667 to 1.2 GHz 1.2 to 1.5 GHz
L2 Cache - 128 KB/core
L3/Platform Cache 1 MB 1 MB
DDR3 1x 32/64-bit 1x 32/64-bit
GbE - 5x 1 Gigabit Ethernet 1x 10 Gigabit Ethernet
SERDES 10 Lanes 10 Lanes
Security Trust Trust


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