i.MX 6DualPlus Applications Processors | Dual Arm Cortex-A9 for extreme graphics performance| 1.2 GHz

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The i.MX 6DualPlus family delivers dramatic graphics and memory performance enhancements and are pin-compatible with a broad range of i.MX 6 processors. This device encompasses a dual-core Arm^® Cortex^®-A9 platform running up to 1.2 GHz* with 1 MB of L2 cache, advanced graphics, prefetch and resolve engine, and optimized 64-bit DDR3 or 2-ch., 32-bit LPDDR2 support. Integrated FlexCAN, MLB busses, PCI Express^® and SATA-2 provide excellent connectivity, while integration of LVDS, MIPI display port, MIPI camera port and HDMI v1.4 makes it an ideal multicore platform for a leading-edge consumer, automotive and industrial multimedia applications which require higher graphics performance.

Visit www.nxp.com/imx6tools for the latest software and tools.

* 1.0 GHz available now. For 1.2 GHz, contact NXP for availability.

i.MX 6 applications processors are part of NXP's EdgeVerse™ edge computing platform.

データシート

リファレンス・マニュアル

製品詳細

ブロック図

i.MX 6DualPlus Multimedia Applications Processor Block Diagram

図を取得する PDF

Features

CPU Complex

Embedded prefetch and resolve engine
GPU 3D
- Vivante GC2000
- 200Mtri/s 1000Mpxl/s, OpenGL^® ES 3.0 and Halti, OpenCL^™ 1.1 EP
GPU 2D(Vector Graphics)
- Vivante GC355
- 300Mpxl/s, OpenVG^™ 1.1
GPU 2D(8-layer Composition)
- Vivante GC320
- 600Mpxl/s, BLIT
Video Decode
- HD (1080p + 720p) 30fps
Video Encode
- HD 1080p 30fps
Camera Interface
- Types: 1x 20-bit parallel, MIPI-CSI2 (4 lanes), three simultaneous inputs

Memory

512KB OCRAM
DDR
- Significant increase in 64-bit memory bus performance, and memory interfaces support DDR3, DDR3L and LP-DDR2 at 533 MHz
2x32 LP-DDR2, 1x64 DDR3 / DDR3L

Connectivity

Four USB 2.0
- 1x HS USB 2.0 OTG + PHY
- 1x HS USB 2.0 Host + PHY
- 2x HS USB 2.0 Host (HSIC)
Ethernet
- 1 Gbps + IEEE^®1588
Expansion Ports
- 4x eMMC 4.5 / SD 3.0
- 5x SPI, 5x UART, 3x I²C
- PCIe 2.0 (1 lane)

Display

2x QXGA (2048x1536)
or 2x WXGA (1280 x 720)

Advanced Power Management

PMU integration
NXP^® PF0100F9 power management unit

Package and Temperature

2x Arm^® Cortex^®-A9 up to 1.2 GHz per core
1 MB L2 cache
32 KB instruction and data caches
NEON SIMD media accelerator

設計・リソース

設計・ファイル

2 設計・ファイル

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IBIS Model file for i.MX 6DQP

ZIP改訂 1Jan 11, 2017 00:00:0025135 KBIMX6DQP-IBIS
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BSDL file for i.MX 6QuadPlus and i.MX 6DualPlus

ZIP改訂 1Feb 19, 2016 00:00:0021.5 KBIMX6DP-6QP-BSDL
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