Expandable 5-Channel I²C-Bus Hub

PCA9518A

The PCA9518A is a CMOS integrated circuit intended for application in I²C-bus and SMBus systems.

While retaining all the operating modes and features of the I²C-bus system, it permits extension of the I²C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling virtually an unlimited number of buses of 400 pF.

The I²C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9518A enables the system designer to divide the bus into an unlimited number of segments off of a hub where any segment to segment transition sees only one repeater delay and is multiple controller capable on each segment.

Using multiple PCA9518A parts, any width hub (in multiples of five)1can be implemented using the expansion pins.

The PCA9518A is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also improves partial power-down performance, keeping I²C-bus I/O pins in high-impedance state when VDD is below 2.0 V.

A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster thanks to the EXPxxxn pins that allow the I²C-bus signals to be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since there is no direction pin, slightly different 'legal' low voltage levels are used to avoid lock-up conditions between the input and the output of individual repeaters in the cluster. A 'regular LOW' applied at the input of any of the PCA9518 devices will then be propagated as a 'buffered LOW' with a slightly higher LOW value to all enabled outputs in the PCA9518 cluster. When this 'buffered LOW' is applied to a PCA9515 and PCA9516 or separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a 'regular LOW 'and will not propagate it as a 'buffered LOW' again. The PCA9510/9511/9513/9514 and PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518 either, but can be used in series with themselves since they use shifting instead of static offsets to avoid lock-up conditions. This note is applicable to the 'A' versions of these devices also.

製品詳細

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PCA9518A Block Diagram

PCA9518A Block Diagram

Block diagram: PCA9518AD, PCA9518APW

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Features

Key Features

  • Expandable 5 channel, bidirectional buffer
  • I²C-bus and SMBus compatible
  • Active HIGH individual repeater enable inputs
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • Operating supply voltage range of 2.3 V to 3.6 V
  • 5 V tolerant I²C-bus and enable pins
  • 0 Hz to 400 kHz clock frequency²
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Package offerings: SO20 and TSSOP20
  • The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater

部品番号： PCA9518APW.

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