High-Performance Quad-Core DSP with Security





MSC8154 Digital Signal Processor Block Diagram

MSC8154 Digital Signal Processor Block Diagram


  • Four StarCore® DSP SC3850 core subsystems operating at up to 1 GHz/8000 MMACS per core and up to 32000 MMACS per device
  • Multi accelerator platform engine for baseband (MAPLE-B)
  • High-speed, high-bandwidth CLASS fabric arbitrates between the DSP cores and other CLASS leaders to M2 memory, M3 memory, DDR controllers, MAPLE-B and the configuration registers
  • Two DDR controllers with up to 400 MHz clock (800 MHz data) rate and 32/64-bit DDR2/3 SDRAM data bus
  • Dual RISC core QUICC Engine® subsystem operating at up to 500 MHz provides parallel packet processing independent of the DSP cores
  • HSSI that supports two 4x SerDes ports
  • Security engine core (SEC) optimized to process all the cryptographic algorithms associated with IPSec, IKE, SSL/TLS, 3GPP and LTE
  • Four TDM interfaces
  • UART and I²C interfaces
  • Eight software watchdog timers
  • Sixteen 16-bit timers, two 32-bit general purpose timers per core for RTOS support
  • I/O interrupt concentrator and virtual interrupt support, eight hardware semaphores
  • Thirty-two GPIO ports multiplexed with interface signals and IRQ inputs
  • Boot options: Ethernet, Serial RapidIO, I²C and serial peripheral interface (SPI)
  • Three input clocks and five PLLs
  • JTAG Test Access Port (TAP) and boundary scan architecture designed to comply with IEEE® Std. 1149.1 profiling and performance monitoring support
  • Reduced power dissipation with wait, stop and power down low-power standby modes
  • Optimized power management circuitry
  • CMOS 45 nm SOI technology in 29 mm x 29 mm, 783 ball FC-PBGA package


クイック・リファレンス ドキュメンテーションの種類.

1-5 の 54 ドキュメント




1 ハードウェア提供


1 ソフトウェア・ファイル

  • IDE: デバッグ/コンパイル/ビルド・ツール

    SmartDSP OS

注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。


3 エンジニアリング・サービス

本製品をサポートするパートナーの一覧は、 パートナーマーケットプレイス.


1 トレーニング