24-bit Symphony® DSP

DSP56371
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Targeted at audio/video (AV) receivers, home theaters, surround sound decoders, mini stereo systems, digital TV audio systems and automotive audio systems, the DSP56371 is designed to meet the demands of audio electronics system designers by supporting the latest generation decoders, such as Dolby®, THX® and DTS®, among others.

The DSP56371 is capable of running delay management, bass management and DTS96/24 while using less than half of the DSP's computing capability. This enables designers to add system enhancements that the discerning audio consumer expects. The performance increase is made possible through the use of a higher core frequency, fewer memory wait states, a larger amount of on-chip static random access memory (SRAM) and the addition of an enhanced filter coprocessor (EFCOP). By removing the need for external high-speed SRAM and making smaller, less complex boards, the DSP56371 is performance-rich and cost-effective.

製品詳細

ブロック図

DSP56371 Block Diagram

DSP56371 Block Diagram
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Features

  • Multimode, multichannel decoder software functionality
  • Dolby and/or DTS license required
    • Prologic II
    • DTS Neo6
    • DTS 2.3
    • WMA
    • AAC
    • Dolby headphone
    • Dolby virtual speaker
  • Digital audio post-processing capabilities
    • Parametric EQ
    • Tone control or graphic EQ
    • Dynamic range compression
    • Loudness
    • Bass boost
    • Speaker comp
    • Fade/balance
    • Music search
    • Compression 
  • DSP core
    • 1.25-volt core with a 3.3-volt peripheral I/O
    • Object code compatible with the DSP56000 core with highly parallel instruction set 
    • Data ALU with a 24 x 24-bit multiplier-accumulator and a 56-bit barrel shifter; 16-bit arithmetic support
    • Program control with position-independent code support and instruction cache support
    • Six-channel DMA controller
    • PLL based clocking with a wide range of frequency multiplications (1 to 255), predivider factors (1 to 3) and power saving clock divider (2I: i=0 to 7); reduces clock noise
    • Internal address tracing support and OnCE for hardware/software debugging
    • JTAG port
    • Very low-power CMOS design, fully static design with operating frequencies down to DC
    • Stop and wait low-power standby modes
    • EFCOP running concurrently with core
  • On-chip memory configuration
    • 16K–48K x 24-bit Y-data RAM and 32K x 24-bit Y-data ROM
    • 36K x 24-bit X-data RAM and 32K x 24-bit X-data ROM
    • 28K–64K x 24-bit program and bootstrap ROM
    • 4K x 24-bit program RAM
    • Various memory switches available 
  • Peripheral modules
    • Enhanced serial audio interface (ESAI_0): up to four receivers and six transmitters, leader or follower. I²S, Sony, AC97, network and other programmable protocols
    • Serial host interface (SHI): SPI and I²C protocols, 10-word receive FIFO, support for eigth, 16 and 24-bit words.
    • Triple timer module
    • Digital audio transmitter (DAX): one serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats
    • Pins of unused peripherals (except SHI) may be programmed as GPIO lines

部品番号： DSPA56371AF150, DSPB56371AF150, DSPB56371AF180, DSPC56371AF150.

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