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MC92602FS SerDes Quad Transceivers[MC92602FS]
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Signal I/O count is reduced relative to the MC92600 Quad device by operating the parallel interfaces at 125 MHz Double Data Rate (DDR) 4-bits wide per channel, per direction. The I/O interface is HSTL class-I, source terminated which is an accepted signaling method for 125 MHz DDR data for FR-4 board traces up to 8 inches. This aggressive signaling scheme offers excellent board density without making unreasonable signal integrity demands of the system logic to which it interfaces.
The double data rate interface and IEEE Std. 802.3 packet compatability, make the MC92602 an ideal choice for high-density board designs requiring a high number of Gigabit Ethernet ports. Like it's predecessors, it is carefully designed for low power consumption and nominally consumes less than 1.2 W with all links operating at full speed. The MC92602 is offered in a JEDEC standard 196 pin, 15 mm body size package to provide excellent board density in applications with a large number of channels
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