24-bit Digital Signal Processor | NXP Semiconductors

The ROM-based DSP56306 is designed to support multifunction wireless and embedded DSP applications. In addition to the large on-chip ROM spaces, the DSP56306 also has a ROM patch feature that facilitates updates to the mask-program ROM-based on-chip software. The DSP56306 includes a triple timer module, Host Interface (HI08), an Enhanced Synchronous Serial Interface (ESSI), and a Serial Communications Interface (SCI). The DSP56300 core family includes a Phase Lock Loop (PLL), External Memory Interface (EMI), Data Arithmetic Logic Unit (Data ALU), 24-bit addressing, instruction cache, and DMA. The DSP56306 offers 66 MIPS at 3.0-3.6 volts. TEMPORAL 2.

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1-10 件/全 11 ドキュメント

コンパクトリスト

Programming the CS4218 CODEC for Use With DSP56300 Devices[AN1790]

PDFAug 3, 2005改訂 1
DSP56300 HI08 Host Port Programming[AN1808]

PDFAug 2, 2005改訂 1
DSP56300 Programming the DSP56300 OnCE and JTAG Ports[AN1839]

PDFAug 1, 2005改訂 1
Using the DSP56300 Direct Memory Access Controller[APR23]

PDFOct 5, 2001改訂 0
DSP563xx Port A Programming[AN1751]

PDFMay 1, 1998改訂 1

Programming the CS4218 Codec for Use with DSP56300 Devices Supporting Software[AN1790SW]

ZIPAug 4, 2005改訂 1

DSP56306 Chip Errata for DSP56306 0F93S Rev 3.0[DSP56306CE0F93S]

PDFJul 17, 2000改訂 3.0
DSP56306 Chip Errata for DSP56306 0J27A Rev 2.0[DSP56306CE0J27A]

PDFJul 17, 2000改訂 1.9
DSP56306 Chip Errata for DSP56306 1F93S Rev 2.9[DSP56306CE1F93S]

PDFJul 17, 2000改訂 2.9

DSP56300 Mechanical Differences Between the 196-Pin MAP-BGA and 196-Pin PBGA Packages[EB360]

PDFOct 6, 2005改訂 1

NXP^® DSP Linker/Librarian Reference Manual[DSPLNKRRM]

PDFJan 18, 2008改訂 1

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