1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications
SSTUH32865ET アラートの受信
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The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUH32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUH32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which-while requiring a minimum 9 mm x 13 mm of board space-allows for adequate signal routing and escape using conventional card technology.
The SSTUH32865 is identical to SSTU32865 in function and performance, with higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while maintaining speed and signal integrity.
製品詳細
部品番号： SSTUH32865ET.
ドキュメント
クイック・リファレンス ドキュメンテーションの種類.