1.8 V Simple Mobile Interface Link Bridge IC
PTN3700EV アラートの受信
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The PTN3700 is a 1.8 V simple mobile interface link bridge IC which can function both as a transmitter-serializer or a receiver-deserializer for RGB888 video data. When configured as transmitter (using input pin TX/RX), the PTN3700 serializes parallel CMOS video input data into 1, 2 or 3 subLVDS-based high-speed serial data channels. When configured as receiver, the PTN3700 deserializes up to 3 high-speed serial data channels into parallel CMOS video data signals.
The parallel interface of the PTN3700 is based on the conventional and widely used 24-bit wide data bus for RGB video data, plus active LOW HS (Horizontal Synchronization) and VS (Vertical Synchronization) signals and an active HIGH DE (Data Enable) signal. An additional two auxiliary bits A[1:0] are provided to permit signaling of miscellaneous status or mode information across the link to the display. The serial interface link of the PTN3700 is based on the open Simple Mobile Interface Link (SMILi) definition. In order to keep power low while accommodating various display sizes (e.g., up to 24-bit, 60 frames per second XVGA), the number of high-speed serial channels (‘lanes’) is configurable from 1 to 3 depending on the bandwidth needed. The data link speed is determined by the PCLK (Pixel Clock) rate and the number of serial channels selected.
In order to maintain a low power profile, the PTN3700 has three power modes, determined by detection of an active input clock and by shutdown pin XSD. In Shutdown mode (XSD = LOW), the PTN3700 is completely inactive and consumes a minimum of current. In Standby mode (XSD = HIGH), the device is ready to switch to Active mode as soon as an active input clock signal is detected and assume normal link operation.
In Transmitter mode, the PTN3700 performs parity calculation on the input data (R[7:0], G[7:0], B[7:0] plus HS, VS and DE data bits) and adds an odd parity bit CP to the serial transmitted data stream. The PTN3700 in Receiver mode also integrates a parity checking function, which checks for odd parity across the decoded input word (R[7:0], G[7:0], B[7:0] plus HS, VS and DE data bits) and indicates whether a parity error has occurred on its CPO out pin (active HIGH). When a parity error occurs, the most recent error-free pixel data will be output instead of the received invalid pixel data.
PTN3700 in Receiver mode offers an optional advanced frame mixing feature, which allows 18-bit displays to effectively display 24-bit color resolution by applying a pixel data processing algorithm to the 24-bit video input data.
One of two serial transmission methods is selectable: pseudo source synchronous transmission based on the pixel clock, or true source synchronous transmission based on the bit clock. The latter uses a methodology characterized by zero overhead and operation guaranteed free from false pixel synchronization.
The PTN3700 automatically rotates the order of the essential signals (parallel CMOS and high-speed serial data and clock) depending on whether it is operating as transmitter or as receiver (using pin TX/RX). In addition, two Pinning Select bits (inputs PSEL[1:0]) allow for four additional signal order configurations. This allows for various topologies of printed circuit board or flex foil layout without crossing of traces and enables the easy introduction of PTN3700 into an existing ‘parallel’ design avoiding board re-layout.
The PTN3700 is available in a 56-ball VFBGA package and operates across a temperature range of -40 °C to +85 °C.
製品詳細
Features
General Features
- Configurable as either Transmitter or Receiver
- One of two serial transmission methods selectable (pixel clock referenced pseudo source synchronous or bit clock referenced true source synchronous)
- 3 differential subLVDS high-speed serial lanes
- One differential pixel clock
- Configurable aggregate data bandwidth allowing up to 24-bit color, 60 fps XGA:
- 1 lane at 30x serialization rate up to 650 Mbit/s
- 2 lanes at 15x serialization rate up to 1300 Mbit/s
- 3 lanes at 10x serialization rate up to 1.95 Gbit/s
- Parity encoding (transmitter) and detection (receiver) with last valid pixel repetition
- Advanced Frame Mixing function (in Receiver mode) for 24-bit color depth using conventional 18-bit displays or specially adapted '18-bit plus' displays
- Parallel CMOS I/O based on interface definition of RGB888 plus HS, VS, DE
- Very low power profile:
- Shutdown mode for minimum idle power (< 3 uA typical)
- Low-power Standby mode with input clock frequency auto-detect (< 3 uA typical)
- Low active transmitter power: 18 mW (typ.) for QVGA and 40 mW (typ.) for WVGA
- Low active receiver power: 15 mW (typ.) for QVGA and 36 mW (typ.) for WVGA
- Slew rate control on receiver parallel CMOS outputs
- Operates from a single 1.8 V ± 150 mV power supply
- Configurable mirroring pinout (dependent on Tx or Rx mode and PSEL[1:0] inputs) for optimum single layer flex-foil flow-through in various application scenarios
- Available in 56-ball VFBGA package
部品番号： PTN3700EV.
ドキュメント
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