Target Processor

The Target Processor page displays the build configuration settings that apply to the target processor specified in an application project or in a library project.

In the following table, the Setting column lists the settings and the related GCC compiler options. If a setting has the “Toolchain default” option, this stands for the default (“factory”) GCC configuration setting. The availability of properties depends on the selected processor.

Table 1. Application and Library Project Properties: Target Processor
Setting Description
Other target flags Additional compiler options not included in the project properties. You can specify any required options supported by the compiler. Consult the compiler documentation.
Important: For this setting to take effect, specify “Toolchain default” in the Target processor field.
Arm family The target Arm® processor. GCC uses this name to derive the target Arm® architecture and the Arm® processor type to tune it for performance. Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option.

By default, the core specified in the project creation wizard is selected.

Recommendations:
  • Do not use options other than “cortex-m7”, “cortex-r52”, “cortex-m33” and “cortex-m4”. Other cores, though displayed, are not supported by the project creation wizard. If you select an unsupported core, you will have to manually recreate the project structure, the startup code and other metadata in the project.
  • When you use the “Toolchain default” option, no core-specific options are passed to the compiler. Using this option is not recommended as the default option set may change without further notice.
Architecture

-march=name

 The target Arm® architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code.
Target processor

-mcpu={cortex-a53, cortex-a53+nofp}

 The target processor that will execute the code. Options:
  • Toolchain default: Compiles the code by using the default core that was used to build GCC.
  • cortex-a53: Compiles the code for Cortex-A53 with hardware support for floating-point instructions that will be performed by the integrated FPU.
  • cortex-a53+nofp: Compiles the code for Cortex-A53 with no support for floating-point instructions.
Optimize

-mtune=name

 The target host processor for which you want to run code optimizations.
Instruction set

-marm, -mthumb

The assembler instruction set for generating code that executes in the Arm or Thumb state.

Options: Toolchain default, Thumb (-mthumb), Arm (-marm).

Thumb interwork

-mthumb-interwork

 This option enables GCC to generate code that supports calls between the Arm and Thumb instruction sets.
Endianness

-mlittle-endian

 This setting enables you to generate code for a processor running in the little-endian/big-endian mode.

Options: Toolchain default, Little endian.

Default: Toolchain default.

Note: By default, GCC is configured to generate code for a processor running in the little-endian mode.
Float ABI

-mfloat-abi={hard, soft,softfp}

 The floating-point application binary interface (ABI) that the GCC will use when compiling the code. Notice that hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.

Options:

  • Toolchain default: Compiles your code by using the default (specified in the GCC) ABI for the target processor. The GCC will detect the floating-point operations support based on the support for FPU in the selected processor. On Cortex-A53 based processors, this defaults to -mfloat-abi=hard so that the core is responsible for floating-point operations and the FPU-specific calling conventions are used.
  • Library (soft): Enables GCC to generate code with library calls so that floating-point operations are emulated by the compiler and not the FPU on the processor.
  • Library with FP (softfp): Enables GCC to generate code with support for hardware floating-point instructions provided by the processor while using soft floating-point ABI calling conventions.
  • FP instructions (hard): Enables GCC to generate code with support for hardware floating-point instructions provided by the processor, and uses the ABI calling convention specific to the FPU on the processor.
Default: Toolchain default.
FPU Type

-mfpu=name

 The floating-point unit (FPU) or hardware emulation available on the target processor.

This setting is only available if hardware or hardware emulated ABI option (FP instructions (hard) or Library with FP (softfp) respectively) is selected in Float ABI and is currently locked to the fpv5-sp-d16 architecture for handling floating-point operations. This architecture includes support for FP registers that can be used by your application as 32 single-precision floating point registers or as 16 double-precision floating point registers.

Options: Toolchain default, fpv5-sp-d16.

Default: Toolchain default. The GCC will select the floating-point instructions based on the settings specified in the Architecture and Target processor settings.
Unaligned access

-munaligned-access, -mno-unaligned-access

This option enables or disables access to addresses not aligned to 16 or 32 bits. If unaligned access is disabled, words in packed data structures are accessed a byte at a time.

Options: Toolchain default, Enabled (-munaligned-access), Disabled (-mno-unaligned-access)

Default: Toolchain default.

Note: By default, unaligned access is enabled on all Arm® architectures, except for all pre-Arm®v6, all Arm®v6-M, and all Arm®v8-M.
Libraries support The standard library and the I/O mode to be used for the application. Options:
  • None: (Not recommended) Do not link the standard C/C++ library and disable support for console I/O.
  • newlib_nano no I/O: Link the lightweight NewLib and disable semihosting.
  • newlib_nano Debugger Console: Link the lightweight NewLib and enable semihosting.
  • newlib_nano Semihosting: Link the lightweight NewLib and enable semihosting.
  • newlib_nano Semihosting v2: Link the lightweight NewLib and enable semihosting v2 specs for M cores.
  • newlib no I/O: Link the standard NewLib with system C/C++ functions and disable semihosting.
  • newlib Debugger Console: Link the standard NewLib with system C/C++ functions and use semihosting.
  • newlib Semihosting: Link the standard NewLib with system C/C++ functions and use semihosting.
  • newlib Semihosting v2: Link the standard NewLib with system C/C++ functions and use semihosting v2 specs for M core.
  • ewl_c no I/O: Link the standard Embedded Warrior Library (EWL) and disable semihosting.
  • ewl_c Debugger Console: Link the standard EWL and enable semihosting.
  • ewl_nano_c no I/O: Link the lightweight EWL and disable semihosting.
  • ewl_nano_c Debugger Console: Link the lightweight EWL and enable semihosting.
Note: The availability of libraries depends on GCC toolchain and the Arm® core.
Sysroot The logical root location of headers and libraries.
Code Model This option tells the compiler to generate code for specific code model.

Options: Toolchain default, large, small, tiny.