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i2s_001.h
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1 /*
2  * @brief I2S Registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __I2S_001_H_
33 #define __I2S_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
50 typedef struct {
51  __IO uint32_t DAO;
52  __IO uint32_t DAI;
56  __IO uint32_t DMA1;
57  __IO uint32_t DMA2;
58  __IO uint32_t IRQ;
66 
71 #define I2S_WORDWIDTH_8 (0UL << 0)
72 #define I2S_WORDWIDTH_16 (1UL << 0)
73 #define I2S_WORDWIDTH_32 (3UL << 0)
74 
75 #define I2S_STEREO (0UL << 2)
76 #define I2S_MONO (1UL << 2)
77 
78 #define I2S_MASTER_MODE (0UL << 5)
79 #define I2S_SLAVE_MODE (1UL << 5)
80 
81 #define I2S_STOP_ENABLE (0UL << 3)
82 #define I2S_STOP_DISABLE (1UL << 3)
83 
84 #define I2S_RESET_ENABLE (1UL << 4)
85 #define I2S_RESET_DISABLE (0UL << 4)
86 
87 #define I2S_MUTE_ENABLE (1UL << 15)
88 #define I2S_MUTE_DISABLE (0UL << 15)
89 
95 #define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0))
96 #define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1))
97 #define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3))
98 #define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
99 
100 #define I2S_DAO_MONO ((uint32_t) (1 << 2))
101 
102 #define I2S_DAO_STOP ((uint32_t) (1 << 3))
103 
104 #define I2S_DAO_RESET ((uint32_t) (1 << 4))
105 
106 #define I2S_DAO_SLAVE ((uint32_t) (1 << 5))
107 
108 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))
109 #define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
110 
111 #define I2S_DAO_MUTE ((uint32_t) (1 << 15))
112 
118 #define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0))
119 #define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1))
120 #define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3))
121 #define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3))
122 
123 #define I2S_DAI_MONO ((uint32_t) (1 << 2))
124 
125 #define I2S_DAI_STOP ((uint32_t) (1 << 3))
126 
127 #define I2S_DAI_RESET ((uint32_t) (1 << 4))
128 
129 #define I2S_DAI_SLAVE ((uint32_t) (1 << 5))
130 
131 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))
132 #define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
133 
139 #define I2S_STATE_IRQ ((uint32_t) (1))
140 
141 #define I2S_STATE_DMA1 ((uint32_t) (1 << 1))
142 
143 #define I2S_STATE_DMA2 ((uint32_t) (1 << 2))
144 
145 #define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))
146 
147 #define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16))
148 
154 #define I2S_DMA1_RX_ENABLE ((uint32_t) (1))
155 
156 #define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1))
157 
158 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
159 
160 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
161 
167 #define I2S_DMA2_RX_ENABLE ((uint32_t) (1))
168 
169 #define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1))
170 
171 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
172 
173 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
174 
180 #define I2S_IRQ_RX_ENABLE ((uint32_t) (1))
181 
182 #define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1))
183 
184 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8))
185 #define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
186 
187 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16))
188 #define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
189 
195 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
196 
197 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
198 
199 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
200 
201 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
202 
207 #define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
208 #define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
209 
215 #define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
216 
217 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
218 
219 #define I2S_TXMODE_MCENA ((uint32_t) (1 << 3))
220 
221 #define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
222 
223 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
224 
225 #define I2S_RXMODE_MCENA ((uint32_t) (1 << 3))
226 
230 typedef enum {
234 
238 typedef enum {
242 
243 /**********************************************************************************
244  * I2S Init/DeInit functions
245  *********************************************************************************/
246 
252 void IP_I2S_Init(IP_I2S_001_Type *pI2S);
253 
260 void IP_I2S_DeInit(IP_I2S_001_Type *pI2S);
261 
262 /**********************************************************************************
263  * I2S configuration functions
264  *********************************************************************************/
265 
276 void IP_I2S_SetWordWidth(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t wordwidth);
277 
287 void IP_I2S_SetMono(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mono);
288 
298 void IP_I2S_SetMasterSlaveMode(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mode);
299 
309 void IP_I2S_SetBitRate(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mclk_divider);
310 
326 void IP_I2S_SetXYDivider(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider);
327 
337 void IP_I2S_SetWS_Halfperiod(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t ws_halfperiod);
338 
352 void IP_I2S_ModeConfig(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena);
353 
360 uint8_t IP_I2S_GetLevel(IP_I2S_001_Type *pI2S, uint8_t TRMode);
361 
362 /**********************************************************************************
363  * I2S operate functions
364  *********************************************************************************/
365 
373 void IP_I2S_Send(IP_I2S_001_Type *pI2S, uint32_t data);
374 
382 
389 void IP_I2S_Start(IP_I2S_001_Type *pI2S, uint8_t TRMode);
390 
397 void IP_I2S_Pause(IP_I2S_001_Type *pI2S, uint8_t TRMode);
398 
406 void IP_I2S_Mute(IP_I2S_001_Type *pI2S, FunctionalState NewState);
407 
415 void IP_I2S_Stop(IP_I2S_001_Type *pI2S, uint8_t TRMode);
416 
417 /**********************************************************************************
418  * I2S DMA functions
419  *********************************************************************************/
420 
432 void IP_I2S_SetFIFODepthDMA(IP_I2S_001_Type *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_Type DMANum, uint32_t depth);
433 
444 void IP_I2S_DMACmd(IP_I2S_001_Type *pI2S, IP_I2S_DMARequestNumber_Type DMANum, uint8_t TRMode, FunctionalState NewState);
445 
446 /**********************************************************************************
447  * I2S IRQ functions
448  *********************************************************************************/
449 
458 void IP_I2S_InterruptCmd(IP_I2S_001_Type *pI2S, uint8_t TRMode, FunctionalState NewState);
459 
467 void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t depth);
468 
475 Status IP_I2S_GetIntStatus(IP_I2S_001_Type *pI2S, uint8_t TRMode);
476 
481 #ifdef __cplusplus
482 }
483 #endif
484 
485 #endif /* __I2S_001_H_ */