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timer_001.h
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1 /*
2  * @brief 32-bit Timer/PWM registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __TIMER_001_H_
33 #define __TIMER_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
50 typedef struct {
51  __IO uint32_t IR;
52  __IO uint32_t TCR;
53  __IO uint32_t TC;
54  __IO uint32_t PR;
55  __IO uint32_t PC;
56  __IO uint32_t MCR;
57  __IO uint32_t MR[4];
58  __IO uint32_t CCR;
59  __IO uint32_t CR[4];
60  __IO uint32_t EMR;
61  __I uint32_t RESERVED0[12];
62  __IO uint32_t CTCR;
64 
66 #define TIMER_IR_CLR(n) _BIT(n)
67 
69 #define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
70 
71 #define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
72 
74 #define TIMER_ENABLE ((uint32_t) (1 << 0))
75 
76 #define TIMER_RESET ((uint32_t) (1 << 1))
77 
79 #define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
80 
81 #define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
82 
83 #define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
84 
86 #define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
87 
88 #define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
89 
90 #define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
91 
101 {
102  return (bool) ((timer->IR & TIMER_MATCH_INT(matchnum)) != 0);
103 }
104 
114 {
115  return (bool) ((timer->IR & TIMER_CAP_INT(capnum)) != 0);
116 }
117 
125 STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_Type *timer, int8_t matchnum)
126 {
127  timer->IR = TIMER_IR_CLR(matchnum);
128 }
129 
138 {
139  timer->IR = (0x10 << capnum);
140 }
141 
149 {
150  timer->TCR |= TIMER_ENABLE;
151 }
152 
160 {
161  timer->TCR &= ~TIMER_ENABLE;
162 }
163 
171 {
172  return timer->TC;
173 }
174 
182 {
183  return timer->PC;
184 }
185 
194 {
195  timer->PR = prescale;
196 }
197 
206 STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_Type *timer, int8_t matchnum, uint32_t matchval)
207 {
208  timer->MR[matchnum] = matchval;
209 }
210 
219 {
220  return timer->CR[capnum];
221 }
222 
228 void IP_TIMER_Reset(IP_TIMER_001_Type *timer);
229 
238 {
239  timer->MCR |= TIMER_INT_ON_MATCH(matchnum);
240 }
241 
249 {
250  timer->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
251 }
252 
260 {
261  timer->MCR |= TIMER_RESET_ON_MATCH(matchnum);
262 }
263 
271 {
272  timer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
273 }
274 
283 {
284  timer->MCR |= TIMER_STOP_ON_MATCH(matchnum);
285 }
286 
295 {
296  timer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
297 }
298 
308 {
309  timer->CCR |= TIMER_CAP_RISING(capnum);
310 }
311 
321 {
322  timer->CCR &= ~TIMER_CAP_RISING(capnum);
323 }
324 
334 {
335  timer->CCR |= TIMER_CAP_FALLING(capnum);
336 }
337 
347 {
348  timer->CCR &= ~TIMER_CAP_FALLING(capnum);
349 }
350 
360 {
361  timer->CCR |= TIMER_INT_ON_CAP(capnum);
362 }
363 
371 {
372  timer->CCR &= ~TIMER_INT_ON_CAP(capnum);
373 }
374 
378 typedef enum {
384 
395 void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_Type *timer, int8_t initial_state,
396  IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum);
397 
401 typedef enum {
407 
417  IP_TIMER_CAP_SRC_STATE_Type capSrc, int8_t capnum);
422 #ifdef __cplusplus
423 }
424 #endif
425 
426 #endif /* __TIMER_001_H_ */