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rgu_18xx_43xx.h
Go to the documentation of this file.
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/*
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* @brief LPC18xx/43xx Reset Generator Unit driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __RGU_18XX_43XX_H_
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#define __RGU_18XX_43XX_H_
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#include "
chip.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
enum
{
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RGU_CORE_RST
,
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RGU_PERIPH_RST
,
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RGU_MASTER_RST
,
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RGU_WWDT_RST
= 4,
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RGU_CREG_RST
,
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RGU_BUS_RST
= 8,
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RGU_SCU_RST
,
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RGU_M3_RST
= 13,
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RGU_LCD_RST
= 16,
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RGU_USB0_RST
,
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RGU_USB1_RST
,
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RGU_DMA_RST
,
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RGU_SDIO_RST
,
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RGU_EMC_RST
,
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RGU_ETHERNET_RST
,
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RGU_FLASHA_RST
= 25,
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RGU_EEPROM_RST
= 27,
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RGU_GPIO_RST
,
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RGU_FLASHB_RST
,
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RGU_TIMER0_RST
= 32,
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RGU_TIMER1_RST
,
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RGU_TIMER2_RST
,
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RGU_TIMER3_RST
,
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RGU_RITIMER_RST
,
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RGU_SCT_RST
,
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RGU_MOTOCONPWM_RST
,
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RGU_QEI_RST
,
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RGU_ADC0_RST
,
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RGU_ADC1_RST
,
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RGU_DAC_RST
,
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RGU_UART0_RST
= 44,
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RGU_UART1_RST
,
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RGU_UART2_RST
,
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RGU_UART3_RST
,
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RGU_I2C0_RST
,
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RGU_I2C1_RST
,
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RGU_SSP0_RST
,
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RGU_SSP1_RST
,
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RGU_I2S_RST
,
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RGU_SPIFI_RST
,
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RGU_CAN1_RST
,
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RGU_CAN0_RST
,
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#ifdef CHIP_LPC43XX
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RGU_M0APP_RST,
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RGU_SGPIO_RST,
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RGU_SPI_RST,
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#endif
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RGU_LAST_RST
= 63,
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}
RGU_RST_TYPE
;
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typedef
struct
{
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__I
uint32_t
RESERVED0[64];
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__O
uint32_t
RESET_CTRL0
;
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__O
uint32_t
RESET_CTRL1
;
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__I
uint32_t
RESERVED1[2];
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__IO
uint32_t
RESET_STATUS0
;
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__IO
uint32_t
RESET_STATUS1
;
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__IO
uint32_t
RESET_STATUS2
;
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__IO
uint32_t
RESET_STATUS3
;
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__I
uint32_t
RESERVED2[12];
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__I
uint32_t
RESET_ACTIVE_STATUS0
;
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__I
uint32_t
RESET_ACTIVE_STATUS1
;
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__I
uint32_t
RESERVED3[170];
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__IO
uint32_t
RESET_EXT_STAT[
RGU_LAST_RST
+ 1];
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}
LPC_RGU_T
;
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void
Chip_RGU_TriggerReset
(
RGU_RST_TYPE
ResetNumber);
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bool
Chip_RGU_InReset
(
RGU_RST_TYPE
ResetNumber);
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void
Chip_RGU_ClearReset
(
RGU_RST_TYPE
ResetNumber);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __RGU_18XX_43XX_H_ */
software
lpc_core
lpc_chip
chip_18xx_43xx
rgu_18xx_43xx.h
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