32 #ifndef __SDMMC_001_H_
33 #define __SDMMC_001_H_
35 #include "sys_config.h"
94 #define MCI_DMADES0_OWN (1UL << 31)
95 #define MCI_DMADES0_CES (1 << 30)
96 #define MCI_DMADES0_ER (1 << 5)
97 #define MCI_DMADES0_CH (1 << 4)
98 #define MCI_DMADES0_FS (1 << 3)
99 #define MCI_DMADES0_LD (1 << 2)
100 #define MCI_DMADES0_DIC (1 << 1)
104 #define MCI_DMADES1_BS1(x) (x)
105 #define MCI_DMADES1_BS2(x) ((x) << 13)
106 #define MCI_DMADES1_MAXTR 4096
110 #define MCI_CTRL_USE_INT_DMAC (1 << 25)
111 #define MCI_CTRL_CARDV_MASK (0x7 << 16)
112 #define MCI_CTRL_CEATA_INT_EN (1 << 11)
113 #define MCI_CTRL_SEND_AS_CCSD (1 << 10)
114 #define MCI_CTRL_SEND_CCSD (1 << 9)
115 #define MCI_CTRL_ABRT_READ_DATA (1 << 8)
116 #define MCI_CTRL_SEND_IRQ_RESP (1 << 7)
117 #define MCI_CTRL_READ_WAIT (1 << 6)
118 #define MCI_CTRL_INT_ENABLE (1 << 4)
119 #define MCI_CTRL_DMA_RESET (1 << 2)
120 #define MCI_CTRL_FIFO_RESET (1 << 1)
121 #define MCI_CTRL_RESET (1 << 0)
125 #define MCI_POWER_ENABLE 0x1
129 #define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8))
133 #define MCI_CLKSRC_CLKDIV0 0
134 #define MCI_CLKSRC_CLKDIV1 1
135 #define MCI_CLKSRC_CLKDIV2 2
136 #define MCI_CLKSRC_CLKDIV3 3
137 #define MCI_CLK_SOURCE(clksrc) (clksrc)
141 #define MCI_CLKEN_LOW_PWR (1 << 16)
142 #define MCI_CLKEN_ENABLE (1 << 0)
146 #define MCI_TMOUT_DATA(clks) ((clks) << 8)
147 #define MCI_TMOUT_DATA_MSK 0xFFFFFF00
148 #define MCI_TMOUT_RESP(clks) ((clks) & 0xFF)
149 #define MCI_TMOUT_RESP_MSK 0xFF
153 #define MCI_CTYPE_8BIT (1 << 16)
154 #define MCI_CTYPE_4BIT (1 << 0)
158 #define MCI_INT_SDIO (1 << 16)
159 #define MCI_INT_EBE (1 << 15)
160 #define MCI_INT_ACD (1 << 14)
161 #define MCI_INT_SBE (1 << 13)
162 #define MCI_INT_HLE (1 << 12)
163 #define MCI_INT_FRUN (1 << 11)
164 #define MCI_INT_HTO (1 << 10)
165 #define MCI_INT_DTO (1 << 9)
166 #define MCI_INT_RTO (1 << 8)
167 #define MCI_INT_DCRC (1 << 7)
168 #define MCI_INT_RCRC (1 << 6)
169 #define MCI_INT_RXDR (1 << 5)
170 #define MCI_INT_TXDR (1 << 4)
171 #define MCI_INT_DATA_OVER (1 << 3)
172 #define MCI_INT_CMD_DONE (1 << 2)
173 #define MCI_INT_RESP_ERR (1 << 1)
174 #define MCI_INT_CD (1 << 0)
178 #define MCI_CMD_START (1UL << 31)
179 #define MCI_CMD_VOLT_SWITCH (1 << 28)
180 #define MCI_CMD_BOOT_MODE (1 << 27)
181 #define MCI_CMD_DISABLE_BOOT (1 << 26)
182 #define MCI_CMD_EXPECT_BOOT_ACK (1 << 25)
183 #define MCI_CMD_ENABLE_BOOT (1 << 24)
184 #define MCI_CMD_CCS_EXP (1 << 23)
185 #define MCI_CMD_CEATA_RD (1 << 22)
186 #define MCI_CMD_UPD_CLK (1 << 21)
187 #define MCI_CMD_INIT (1 << 15)
188 #define MCI_CMD_STOP (1 << 14)
189 #define MCI_CMD_PRV_DAT_WAIT (1 << 13)
190 #define MCI_CMD_SEND_STOP (1 << 12)
191 #define MCI_CMD_STRM_MODE (1 << 11)
192 #define MCI_CMD_DAT_WR (1 << 10)
193 #define MCI_CMD_DAT_EXP (1 << 9)
194 #define MCI_CMD_RESP_CRC (1 << 8)
195 #define MCI_CMD_RESP_LONG (1 << 7)
196 #define MCI_CMD_RESP_EXP (1 << 6)
197 #define MCI_CMD_INDX(n) ((n) & 0x1F)
201 #define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
205 #define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
206 #define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
207 #define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
208 #define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
209 #define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
210 #define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
211 #define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
212 #define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
213 #define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
214 #define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
218 #define MCI_BMOD_PBL1 (0 << 8)
219 #define MCI_BMOD_PBL4 (1 << 8)
220 #define MCI_BMOD_PBL8 (2 << 8)
221 #define MCI_BMOD_PBL16 (3 << 8)
222 #define MCI_BMOD_PBL32 (4 << 8)
223 #define MCI_BMOD_PBL64 (5 << 8)
224 #define MCI_BMOD_PBL128 (6 << 8)
225 #define MCI_BMOD_PBL256 (7 << 8)
226 #define MCI_BMOD_DE (1 << 7)
227 #define MCI_BMOD_DSL(len) ((len) << 2)
228 #define MCI_BMOD_FB (1 << 1)
229 #define MCI_BMOD_SWR (1 << 0)
233 #define SD_FIFO_SZ 32
236 typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
255 typedef struct _sdif_device {