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IP: EMC register block and driver

Data Structures

struct  IP_EMC_001_Type
 External Memory Controller (EMC) register block structure. More...
 
struct  IP_EMC_DYN_DEVICE_CONFIG_Type
 EMC Dynamic Device Configuration structure used for IP drivers. More...
 
struct  IP_EMC_DYN_CONFIG_Type
 EMC Dynamic Configure Struct. More...
 
struct  IP_EMC_STATIC_CONFIG_Type
 EMC Static Configure Structure. More...
 

Macros

#define EMC_SUPPORT_ONLY_PL172
 EMC register support bitfields and mask.
 
#define EMC_CONFIG_ENDIAN_LITTLE   (0)
 
#define EMC_CONFIG_ENDIAN_BIG   (1)
 
#define EMC_CONFIG_BUFFER_ENABLE   (1 << 19)
 
#define EMC_CONFIG_WRITE_PROTECT   (1 << 20)
 
#define EMC_DYN_CONFIG_MD_BIT   (3)
 
#define EMC_DYN_CONFIG_MD_SDRAM   (0 << EMC_DYN_CONFIG_MD_BIT)
 
#define EMC_DYN_CONFIG_MD_LPSDRAM   (1 << EMC_DYN_CONFIG_MD_BIT)
 
#define EMC_DYN_CONFIG_LPSDRAM_BIT   (12)
 
#define EMC_DYN_CONFIG_LPSDRAM   (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_BIT   (9)
 
#define EMC_DYN_CONFIG_DEV_SIZE_16Mb   (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_64Mb   (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_BIT   (7)
 
#define EMC_DYN_CONFIG_DEV_BUS_8   (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_16   (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_32   (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)
 
#define EMC_DYN_CONFIG_DATA_BUS_16   (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
 
#define EMC_DYN_CONFIG_DATA_BUS_32   (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
 
#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS   ((0x0 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS   ((0x0 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS   ((0x1 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS   ((0x1 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS   ((0x1 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS   ((0x2 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS   ((0x3 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS   ((0x4 << 9) | (0x1 << 7))
 
#define EMC_DYN_MODE_BURST_LEN_BIT   (0)
 
#define EMC_DYN_MODE_BURST_LEN_1   (0)
 
#define EMC_DYN_MODE_BURST_LEN_2   (1)
 
#define EMC_DYN_MODE_BURST_LEN_4   (2)
 
#define EMC_DYN_MODE_BURST_LEN_8   (3)
 
#define EMC_DYN_MODE_BURST_LEN_FULL   (7)
 
#define EMC_DYN_MODE_BURST_TYPE_BIT   (3)
 
#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL   (0 << EMC_DYN_MODE_BURST_TYPE_BIT)
 
#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE   (1 << EMC_DYN_MODE_BURST_TYPE_BIT)
 
#define EMC_DYN_MODE_CAS_BIT   (4)
 
#define EMC_DYN_MODE_CAS_1   (1 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_CAS_2   (2 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_CAS_3   (3 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_OPMODE_BIT   (7)
 
#define EMC_DYN_MODE_OPMODE_STANDARD   (0 << EMC_DYN_MODE_OPMODE_BIT)
 
#define EMC_DYN_MODE_WBMODE_BIT   (9)
 
#define EMC_DYN_MODE_WBMODE_PROGRAMMED   (0 << EMC_DYN_MODE_WBMODE_BIT)
 
#define EMC_DYN_MODE_WBMODE_SINGLE_LOC   (1 << EMC_DYN_MODE_WBMODE_BIT)
 
#define EMC_DYN_CONTROL_DEEPSLEEP_BIT   (13)
 
#define EMC_DYN_CONTROL_ENABLE   (0x03)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_8   (0)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_16   (1)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_32   (2)
 
#define EMC_STATIC_CONFIG_PAGE_MODE_BIT   (3)
 
#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE   (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)
 
#define EMC_STATIC_CONFIG_CS_POL_BIT   (6)
 
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH   (1 << EMC_STATIC_CONFIG_CS_POL_BIT)
 
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW   (0 << EMC_STATIC_CONFIG_CS_POL_BIT)
 
#define EMC_STATIC_CONFIG_BLS_BIT   (7)
 
#define EMC_STATIC_CONFIG_BLS_HIGH   (1 << EMC_STATIC_CONFIG_BLS_BIT)
 
#define EMC_STATIC_CONFIG_BLS_LOW   (0 << EMC_STATIC_CONFIG_BLS_BIT)
 
#define EMC_STATIC_CONFIG_EW_BIT   (8)
 
#define EMC_STATIC_CONFIG_EW_ENABLE   (1 << EMC_STATIC_CONFIG_EW_BIT)
 
#define EMC_STATIC_CONFIG_EW_DISABLE   (0 << EMC_STATIC_CONFIG_EW_BIT)
 
#define Q24_8_FP(x)   ((x) * 256)
 
#define EMC_NANOSECOND(x)   Q24_8_FP(x)
 
#define EMC_CLOCK(x)   Q24_8_FP(-(x))
 

Functions

void IP_EMC_Dynamic_Init (IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock)
 Initializes the Dynamic Controller.
 
void IP_EMC_Dynamic_DeepSleepMode (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Set Deep Sleep Mode for Dynamic Memory Controller.
 
void IP_EMC_Dynamic_Enable (IP_EMC_001_Type *pEMC, uint8_t Enable)
 Enable Dynamic Memory Controller.
 
void IP_EMC_Static_Init (IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock)
 Initializes the Static Controller according to the specified parameters in the IP_EMC_STATIC_CONFIG_Type.
 
void IP_EMC_Mirror (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Mirror CS1 to CS0 and DYCS0.
 
void IP_EMC_Enable (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Enable EMC.
 
void IP_EMC_LowPowerMode (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Set EMC LowPower Mode.
 
void IP_EMC_Init (IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
 Initialize EMC.
 
void IP_EMC_SetStaticExtendedWait (IP_EMC_001_Type *pEMC, uint32_t Wait16Clks)
 Set Static Memory Extended Wait in Clock.
 

Detailed Description

External Memory Controller

Macro Definition Documentation

#define EMC_CLOCK (   x)    Q24_8_FP(-(x))

Definition at line 224 of file emc_001.h.

#define EMC_CONFIG_BUFFER_ENABLE   (1 << 19)

EMC Buffer enable bit in EMC Dynamic Configuration register

Definition at line 128 of file emc_001.h.

#define EMC_CONFIG_ENDIAN_BIG   (1)

Value for EMC to operate in Big Endian Mode

Definition at line 126 of file emc_001.h.

#define EMC_CONFIG_ENDIAN_LITTLE   (0)

Value for EMC to operate in Little Endian Mode

Definition at line 125 of file emc_001.h.

#define EMC_CONFIG_WRITE_PROTECT   (1 << 20)

EMC Write protect bit in EMC Dynamic Configuration register

Definition at line 129 of file emc_001.h.

#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))

Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns

Definition at line 165 of file emc_001.h.

#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))

Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns

Definition at line 161 of file emc_001.h.

#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS   ((0x0 << 9) | (0x1 << 7))

Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns

Definition at line 157 of file emc_001.h.

#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS   ((0x1 << 9) | (0x2 << 7))

Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns

Definition at line 160 of file emc_001.h.

#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS   ((0x0 << 9) | (0x0 << 7))

Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns

Definition at line 156 of file emc_001.h.

#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS   ((0x4 << 9) | (0x1 << 7))

Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns Dynamic Memory Mode Register Bit Definition

Definition at line 168 of file emc_001.h.

#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))

Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns

Definition at line 164 of file emc_001.h.

#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS   ((0x1 << 9) | (0x1 << 7))

Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns

Definition at line 159 of file emc_001.h.

#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS   ((0x2 << 9) | (0x2 << 7))

Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns

Definition at line 163 of file emc_001.h.

#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))

Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns

Definition at line 167 of file emc_001.h.

#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))

Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns

Definition at line 162 of file emc_001.h.

#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS   ((0x3 << 9) | (0x2 << 7))

Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns

Definition at line 166 of file emc_001.h.

#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS   ((0x1 << 9) | (0x0 << 7))

Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns

Definition at line 158 of file emc_001.h.

#define EMC_DYN_CONFIG_DATA_BUS_16   (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)

Device 16-bit data bus width value in EMC Dynamic Configuration register

Definition at line 152 of file emc_001.h.

#define EMC_DYN_CONFIG_DATA_BUS_32   (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)

Device 32-bit bus width value in EMC Dynamic Configuration register Memory configuration values in EMC Dynamic Configuration Register

Definition at line 153 of file emc_001.h.

#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)

Device data bus width starting bit in EMC Dynamic Configuration register

Definition at line 151 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_BUS_16   (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)

Device 16-bit bus width value in EMC Dynamic Configuration register

Definition at line 148 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_BUS_32   (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)

Device 32-bit bus width value in EMC Dynamic Configuration register

Definition at line 149 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_BUS_8   (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)

Device 8-bit bus width value in EMC Dynamic Configuration register

Definition at line 147 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_BUS_BIT   (7)

Device bus width starting bit in EMC Dynamic Configuration register

Definition at line 146 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

128Mb Device Size value in EMC Dynamic Configuration register

Definition at line 142 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_SIZE_16Mb   (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

16Mb Device Size value in EMC Dynamic Configuration register

Definition at line 140 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

256Mb Device Size value in EMC Dynamic Configuration register

Definition at line 143 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

512Mb Device Size value in EMC Dynamic Configuration register

Definition at line 144 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_SIZE_64Mb   (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

64Mb Device Size value in EMC Dynamic Configuration register

Definition at line 141 of file emc_001.h.

#define EMC_DYN_CONFIG_DEV_SIZE_BIT   (9)

Device Size starting bit in EMC Dynamic Configuration register

Definition at line 139 of file emc_001.h.

#define EMC_DYN_CONFIG_LPSDRAM   (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)

LPSDRAM value in EMC Dynamic Configuration register

Definition at line 137 of file emc_001.h.

#define EMC_DYN_CONFIG_LPSDRAM_BIT   (12)

LPSDRAM bit in EMC Dynamic Configuration register

Definition at line 136 of file emc_001.h.

#define EMC_DYN_CONFIG_MD_BIT   (3)

Memory device bit in EMC Dynamic Configuration register

Definition at line 132 of file emc_001.h.

#define EMC_DYN_CONFIG_MD_LPSDRAM   (1 << EMC_DYN_CONFIG_MD_BIT)

Select device as LPSDRAM in EMC Dynamic Configuration register

Definition at line 134 of file emc_001.h.

#define EMC_DYN_CONFIG_MD_SDRAM   (0 << EMC_DYN_CONFIG_MD_BIT)

Select device as SDRAM in EMC Dynamic Configuration register

Definition at line 133 of file emc_001.h.

#define EMC_DYN_CONTROL_DEEPSLEEP_BIT   (13)

Deep sleep Mode bit

Definition at line 198 of file emc_001.h.

#define EMC_DYN_CONTROL_ENABLE   (0x03)

Control Enable value Static Memory Configuration Register Bit Definitions

Definition at line 199 of file emc_001.h.

#define EMC_DYN_MODE_BURST_LEN_1   (0)

Value to set Burst Length to 1 in Dynamic Memory Mode Register

Definition at line 172 of file emc_001.h.

#define EMC_DYN_MODE_BURST_LEN_2   (1)

Value to set Burst Length to 2 in Dynamic Memory Mode Register

Definition at line 173 of file emc_001.h.

#define EMC_DYN_MODE_BURST_LEN_4   (2)

Value to set Burst Length to 4 in Dynamic Memory Mode Register

Definition at line 174 of file emc_001.h.

#define EMC_DYN_MODE_BURST_LEN_8   (3)

Value to set Burst Length to 8 in Dynamic Memory Mode Register

Definition at line 175 of file emc_001.h.

#define EMC_DYN_MODE_BURST_LEN_BIT   (0)

Starting bit No. of Burst Length in Dynamic Memory Mode Register

Definition at line 171 of file emc_001.h.

#define EMC_DYN_MODE_BURST_LEN_FULL   (7)

Value to set Burst Length to Full in Dynamic Memory Mode Register

Definition at line 176 of file emc_001.h.

#define EMC_DYN_MODE_BURST_TYPE_BIT   (3)

Burst Type bit in Dynamic Memory Mode Register

Definition at line 178 of file emc_001.h.

#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE   (1 << EMC_DYN_MODE_BURST_TYPE_BIT)

Burst Type Interleaved in Dynamic Memory Mode Register CAS Latency in Dynamic Mode Register

Definition at line 180 of file emc_001.h.

#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL   (0 << EMC_DYN_MODE_BURST_TYPE_BIT)

Burst Type Sequential in Dynamic Memory Mode Register

Definition at line 179 of file emc_001.h.

#define EMC_DYN_MODE_CAS_1   (1 << EMC_DYN_MODE_CAS_BIT)

value for CAS latency of 1 cycle

Definition at line 184 of file emc_001.h.

#define EMC_DYN_MODE_CAS_2   (2 << EMC_DYN_MODE_CAS_BIT)

value for CAS latency of 2 cycle

Definition at line 185 of file emc_001.h.

#define EMC_DYN_MODE_CAS_3   (3 << EMC_DYN_MODE_CAS_BIT)

value for CAS latency of 3 cycle Operation Mode in Dynamic Mode register

Definition at line 186 of file emc_001.h.

#define EMC_DYN_MODE_CAS_BIT   (4)

CAS latency starting bit in Dynamic Memory Mode register

Definition at line 183 of file emc_001.h.

#define EMC_DYN_MODE_OPMODE_BIT   (7)

Dynamic Mode Operation bit

Definition at line 189 of file emc_001.h.

#define EMC_DYN_MODE_OPMODE_STANDARD   (0 << EMC_DYN_MODE_OPMODE_BIT)

Value for Dynamic standard operation Mode Write Burst Mode in Dynamic Mode register

Definition at line 190 of file emc_001.h.

#define EMC_DYN_MODE_WBMODE_BIT   (9)

Write Burst Mode bit

Definition at line 193 of file emc_001.h.

#define EMC_DYN_MODE_WBMODE_PROGRAMMED   (0 << EMC_DYN_MODE_WBMODE_BIT)

Write Burst Mode programmed

Definition at line 194 of file emc_001.h.

#define EMC_DYN_MODE_WBMODE_SINGLE_LOC   (1 << EMC_DYN_MODE_WBMODE_BIT)

Write Burst Mode Single LOC Dynamic Memory Control Register Bit Definitions

Definition at line 195 of file emc_001.h.

#define EMC_NANOSECOND (   x)    Q24_8_FP(x)

Definition at line 223 of file emc_001.h.

#define EMC_STATIC_CONFIG_BLS_BIT   (7)

BLS Configuration bit No

Definition at line 213 of file emc_001.h.

#define EMC_STATIC_CONFIG_BLS_HIGH   (1 << EMC_STATIC_CONFIG_BLS_BIT)

BLS High Configuration value

Definition at line 214 of file emc_001.h.

#define EMC_STATIC_CONFIG_BLS_LOW   (0 << EMC_STATIC_CONFIG_BLS_BIT)

BLS Low Configuration value

Definition at line 215 of file emc_001.h.

#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH   (1 << EMC_STATIC_CONFIG_CS_POL_BIT)

Chip Select polarity - Active High

Definition at line 210 of file emc_001.h.

#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW   (0 << EMC_STATIC_CONFIG_CS_POL_BIT)

Chip Select polarity - Active Low

Definition at line 211 of file emc_001.h.

#define EMC_STATIC_CONFIG_CS_POL_BIT   (6)

Chip Select bit No

Definition at line 209 of file emc_001.h.

#define EMC_STATIC_CONFIG_EW_BIT   (8)

Ext Wait bit No

Definition at line 217 of file emc_001.h.

#define EMC_STATIC_CONFIG_EW_DISABLE   (0 << EMC_STATIC_CONFIG_EW_BIT)

Ext Wait Diabled value Q24.8 Fixed Point Helper

Definition at line 219 of file emc_001.h.

#define EMC_STATIC_CONFIG_EW_ENABLE   (1 << EMC_STATIC_CONFIG_EW_BIT)

Ext Wait Enabled value

Definition at line 218 of file emc_001.h.

#define EMC_STATIC_CONFIG_MEM_WIDTH_16   (1)

Static Memory Configuration - 16-bit width

Definition at line 203 of file emc_001.h.

#define EMC_STATIC_CONFIG_MEM_WIDTH_32   (2)

Static Memory Configuration - 32-bit width

Definition at line 204 of file emc_001.h.

#define EMC_STATIC_CONFIG_MEM_WIDTH_8   (0)

Static Memory Configuration - 8-bit width

Definition at line 202 of file emc_001.h.

#define EMC_STATIC_CONFIG_PAGE_MODE_BIT   (3)

Page Mode bit No

Definition at line 206 of file emc_001.h.

#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE   (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)

Value to enable Page Mode

Definition at line 207 of file emc_001.h.

#define EMC_SUPPORT_ONLY_PL172

EMC register support bitfields and mask.

Reserve for extending support to ARM9 or nextgen LPC

Definition at line 123 of file emc_001.h.

#define Q24_8_FP (   x)    ((x) * 256)

Definition at line 222 of file emc_001.h.

Function Documentation

void IP_EMC_Dynamic_DeepSleepMode ( IP_EMC_001_Type pEMC,
uint32_t  Enable 
)

Set Deep Sleep Mode for Dynamic Memory Controller.

Parameters
pEMC: Pointer to EMC peripheral
Enable: 1 = enter DeepSleep Mode, 0 = Normal Mode
Returns
None

Definition at line 192 of file emc_001.c.

void IP_EMC_Dynamic_Enable ( IP_EMC_001_Type pEMC,
uint8_t  Enable 
)

Enable Dynamic Memory Controller.

Parameters
pEMC: Pointer to EMC peripheral
Enable: 1 = Enable Dynamic Memory Controller, 0 = Disable
Returns
None

Definition at line 203 of file emc_001.c.

void IP_EMC_Dynamic_Init ( IP_EMC_001_Type pEMC,
IP_EMC_DYN_CONFIG_Type Dynamic_Config,
uint32_t  EMC_Clock 
)

Initializes the Dynamic Controller.

Parameters
pEMC: Pointer to EMC peripheral
Dynamic_Config: Dynamic Memory Configure Struct
EMC_Clock: Frequency of EMC Clock Out
Returns
None Initializes the Dynamic Controller according to the specified parameters in the IP_EMC_DYN_CONFIG_Type

Definition at line 107 of file emc_001.c.

void IP_EMC_Enable ( IP_EMC_001_Type pEMC,
uint32_t  Enable 
)

Enable EMC.

Parameters
pEMC: Pointer to EMC peripheral
Enable: 1 = Enable, 0 = Disable
Returns
None

Definition at line 240 of file emc_001.c.

void IP_EMC_Init ( IP_EMC_001_Type pEMC,
uint32_t  Enable,
uint32_t  ClockRatio,
uint32_t  EndianMode 
)

Initialize EMC.

Parameters
pEMC: Pointer to EMC peripheral
Enable: 1 = Enable, 0 = Disable
ClockRatio: clock out ratio, 0 = 1:1, 1 = 1:2
EndianMode: Endian Mode, 0 = Little, 1 = Big
Returns
None

Definition at line 262 of file emc_001.c.

void IP_EMC_LowPowerMode ( IP_EMC_001_Type pEMC,
uint32_t  Enable 
)

Set EMC LowPower Mode.

Parameters
pEMC: Pointer to EMC peripheral
Enable: 1 = Enable, 0 = Disable
Returns
None

Definition at line 251 of file emc_001.c.

void IP_EMC_Mirror ( IP_EMC_001_Type pEMC,
uint32_t  Enable 
)

Mirror CS1 to CS0 and DYCS0.

Parameters
pEMC: Pointer to EMC peripheral
Enable: 1 = Mirror, 0 = Normal Memory Map
Returns
None

Definition at line 229 of file emc_001.c.

void IP_EMC_SetStaticExtendedWait ( IP_EMC_001_Type pEMC,
uint32_t  Wait16Clks 
)

Set Static Memory Extended Wait in Clock.

Parameters
pEMC: Pointer to EMC peripheral
Wait16Clks: Number of '16 clock' delay cycles
Returns
None

Definition at line 271 of file emc_001.c.

void IP_EMC_Static_Init ( IP_EMC_001_Type pEMC,
IP_EMC_STATIC_CONFIG_Type Static_Config,
uint32_t  EMC_Clock 
)

Initializes the Static Controller according to the specified parameters in the IP_EMC_STATIC_CONFIG_Type.

Parameters
pEMC: Pointer to EMC peripheral
Static_Config: Static Memory Configure Struct
EMC_Clock: Frequency of EMC Clock Out
Returns
None

Definition at line 216 of file emc_001.c.