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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Data Structures | |
struct | IP_SSP_001_Type |
SSP register block structure. More... | |
Macros | |
#define | SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF)) |
#define | SSP_CR0_FRF_SPI ((uint32_t) (0 << 4)) |
#define | SSP_CR0_FRF_TI ((uint32_t) (1 << 4)) |
#define | SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4)) |
#define | SSP_CR0_CPOL_LO ((uint32_t) (0)) |
#define | SSP_CR0_CPOL_HI ((uint32_t) (1 << 6)) |
#define | SSP_CR0_CPHA_FIRST ((uint32_t) (0)) |
#define | SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7)) |
#define | SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) |
#define | SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) |
#define | SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) |
#define | SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) |
#define | SSP_CR1_LBM_EN ((uint32_t) (1 << 0)) |
#define | SSP_CR1_SSP_EN ((uint32_t) (1 << 1)) |
#define | SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2)) |
#define | SSP_CR1_MASTER_EN ((uint32_t) (0)) |
#define | SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3)) |
#define | SSP_CR1_BITMASK ((uint32_t) (0x0F)) |
#define | SSP_CPSR_BITMASK ((uint32_t) (0xFF)) |
#define | SSP_DR_BITMASK(n) ((n) & 0xFFFF) |
#define | SSP_SR_BITMASK ((uint32_t) (0x1F)) |
#define | SSP_ICR_BITMASK ((uint32_t) (0x03)) |
Enumerations | |
enum | SSP_Status_Type { SSP_STAT_TFE = ((uint32_t)(1 << 0)), SSP_STAT_TNF = ((uint32_t)(1 << 1)), SSP_STAT_RNE = ((uint32_t)(1 << 2)), SSP_STAT_RFF = ((uint32_t)(1 << 3)), SSP_STAT_BSY = ((uint32_t)(1 << 4)) } |
SSP Type of Status. More... | |
enum | SSP_Int_Mask_Type { SSP_RORIM = ((uint32_t)(1 << 0)), SSP_RTIM = ((uint32_t)(1 << 1)), SSP_RXIM = ((uint32_t)(1 << 2)), SSP_TXIM = ((uint32_t)(1 << 3)), SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)) } |
SSP Type of Interrupt Mask. More... | |
enum | SSP_Mask_Int_Status_Type { SSP_RORMIS = ((uint32_t)(1 << 0)), SSP_RTMIS = ((uint32_t)(1 << 1)), SSP_RXMIS = ((uint32_t)(1 << 2)), SSP_TXMIS = ((uint32_t)(1 << 3)), SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)) } |
SSP Type of Mask Interrupt Status. More... | |
enum | SSP_Raw_Int_Status_Type { SSP_RORRIS = ((uint32_t)(1 << 0)), SSP_RTRIS = ((uint32_t)(1 << 1)), SSP_RXRIS = ((uint32_t)(1 << 2)), SSP_TXRIS = ((uint32_t)(1 << 3)), SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)) } |
SSP Type of Raw Interrupt Status. More... | |
enum | SSP_Int_Clear_Type { SSP_RORIC = 0x0, SSP_RTIC = 0x1, SSP_INT_CLEAR_BITMASK = 0x3 } |
enum | SSP_DMA_Type { SSP_DMA_RX = (1u), SSP_DMA_TX = (1u << 1) } |
Functions | |
void | IP_SSP_DeInit (IP_SSP_001_Type *pSSP) |
Disable SSP operation. | |
void | IP_SSP_Cmd (IP_SSP_001_Type *pSSP, FunctionalState NewState) |
Enable/Disable SSP operation. | |
void | IP_SSP_LoopBackCmd (IP_SSP_001_Type *pSSP, FunctionalState NewState) |
Enable/Disable loopback mode. | |
FlagStatus | IP_SSP_GetStatus (IP_SSP_001_Type *pSSP, SSP_Status_Type Stat) |
Get the current status of SSP controller. | |
uint32_t | IP_SSP_GetIntStatus (IP_SSP_001_Type *pSSP) |
Get the masked interrupt status. | |
IntStatus | IP_SSP_GetRawIntStatus (IP_SSP_001_Type *pSSP, SSP_Raw_Int_Status_Type RawInt) |
Get the raw interrupt status. | |
uint8_t | IP_SSP_GetDataSize (IP_SSP_001_Type *pSSP) |
Get the number of bits transferred in each frame. | |
void | IP_SSP_ClearIntPending (IP_SSP_001_Type *pSSP, SSP_Int_Clear_Type IntClear) |
Clear the corresponding interrupt condition(s) in the SSP controller. | |
void | IP_SSP_Int_Enable (IP_SSP_001_Type *pSSP, SSP_Int_Mask_Type IntType, FunctionalState NewState) |
Enable/Disable interrupt for the SSP. | |
uint16_t | IP_SSP_ReceiveFrame (IP_SSP_001_Type *pSSP) |
Get received SSP data. | |
void | IP_SSP_SendFrame (IP_SSP_001_Type *pSSP, uint16_t tx_data) |
Send SSP 16-bit data. | |
void | IP_SSP_Set_ClockRate (IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale) |
Set up output clocks per bit for SSP bus. | |
void | IP_SSP_Set_Format (IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat) |
Set up the SSP frame format. | |
void | IP_SSP_Set_Mode (IP_SSP_001_Type *pSSP, uint32_t mode) |
Set the SSP working as master or slave mode. | |
void | IP_SSP_DMA_Cmd (IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState) |
Enable/Disable DMA for SSP. | |
#define SSP_CPSR_BITMASK ((uint32_t) (0xFF)) |
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) |
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) |
#define SSP_CR0_CPHA_FIRST ((uint32_t) (0)) |
#define SSP_CR0_CPOL_LO ((uint32_t) (0)) |
#define SSP_CR0_DSS | ( | n | ) | ((uint32_t) ((n) & 0xF)) |
#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4)) |
#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4)) |
#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4)) |
#define SSP_CR0_SCR | ( | n | ) | ((uint32_t) ((n & 0xFF) << 8)) |
#define SSP_CR0_SCR | ( | n | ) | ((uint32_t) ((n & 0xFF) << 8)) |
#define SSP_CR1_BITMASK ((uint32_t) (0x0F)) |
#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0)) |
#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2)) |
#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3)) |
#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1)) |
#define SSP_DR_BITMASK | ( | n | ) | ((n) & 0xFFFF) |
#define SSP_SR_BITMASK ((uint32_t) (0x1F)) |
enum SSP_DMA_Type |
enum SSP_Int_Clear_Type |
enum SSP_Int_Mask_Type |
enum SSP_Status_Type |
void IP_SSP_ClearIntPending | ( | IP_SSP_001_Type * | pSSP, |
SSP_Int_Clear_Type | IntClear | ||
) |
Clear the corresponding interrupt condition(s) in the SSP controller.
pSSP | : The base of SSP peripheral on the chip |
IntClear,: | Type of cleared interrupt, should be :
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void IP_SSP_Cmd | ( | IP_SSP_001_Type * | pSSP, |
FunctionalState | NewState | ||
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void IP_SSP_DeInit | ( | IP_SSP_001_Type * | pSSP | ) |
void IP_SSP_DMA_Cmd | ( | IP_SSP_001_Type * | pSSP, |
SSP_DMA_Type | ssp_dma_t, | ||
FunctionalState | NewState | ||
) |
uint8_t IP_SSP_GetDataSize | ( | IP_SSP_001_Type * | pSSP | ) |
uint32_t IP_SSP_GetIntStatus | ( | IP_SSP_001_Type * | pSSP | ) |
IntStatus IP_SSP_GetRawIntStatus | ( | IP_SSP_001_Type * | pSSP, |
SSP_Raw_Int_Status_Type | RawInt | ||
) |
Get the raw interrupt status.
pSSP | : The base of SSP peripheral on the chip |
RawInt | : Interrupt condition to be get status, shoud be :
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FlagStatus IP_SSP_GetStatus | ( | IP_SSP_001_Type * | pSSP, |
SSP_Status_Type | Stat | ||
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void IP_SSP_Int_Enable | ( | IP_SSP_001_Type * | pSSP, |
SSP_Int_Mask_Type | IntType, | ||
FunctionalState | NewState | ||
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void IP_SSP_LoopBackCmd | ( | IP_SSP_001_Type * | pSSP, |
FunctionalState | NewState | ||
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uint16_t IP_SSP_ReceiveFrame | ( | IP_SSP_001_Type * | pSSP | ) |
void IP_SSP_SendFrame | ( | IP_SSP_001_Type * | pSSP, |
uint16_t | tx_data | ||
) |
void IP_SSP_Set_ClockRate | ( | IP_SSP_001_Type * | pSSP, |
uint32_t | clk_rate, | ||
uint32_t | prescale | ||
) |
Set up output clocks per bit for SSP bus.
pSSP | : The base of SSP peripheral on the chip |
clk_rate | fs: The number of prescaler-output clocks per bit on the bus, minus one |
prescale | : The factor by which the Prescaler divides the SSP peripheral clock PCLK |
void IP_SSP_Set_Format | ( | IP_SSP_001_Type * | pSSP, |
uint32_t | bits, | ||
uint32_t | frameFormat, | ||
uint32_t | clockFormat | ||
) |
Set up the SSP frame format.
pSSP | : The base of SSP peripheral on the chip |
bits | : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16 |
frameFormat | : Frame format, should be :
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clockFormat | : Select Clock polarity and Clock phase, should be :
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void IP_SSP_Set_Mode | ( | IP_SSP_001_Type * | pSSP, |
uint32_t | mode | ||
) |