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gpdma_001.c
Go to the documentation of this file.
1
/*
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* @brief GPDMA Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "
gpdma_001.h
"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Initialize the GPDMA */
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void
IP_GPDMA_Init
(
IP_GPDMA_001_Type
*pGPDMA) {
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uint8_t i;
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/* Reset all channel configuration register */
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for
(i = 8; i > 0; i--) {
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pGPDMA->
CH
[i - 1].
CONFIG
= 0;
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}
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/* Clear all DMA interrupt and error flag */
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pGPDMA->
INTTCCLEAR
= 0xFF;
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pGPDMA->
INTERRCLR
= 0xFF;
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}
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/* Read the status from different registers according to the type */
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IntStatus
IP_GPDMA_IntGetStatus
(
IP_GPDMA_001_Type
*pGPDMA,
GPDMA_Status_Type
type, uint8_t channel) {
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switch
(type) {
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case
GPDMA_STAT_INT
:
/* check status of DMA channel interrupts */
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return
(
IntStatus
) (pGPDMA->
INTSTAT
& (((1UL << channel) & 0xFF)));
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case
GPDMA_STAT_INTTC
:
/* check terminal count interrupt request status for DMA */
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return
(
IntStatus
) (pGPDMA->
INTTCSTAT
& (((1UL << channel) & 0xFF)));
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case
GPDMA_STAT_INTERR
:
/* check interrupt status for DMA channels */
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return
(
IntStatus
) (pGPDMA->
INTERRSTAT
& (((1UL << channel) & 0xFF)));
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case
GPDMA_STAT_RAWINTTC
:
/* check status of the terminal count interrupt for DMA channels */
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return
(
IntStatus
) (pGPDMA->
RAWINTTCSTAT
& (((1UL << channel) & 0xFF)));
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case
GPDMA_STAT_RAWINTERR
:
/* check status of the error interrupt for DMA channels */
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return
(
IntStatus
) (pGPDMA->
RAWINTERRSTAT
& (((1UL << channel) & 0xFF)));
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default
:
/* check enable status for DMA channels */
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return
(
IntStatus
) (pGPDMA->
ENBLDCHNS
& (((1UL << channel) & 0xFF)));
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}
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}
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/* Clear the Interrupt Flag from different registers according to the type */
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void
IP_GPDMA_ClearIntPending
(
IP_GPDMA_001_Type
*pGPDMA,
GPDMA_StateClear_Type
type, uint8_t channel) {
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if
(type ==
GPDMA_STATCLR_INTTC
) {
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/* clears the terminal count interrupt request on DMA channel */
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pGPDMA->
INTTCCLEAR
= (((1UL << (channel)) & 0xFF));
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}
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else
{
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/* clear the error interrupt request */
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pGPDMA->
INTERRCLR
= (((1UL << (channel)) & 0xFF));
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}
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}
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/* Enable or Disable the GPDMA Channel */
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void
IP_GPDMA_ChannelCmd
(
IP_GPDMA_001_Type
*pGPDMA, uint8_t channelNum,
FunctionalState
NewState) {
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IP_GPDMA_001_CH_Type
*pDMAch;
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/* Get Channel pointer */
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pDMAch = (
IP_GPDMA_001_CH_Type
*) &(pGPDMA->
CH
[channelNum]);
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if
(NewState ==
ENABLE
) {
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pDMAch->
CONFIG
|=
GPDMA_DMACCxConfig_E
;
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}
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else
{
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pDMAch->
CONFIG
&= ~
GPDMA_DMACCxConfig_E
;
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}
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}
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/* Set up the DPDMA according to the specification configuration details */
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Status
IP_GPDMA_Setup
(
IP_GPDMA_001_Type
*pGPDMA,
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GPDMA_Channel_CFG_Type
*GPDMAChannelConfig,
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uint32_t
GPDMA_LUTPerBurstSrcConn,
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uint32_t
GPDMA_LUTPerBurstDstConn,
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uint32_t
GPDMA_LUTPerWidSrcConn,
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uint32_t
GPDMA_LUTPerWidDstConn,
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uint32_t
GPDMA_LUTPerAddrSrcConn,
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uint32_t
GPDMA_LUTPerAddrDstConn,
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uint8_t SrcPeripheral,
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uint8_t DstPeripheral)
127
{
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IP_GPDMA_001_CH_Type
*pDMAch;
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130
if
(pGPDMA->
ENBLDCHNS
& ((((1UL << (GPDMAChannelConfig->
ChannelNum
)) & 0xFF)))) {
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/* This channel is enabled, return ERROR, need to release this channel first */
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return
ERROR
;
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}
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/* Get Channel pointer */
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pDMAch = (
IP_GPDMA_001_CH_Type
*) &(pGPDMA->
CH
[GPDMAChannelConfig->
ChannelNum
]);
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/* Reset the Interrupt status */
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pGPDMA->
INTTCCLEAR
= (((1UL << (GPDMAChannelConfig->
ChannelNum
)) & 0xFF));
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pGPDMA->
INTERRCLR
= (((1UL << (GPDMAChannelConfig->
ChannelNum
)) & 0xFF));
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/* Assign Linker List Item value */
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pDMAch->
LLI
= 0;
/* Fixed to 0 (no link list) */
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/* Enable DMA channels, little endian */
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pGPDMA->
CONFIG
=
GPDMA_DMACConfig_E
;
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while
(!(pGPDMA->
CONFIG
&
GPDMA_DMACConfig_E
)) {}
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pDMAch->
SRCADDR
= GPDMAChannelConfig->
SrcAddr
;
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pDMAch->
DESTADDR
= GPDMAChannelConfig->
DstAddr
;
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/* Configure DMA Channel, enable Error Counter and Terminate counter */
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pDMAch->
CONFIG
=
GPDMA_DMACCxConfig_IE
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|
GPDMA_DMACCxConfig_ITC
/*| GPDMA_DMACCxConfig_E*/
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|
GPDMA_DMACCxConfig_TransferType
((
uint32_t
) GPDMAChannelConfig->
TransferType
)
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|
GPDMA_DMACCxConfig_SrcPeripheral
(SrcPeripheral)
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|
GPDMA_DMACCxConfig_DestPeripheral
(DstPeripheral);
158
159
switch
(GPDMAChannelConfig->
TransferType
) {
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/* Memory to memory */
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case
GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
:
162
pDMAch->
CONTROL
=
GPDMA_DMACCxControl_TransferSize
(GPDMAChannelConfig->
TransferSize
)
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|
GPDMA_DMACCxControl_SBSize
((4UL))
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|
GPDMA_DMACCxControl_DBSize
((4UL))
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|
GPDMA_DMACCxControl_SWidth
(GPDMAChannelConfig->
TransferWidth
)
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|
GPDMA_DMACCxControl_DWidth
(GPDMAChannelConfig->
TransferWidth
)
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|
GPDMA_DMACCxControl_SI
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|
GPDMA_DMACCxControl_DI
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|
GPDMA_DMACCxControl_I
;
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break
;
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case
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
:
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case
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
:
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pDMAch->
CONTROL
=
GPDMA_DMACCxControl_TransferSize
((
uint32_t
) GPDMAChannelConfig->
TransferSize
)
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|
GPDMA_DMACCxControl_SBSize
(GPDMA_LUTPerBurstDstConn)
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|
GPDMA_DMACCxControl_DBSize
(GPDMA_LUTPerBurstDstConn)
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|
GPDMA_DMACCxControl_SWidth
(GPDMA_LUTPerWidDstConn)
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|
GPDMA_DMACCxControl_DWidth
(GPDMA_LUTPerWidDstConn)
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|
GPDMA_DMACCxControl_DestTransUseAHBMaster1
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|
GPDMA_DMACCxControl_SI
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|
GPDMA_DMACCxControl_I
;
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break
;
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case
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
:
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case
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
:
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pDMAch->
CONTROL
=
GPDMA_DMACCxControl_TransferSize
((
uint32_t
) GPDMAChannelConfig->
TransferSize
)
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|
GPDMA_DMACCxControl_SBSize
(GPDMA_LUTPerBurstSrcConn)
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|
GPDMA_DMACCxControl_DBSize
(GPDMA_LUTPerBurstSrcConn)
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|
GPDMA_DMACCxControl_SWidth
(GPDMA_LUTPerWidSrcConn)
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|
GPDMA_DMACCxControl_DWidth
(GPDMA_LUTPerWidSrcConn)
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|
GPDMA_DMACCxControl_SrcTransUseAHBMaster1
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|
GPDMA_DMACCxControl_DI
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|
GPDMA_DMACCxControl_I
;
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break
;
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case
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
:
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case
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
:
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case
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
:
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pDMAch->
CONTROL
=
GPDMA_DMACCxControl_TransferSize
((
uint32_t
) GPDMAChannelConfig->
TransferSize
)
200
|
GPDMA_DMACCxControl_SBSize
(GPDMA_LUTPerBurstSrcConn)
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|
GPDMA_DMACCxControl_DBSize
(GPDMA_LUTPerBurstDstConn)
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|
GPDMA_DMACCxControl_SWidth
(GPDMA_LUTPerWidSrcConn)
203
|
GPDMA_DMACCxControl_DWidth
(GPDMA_LUTPerWidDstConn)
204
|
GPDMA_DMACCxControl_SrcTransUseAHBMaster1
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|
GPDMA_DMACCxControl_DestTransUseAHBMaster1
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|
GPDMA_DMACCxControl_I
;
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break
;
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/* Do not support any more transfer type, return ERROR */
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default
:
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return
ERROR
;
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}
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return
SUCCESS
;
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}
software
lpc_core
lpc_ip
gpdma_001.c
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