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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Data Structures | |
struct | IP_GPDMA_001_CH_Type |
GPDMA Channel register block structure. More... | |
struct | IP_GPDMA_001_Type |
GPDMA register block. More... | |
struct | GPDMA_Channel_CFG_Type |
GPDMA structure using for DMA configuration. More... | |
Macros | |
#define | GPDMA_CHANNELS 8 |
#define | GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) |
Macro defines for DMA channel control registers. | |
#define | GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) |
#define | GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) |
#define | GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) |
#define | GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) |
#define | GPDMA_DMACCxControl_SI ((1UL << 26)) |
#define | GPDMA_DMACCxControl_DI ((1UL << 27)) |
#define | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0 |
#define | GPDMA_DMACCxControl_DestTransUseAHBMaster1 0 |
#define | GPDMA_DMACCxControl_Prot1 ((1UL << 28)) |
#define | GPDMA_DMACCxControl_Prot2 ((1UL << 29)) |
#define | GPDMA_DMACCxControl_Prot3 ((1UL << 30)) |
#define | GPDMA_DMACCxControl_I ((1UL << 31)) |
#define | GPDMA_DMACConfig_E ((0x01)) |
Macro defines for DMA Configuration register. | |
#define | GPDMA_DMACConfig_M ((0x02)) |
#define | GPDMA_DMACConfig_BITMASK ((0x03)) |
#define | GPDMA_DMACCxConfig_E ((1UL << 0)) |
Macro defines for DMA Channel Configuration registers. | |
#define | GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) |
#define | GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) |
#define | GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) |
#define | GPDMA_DMACCxConfig_IE ((1UL << 14)) |
#define | GPDMA_DMACCxConfig_ITC ((1UL << 15)) |
#define | GPDMA_DMACCxConfig_L ((1UL << 16)) |
#define | GPDMA_DMACCxConfig_A ((1UL << 17)) |
#define | GPDMA_DMACCxConfig_H ((1UL << 18)) |
Enumerations | |
enum | GPDMA_StateClear_Type { GPDMA_STATCLR_INTTC, GPDMA_STATCLR_INTERR } |
GPDMA Interrupt Clear Status. More... | |
enum | GPDMA_Status_Type { GPDMA_STAT_INT, GPDMA_STAT_INTTC, GPDMA_STAT_INTERR, GPDMA_STAT_RAWINTTC, GPDMA_STAT_RAWINTERR, GPDMA_STAT_ENABLED_CH } |
GPDMA Type of Interrupt Status. More... | |
enum | FlowControlType { GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) } |
GPDMA Type of DMA controller. More... | |
Functions | |
void | IP_GPDMA_Init (IP_GPDMA_001_Type *pGPDMA) |
Initialize the GPDMA. | |
Status | IP_GPDMA_Setup (IP_GPDMA_001_Type *pGPDMA, GPDMA_Channel_CFG_Type *GPDMAChannelConfig, uint32_t GPDMA_LUTPerBurstSrcConn, uint32_t GPDMA_LUTPerBurstDstConn, uint32_t GPDMA_LUTPerWidSrcConn, uint32_t GPDMA_LUTPerWidDstConn, uint32_t GPDMA_LUTPerAddrSrcConn, uint32_t GPDMA_LUTPerAddrDstConn, uint8_t SrcPeripheral, uint8_t DstPeripheral) |
Set up the DPDMA according to the specification configuration details. | |
IntStatus | IP_GPDMA_IntGetStatus (IP_GPDMA_001_Type *pGPDMA, GPDMA_Status_Type type, uint8_t channel) |
Read the status from different registers according to the type. | |
void | IP_GPDMA_ClearIntPending (IP_GPDMA_001_Type *pGPDMA, GPDMA_StateClear_Type type, uint8_t channel) |
Clear the Interrupt Flag from different registers according to the type. | |
void | IP_GPDMA_ChannelCmd (IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState) |
Enable or Disable the GPDMA Channel. | |
General Purpose DMA
#define GPDMA_CHANNELS 8 |
Definition at line 60 of file gpdma_001.h.
#define GPDMA_DMACConfig_BITMASK ((0x03)) |
Definition at line 111 of file gpdma_001.h.
#define GPDMA_DMACConfig_E ((0x01)) |
Macro defines for DMA Configuration register.
DMA Controller enable
Definition at line 109 of file gpdma_001.h.
#define GPDMA_DMACConfig_M ((0x02)) |
AHB Master endianness configuration
Definition at line 110 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_A ((1UL << 17)) |
Active
Definition at line 123 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_DestPeripheral | ( | n | ) | (((n & 0x1F) << 6)) |
Destination peripheral
Definition at line 118 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_E ((1UL << 0)) |
Macro defines for DMA Channel Configuration registers.
DMA control enable
Definition at line 116 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_H ((1UL << 18)) |
Halt
Definition at line 124 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_IE ((1UL << 14)) |
Interrupt error mask
Definition at line 120 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) |
Terminal count interrupt mask
Definition at line 121 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_L ((1UL << 16)) |
Lock
Definition at line 122 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_SrcPeripheral | ( | n | ) | (((n & 0x1F) << 1)) |
Source peripheral
Definition at line 117 of file gpdma_001.h.
#define GPDMA_DMACCxConfig_TransferType | ( | n | ) | (((n & 0x7) << 11)) |
This value indicates the type of transfer
Definition at line 119 of file gpdma_001.h.
#define GPDMA_DMACCxControl_DBSize | ( | n | ) | (((n & 0x07) << 15)) |
Destination burst size
Definition at line 89 of file gpdma_001.h.
#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0 |
Definition at line 99 of file gpdma_001.h.
#define GPDMA_DMACCxControl_DI ((1UL << 27)) |
Destination increment
Definition at line 93 of file gpdma_001.h.
#define GPDMA_DMACCxControl_DWidth | ( | n | ) | (((n & 0x07) << 21)) |
Destination transfer width
Definition at line 91 of file gpdma_001.h.
#define GPDMA_DMACCxControl_I ((1UL << 31)) |
Terminal count interrupt enable bit
Definition at line 104 of file gpdma_001.h.
#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) |
Indicates that the access is in user mode or privileged mode
Definition at line 101 of file gpdma_001.h.
#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) |
Indicates that the access is bufferable or not bufferable
Definition at line 102 of file gpdma_001.h.
#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) |
Indicates that the access is cacheable or not cacheable
Definition at line 103 of file gpdma_001.h.
#define GPDMA_DMACCxControl_SBSize | ( | n | ) | (((n & 0x07) << 12)) |
Source burst size
Definition at line 88 of file gpdma_001.h.
#define GPDMA_DMACCxControl_SI ((1UL << 26)) |
Source increment
Definition at line 92 of file gpdma_001.h.
#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0 |
Definition at line 98 of file gpdma_001.h.
#define GPDMA_DMACCxControl_SWidth | ( | n | ) | (((n & 0x07) << 18)) |
Source transfer width
Definition at line 90 of file gpdma_001.h.
#define GPDMA_DMACCxControl_TransferSize | ( | n | ) | (((n & 0xFFF) << 0)) |
Macro defines for DMA channel control registers.
Transfer size
Definition at line 87 of file gpdma_001.h.
enum FlowControlType |
GPDMA Type of DMA controller.
Definition at line 149 of file gpdma_001.h.
GPDMA Interrupt Clear Status.
GPDMA_STATCLR_INTTC |
GPDMA Interrupt Terminal Count Request Clear |
GPDMA_STATCLR_INTERR |
GPDMA Interrupt Error Clear |
Definition at line 129 of file gpdma_001.h.
enum GPDMA_Status_Type |
GPDMA Type of Interrupt Status.
Definition at line 137 of file gpdma_001.h.
void IP_GPDMA_ChannelCmd | ( | IP_GPDMA_001_Type * | pGPDMA, |
uint8_t | channelNum, | ||
FunctionalState | NewState | ||
) |
Enable or Disable the GPDMA Channel.
pGPDMA | : The Base Address of GPDMA on the chip |
channelNum | : The GPDMA channel : 0 - 7 |
NewState | : ENABLE to enable GPDMA or DISABLE to disable GPDMA |
Definition at line 102 of file gpdma_001.c.
void IP_GPDMA_ClearIntPending | ( | IP_GPDMA_001_Type * | pGPDMA, |
GPDMA_StateClear_Type | type, | ||
uint8_t | channel | ||
) |
Clear the Interrupt Flag from different registers according to the type.
pGPDMA | : The Base Address of GPDMA on the chip |
type | : Flag mode, should be:
|
channel | : The GPDMA channel : 0 - 7 |
Definition at line 90 of file gpdma_001.c.
void IP_GPDMA_Init | ( | IP_GPDMA_001_Type * | pGPDMA | ) |
Initialize the GPDMA.
pGPDMA | : The Base Address of GPDMA on the chip |
Definition at line 51 of file gpdma_001.c.
IntStatus IP_GPDMA_IntGetStatus | ( | IP_GPDMA_001_Type * | pGPDMA, |
GPDMA_Status_Type | type, | ||
uint8_t | channel | ||
) |
Read the status from different registers according to the type.
pGPDMA | : The Base Address of GPDMA on the chip |
type | : Status mode, should be:
|
channel | : The GPDMA channel : 0 - 7 |
TODO check the channel <=8 type is esxited
Definition at line 64 of file gpdma_001.c.
Status IP_GPDMA_Setup | ( | IP_GPDMA_001_Type * | pGPDMA, |
GPDMA_Channel_CFG_Type * | GPDMAChannelConfig, | ||
uint32_t | GPDMA_LUTPerBurstSrcConn, | ||
uint32_t | GPDMA_LUTPerBurstDstConn, | ||
uint32_t | GPDMA_LUTPerWidSrcConn, | ||
uint32_t | GPDMA_LUTPerWidDstConn, | ||
uint32_t | GPDMA_LUTPerAddrSrcConn, | ||
uint32_t | GPDMA_LUTPerAddrDstConn, | ||
uint8_t | SrcPeripheral, | ||
uint8_t | DstPeripheral | ||
) |
Set up the DPDMA according to the specification configuration details.
pGPDMA | : The Base Address of GPDMA on the chip |
GPDMAChannelConfig | : Configuration struct |
GPDMA_LUTPerBurstSrcConn | : Peripheral Source burst size |
GPDMA_LUTPerBurstDstConn | : Peripheral Destination burst size |
GPDMA_LUTPerWidSrcConn | : Peripheral Source transfer width |
GPDMA_LUTPerWidDstConn | : Peripheral Destination transfer width |
GPDMA_LUTPerAddrSrcConn | : Peripheral Source Address |
GPDMA_LUTPerAddrDstConn | : Peripheral Destination Address |
SrcPeripheral | : Peripheral Source ID |
DstPeripheral | : Peripheral Destination ID |
< Burst size = 32
< Burst size = 32
Definition at line 117 of file gpdma_001.c.