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sct_001.h
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1 /*
2 * @brief State Configurable Timer registers and control functions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31 
32 #ifndef __SCT_001_H_
33 #define __SCT_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
48 #define CONFIG_SCT_nEV (16) /* Number of events */
49 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
50 #define CONFIG_SCT_nOU (16) /* Number of outputs */
51 
55 typedef struct
56 {
57  __IO uint32_t CONFIG; /* Configuration Register */
58  union {
59  __IO uint32_t CTRL_U; /* Control Register */
60  struct {
61  __IO uint16_t CTRL_L; /* low control register */
62  __IO uint16_t CTRL_H; /* high control register */
63  };
64  };
65  __IO uint16_t LIMIT_L; /* limit register for counter L */
66  __IO uint16_t LIMIT_H; /* limit register for counter H */
67  __IO uint16_t HALT_L; /* halt register for counter L */
68  __IO uint16_t HALT_H; /* halt register for counter H */
69  __IO uint16_t STOP_L; /* stop register for counter L */
70  __IO uint16_t STOP_H; /* stop register for counter H */
71  __IO uint16_t START_L; /* start register for counter L */
72  __IO uint16_t START_H; /* start register for counter H */
73  uint32_t RESERVED1[10]; /* 0x03C reserved */
74  union {
75  __IO uint32_t COUNT_U; /* counter register */
76  struct {
77  __IO uint16_t COUNT_L; /* counter register for counter L */
78  __IO uint16_t COUNT_H; /* counter register for counter H */
79  };
80  };
81  __IO uint16_t STATE_L; /* state register for counter L */
82  __IO uint16_t STATE_H; /* state register for counter H */
83  __I uint32_t INPUT; /* input register */
84  __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
85  __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
86  __IO uint32_t OUTPUT; /* output register */
87  __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
88  __IO uint32_t RES; /* conflict resolution register */
89  __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
90  __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
91  uint32_t RESERVED2[35];
92  __IO uint32_t EVEN; /* event enable register */
93  __IO uint32_t EVFLAG; /* event flag register */
94  __IO uint32_t CONEN; /* conflict enable register */
95  __IO uint32_t CONFLAG; /* conflict flag register */
96  union {
97  __IO union { /* ... Match / Capture value */
98  uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
99  struct {
100  uint16_t L; /* SCTMATCH[i].L Access to L value */
101  uint16_t H; /* SCTMATCH[i].H Access to H value */
102  };
103  } MATCH[CONFIG_SCT_nRG];
104  __I union {
105  uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
106  struct {
107  uint16_t L; /* SCTCAP[i].L Access to H value */
108  uint16_t H; /* SCTCAP[i].H Access to H value */
109  };
110  } CAP[CONFIG_SCT_nRG];
111  };
112  uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
113  union {
114  __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
115  __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
116  };
117  uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
118  union {
119  __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
120  __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
121  };
122  uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
123  union {
124  __IO union { /* 0x200-... Match Reload / Capture Control value */
125  uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
126  struct {
127  uint16_t L; /* SCTMATCHREL[i].L Access to L value */
128  uint16_t H; /* SCTMATCHREL[i].H Access to H value */
129  };
130  } MATCHREL[CONFIG_SCT_nRG];
131  __IO union {
132  uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
133  struct {
134  uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
135  uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
136  };
137  } CAPCTRL[CONFIG_SCT_nRG];
138  };
139  uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
140  union {
141  __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
142  __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
143  };
144  uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
145  union {
146  __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
147  __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
148  };
149  uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
150  __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
151  uint32_t STATE; /* Event State Register */
152  uint32_t CTRL; /* Event Control Register */
153  } EVENT[CONFIG_SCT_nEV];
154  uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
155  __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
156  uint32_t SET; /* Output n Set Register */
157  uint32_t CLR; /* Output n Clear Register */
158  } OUT[CONFIG_SCT_nOU];
159  uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
160  __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
162 
167 #ifdef __cplusplus
168 }
169 #endif
170 
171 #endif /* __SCT_001_H_ */