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emc_001.h File Reference
#include "sys_config.h"
#include "cmsis.h"

Go to the source code of this file.

Data Structures

struct  IP_EMC_001_Type
 External Memory Controller (EMC) register block structure. More...
 
struct  IP_EMC_DYN_DEVICE_CONFIG_Type
 EMC Dynamic Device Configuration structure used for IP drivers. More...
 
struct  IP_EMC_DYN_CONFIG_Type
 EMC Dynamic Configure Struct. More...
 
struct  IP_EMC_STATIC_CONFIG_Type
 EMC Static Configure Structure. More...
 

Macros

#define EMC_SUPPORT_ONLY_PL172
 EMC register support bitfields and mask.
 
#define EMC_CONFIG_ENDIAN_LITTLE   (0)
 
#define EMC_CONFIG_ENDIAN_BIG   (1)
 
#define EMC_CONFIG_BUFFER_ENABLE   (1 << 19)
 
#define EMC_CONFIG_WRITE_PROTECT   (1 << 20)
 
#define EMC_DYN_CONFIG_MD_BIT   (3)
 
#define EMC_DYN_CONFIG_MD_SDRAM   (0 << EMC_DYN_CONFIG_MD_BIT)
 
#define EMC_DYN_CONFIG_MD_LPSDRAM   (1 << EMC_DYN_CONFIG_MD_BIT)
 
#define EMC_DYN_CONFIG_LPSDRAM_BIT   (12)
 
#define EMC_DYN_CONFIG_LPSDRAM   (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_BIT   (9)
 
#define EMC_DYN_CONFIG_DEV_SIZE_16Mb   (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_64Mb   (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_BIT   (7)
 
#define EMC_DYN_CONFIG_DEV_BUS_8   (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_16   (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_32   (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)
 
#define EMC_DYN_CONFIG_DATA_BUS_16   (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
 
#define EMC_DYN_CONFIG_DATA_BUS_32   (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
 
#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS   ((0x0 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS   ((0x0 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS   ((0x1 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS   ((0x1 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS   ((0x1 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS   ((0x2 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS   ((0x3 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS   ((0x4 << 9) | (0x1 << 7))
 
#define EMC_DYN_MODE_BURST_LEN_BIT   (0)
 
#define EMC_DYN_MODE_BURST_LEN_1   (0)
 
#define EMC_DYN_MODE_BURST_LEN_2   (1)
 
#define EMC_DYN_MODE_BURST_LEN_4   (2)
 
#define EMC_DYN_MODE_BURST_LEN_8   (3)
 
#define EMC_DYN_MODE_BURST_LEN_FULL   (7)
 
#define EMC_DYN_MODE_BURST_TYPE_BIT   (3)
 
#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL   (0 << EMC_DYN_MODE_BURST_TYPE_BIT)
 
#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE   (1 << EMC_DYN_MODE_BURST_TYPE_BIT)
 
#define EMC_DYN_MODE_CAS_BIT   (4)
 
#define EMC_DYN_MODE_CAS_1   (1 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_CAS_2   (2 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_CAS_3   (3 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_OPMODE_BIT   (7)
 
#define EMC_DYN_MODE_OPMODE_STANDARD   (0 << EMC_DYN_MODE_OPMODE_BIT)
 
#define EMC_DYN_MODE_WBMODE_BIT   (9)
 
#define EMC_DYN_MODE_WBMODE_PROGRAMMED   (0 << EMC_DYN_MODE_WBMODE_BIT)
 
#define EMC_DYN_MODE_WBMODE_SINGLE_LOC   (1 << EMC_DYN_MODE_WBMODE_BIT)
 
#define EMC_DYN_CONTROL_DEEPSLEEP_BIT   (13)
 
#define EMC_DYN_CONTROL_ENABLE   (0x03)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_8   (0)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_16   (1)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_32   (2)
 
#define EMC_STATIC_CONFIG_PAGE_MODE_BIT   (3)
 
#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE   (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)
 
#define EMC_STATIC_CONFIG_CS_POL_BIT   (6)
 
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH   (1 << EMC_STATIC_CONFIG_CS_POL_BIT)
 
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW   (0 << EMC_STATIC_CONFIG_CS_POL_BIT)
 
#define EMC_STATIC_CONFIG_BLS_BIT   (7)
 
#define EMC_STATIC_CONFIG_BLS_HIGH   (1 << EMC_STATIC_CONFIG_BLS_BIT)
 
#define EMC_STATIC_CONFIG_BLS_LOW   (0 << EMC_STATIC_CONFIG_BLS_BIT)
 
#define EMC_STATIC_CONFIG_EW_BIT   (8)
 
#define EMC_STATIC_CONFIG_EW_ENABLE   (1 << EMC_STATIC_CONFIG_EW_BIT)
 
#define EMC_STATIC_CONFIG_EW_DISABLE   (0 << EMC_STATIC_CONFIG_EW_BIT)
 
#define Q24_8_FP(x)   ((x) * 256)
 
#define EMC_NANOSECOND(x)   Q24_8_FP(x)
 
#define EMC_CLOCK(x)   Q24_8_FP(-(x))
 

Functions

void IP_EMC_Dynamic_Init (IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock)
 Initializes the Dynamic Controller.
 
void IP_EMC_Dynamic_DeepSleepMode (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Set Deep Sleep Mode for Dynamic Memory Controller.
 
void IP_EMC_Dynamic_Enable (IP_EMC_001_Type *pEMC, uint8_t Enable)
 Enable Dynamic Memory Controller.
 
void IP_EMC_Static_Init (IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock)
 Initializes the Static Controller according to the specified parameters in the IP_EMC_STATIC_CONFIG_Type.
 
void IP_EMC_Mirror (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Mirror CS1 to CS0 and DYCS0.
 
void IP_EMC_Enable (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Enable EMC.
 
void IP_EMC_LowPowerMode (IP_EMC_001_Type *pEMC, uint32_t Enable)
 Set EMC LowPower Mode.
 
void IP_EMC_Init (IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
 Initialize EMC.
 
void IP_EMC_SetStaticExtendedWait (IP_EMC_001_Type *pEMC, uint32_t Wait16Clks)
 Set Static Memory Extended Wait in Clock.