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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Modules | |
CHIP: LPC18xx/43xx Clock Driver driver options | |
Data Structures | |
struct | LPC_CGU_T |
LPC18XX/43XX CGU register block structure. More... | |
Macros | |
#define | CGU_IRC_FREQ (12000000) |
#define | MAX_CLOCK_FREQ (180000000) |
Functions | |
void | Chip_Clock_EnableCrystal (void) |
Enables the crystal oscillator. | |
void | Chip_Clock_DisableCrystal (void) |
Disables the crystal oscillator. | |
uint32_t | Chip_Clock_SetupMainPLLHz (CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz) |
Configures the main PLL. | |
uint32_t | Chip_Clock_SetupMainPLLMult (CGU_CLKIN_T Input, uint32_t mult) |
Directly set the PLL multipler. | |
uint32_t | Chip_Clock_GetMainPLLHz (void) |
Returns the frequency of the main PLL. | |
void | Chip_Clock_DisableMainPLL (void) |
Disables the main PLL. | |
bool | Chip_Clock_MainPLLLocked (void) |
Returns the lock status of the main PLL. | |
void | Chip_Clock_SetDivider (CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor) |
Sets up a CGU clock divider and it's input clock. | |
CGU_CLKIN_T | Chip_Clock_GetDividerSource (CGU_IDIV_T Divider) |
Gets a CGU clock divider source. | |
uint32_t | Chip_Clock_GetDividerDivisor (CGU_IDIV_T Divider) |
Gets a CGU clock divider divisor. | |
uint32_t | Chip_Clock_GetClockInputHz (CGU_CLKIN_T input) |
Returns the frequency of the specified input clock source. | |
uint32_t | Chip_Clock_GetBaseClocktHz (CGU_BASE_CLK_T clock) |
Returns the frequency of the specified base clock source. | |
void | Chip_Clock_SetBaseClock (CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn) |
Sets a CGU Base Clock clock source. | |
CGU_CLKIN_T | Chip_Clock_GetBaseClock (CGU_BASE_CLK_T BaseClock) |
Gets a CGU Base Clock clock source. | |
void | Chip_Clock_EnableBaseClock (CGU_BASE_CLK_T BaseClock) |
Enables a base clock source. | |
void | Chip_Clock_DisableBaseClock (CGU_BASE_CLK_T BaseClock) |
Disables a base clock source. | |
void | Chip_Clock_EnableOpts (CCU_CLK_T clk, bool autoen, bool wakeupen, int div) |
Enables a peripheral clock and sets clock states. | |
void | Chip_Clock_Enable (CCU_CLK_T clk) |
Enables a peripheral clock. | |
void | Chip_Clock_Disable (CCU_CLK_T clk) |
Disables a peripheral clock. | |
uint32_t | Chip_Clock_GetRate (CCU_CLK_T clk) |
Returns a peripheral clock rate. | |
enum | CGU_CLKIN_T { CLKIN_32K, CLKIN_IRC, CLKIN_ENET_RX, CLKIN_ENET_TX, CLKIN_CLKIN, CLKIN_RESERVED1, CLKIN_CRYSTAL, CLKIN_USBPLL, CLKIN_AUDIOPLL, CLKIN_MAINPLL, CLKIN_RESERVED2, CLKIN_RESERVED3, CLKIN_IDIVA, CLKIN_IDIVB, CLKIN_IDIVC, CLKIN_IDIVD, CLKIN_IDIVE, CLKINPUT_PD } |
CGU clock input list These are possible input clocks for the CGU and can come from both external (crystal) and internal (PLL) sources. These clock inputs can be routed to the base clocks (CGU_BASE_CLK_T). More... | |
enum | CGU_BASE_CLK_T { CLK_BASE_SAFE, CLK_BASE_USB0, CLK_BASE_RESERVED1, CLK_BASE_USB1, CLK_BASE_MX, CLK_BASE_SPIFI, CLK_BASE_RESERVED2, CLK_BASE_PHY_RX, CLK_BASE_PHY_TX, CLK_BASE_APB1, CLK_BASE_APB3, CLK_BASE_LCD, CLK_BASE_RESERVED3, CLK_BASE_SDIO, CLK_BASE_SSP0, CLK_BASE_SSP1, CLK_BASE_UART0, CLK_BASE_UART1, CLK_BASE_UART2, CLK_BASE_UART3, CLK_BASE_OUT, CLK_BASE_RESERVED4, CLK_BASE_RESERVED5, CLK_BASE_RESERVED6, CLK_BASE_RESERVED7, CLK_BASE_APLL, CLK_BASE_CGU_OUT0, CLK_BASE_CGU_OUT1, CLK_BASE_LAST, CLK_BASE_NONE = CLK_BASE_LAST } |
CGU base clocks CGU base clocks are clocks that are associated with a single input clock and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH clock can be configured to use the CLKIN_MAINPLL input clock, which will in turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and CLK_PERIPH_SGPIO periphral clocks. More... | |
enum | CGU_IDIV_T { CLK_IDIV_A, CLK_IDIV_B, CLK_IDIV_C, CLK_IDIV_D, CLK_IDIV_E, CLK_IDIV_LAST } |
CGU dividers CGU dividers provide an extra clock state where a specific clock can be divided before being routed to a peripheral group. A divider accepts an input clock and then divides it. To use the divided clock for a base clock group, use the divider as the input clock for the base clock (for example, use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider). More... | |
enum | CCU_CLK_T { CLK_APB3_BUS, CLK_APB3_I2C1, CLK_APB3_DAC, CLK_APB3_ADC0, CLK_APB3_ADC1, CLK_APB3_CAN0, CLK_APB1_BUS = 32, CLK_APB1_MOTOCON, CLK_APB1_I2C0, CLK_APB1_I2S, CLK_APB1_CAN1, CLK_SPIFI = 64, CLK_MX_BUS = 96, CLK_MX_SPIFI, CLK_MX_GPIO, CLK_MX_LCD, CLK_MX_ETHERNET, CLK_MX_USB0, CLK_MX_EMC, CLK_MX_SDIO, CLK_MX_DMA, CLK_MX_MXCORE, RESERVED_ALIGN = CLK_MX_MXCORE + 3, CLK_MX_SCT, CLK_MX_USB1, CLK_MX_EMC_DIV, CLK_MX_FLASHA, CLK_MX_FLASHB, CLK_RESERVED1, CLK_RESERVED2, CLK_MX_EEPROM, CLK_MX_WWDT = 128, CLK_MX_UART0, CLK_MX_UART1, CLK_MX_SSP0, CLK_MX_TIMER0, CLK_MX_TIMER1, CLK_MX_SCU, CLK_MX_CREG, CLK_MX_RITIMER = 160, CLK_MX_UART2, CLK_MX_UART3, CLK_MX_TIMER2, CLK_MX_TIMER3, CLK_MX_SSP1, CLK_MX_QEI, CLK_RESERVED3 = 192, CLK_RESERVED3A, CLK_RESERVED4, CLK_RESERVED5, CLK_USB0 = 224, CLK_USB1 = 256, CLK_RESERVED7 = 320, CLK_RESERVED8, CLK_CCU1_LAST, CLK_CCU2_START, CLK_APLL = CLK_CCU2_START, RESERVED_ALIGNB = CLK_CCU2_START + 31, CLK_APB2_UART3, RESERVED_ALIGNC = CLK_CCU2_START + 63, CLK_APB2_UART2, RESERVED_ALIGND = CLK_CCU2_START + 95, CLK_APB0_UART1, RESERVED_ALIGNE = CLK_CCU2_START + 127, CLK_APB0_UART0, RESERVED_ALIGNF = CLK_CCU2_START + 159, CLK_APB2_SSP1, RESERVED_ALIGNG = CLK_CCU2_START + 191, CLK_APB0_SSP0, RESERVED_ALIGNH = CLK_CCU2_START + 223, CLK_APB2_SDIO, CLK_CCU2_LAST } |
Peripheral clocks Peripheral clocks are individual clocks routed to peripherals. Although multiple peripherals may share a same base clock, each peripheral's clock can be enabled or disabled individually. Some peripheral clocks also have additional dividers associated with them. More... | |
#define CGU_IRC_FREQ (12000000) |
Definition at line 62 of file clock_18xx_43xx.h.
#define MAX_CLOCK_FREQ (180000000) |
Definition at line 68 of file clock_18xx_43xx.h.
enum CCU_CLK_T |
Peripheral clocks Peripheral clocks are individual clocks routed to peripherals. Although multiple peripherals may share a same base clock, each peripheral's clock can be enabled or disabled individually. Some peripheral clocks also have additional dividers associated with them.
Definition at line 149 of file chip_clocks.h.
enum CGU_BASE_CLK_T |
CGU base clocks CGU base clocks are clocks that are associated with a single input clock and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH clock can be configured to use the CLKIN_MAINPLL input clock, which will in turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and CLK_PERIPH_SGPIO periphral clocks.
Definition at line 80 of file chip_clocks.h.
enum CGU_CLKIN_T |
CGU clock input list These are possible input clocks for the CGU and can come from both external (crystal) and internal (PLL) sources. These clock inputs can be routed to the base clocks (CGU_BASE_CLK_T).
Definition at line 51 of file chip_clocks.h.
enum CGU_IDIV_T |
CGU dividers CGU dividers provide an extra clock state where a specific clock can be divided before being routed to a peripheral group. A divider accepts an input clock and then divides it. To use the divided clock for a base clock group, use the divider as the input clock for the base clock (for example, use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
CLK_IDIV_A |
CGU clock divider A |
CLK_IDIV_B |
CGU clock divider B |
CLK_IDIV_C |
CGU clock divider A |
CLK_IDIV_D |
CGU clock divider D |
CLK_IDIV_E |
CGU clock divider E |
CLK_IDIV_LAST |
Definition at line 133 of file chip_clocks.h.
void Chip_Clock_Disable | ( | CCU_CLK_T | clk | ) |
Disables a peripheral clock.
clk | : CCU_CLK_T value indicating which clock to disable |
Definition at line 528 of file clock_18xx_43xx.c.
void Chip_Clock_DisableBaseClock | ( | CGU_BASE_CLK_T | BaseClock | ) |
Disables a base clock source.
BaseClock | : CGU_BASE_CLK_T value indicating which base clock to disable |
Definition at line 464 of file clock_18xx_43xx.c.
void Chip_Clock_DisableCrystal | ( | void | ) |
Disables the crystal oscillator.
void Chip_Clock_DisableMainPLL | ( | void | ) |
Disables the main PLL.
Definition at line 283 of file clock_18xx_43xx.c.
void Chip_Clock_Enable | ( | CCU_CLK_T | clk | ) |
Enables a peripheral clock.
clk | : CCU_CLK_T value indicating which clock to enable |
Definition at line 516 of file clock_18xx_43xx.c.
void Chip_Clock_EnableBaseClock | ( | CGU_BASE_CLK_T | BaseClock | ) |
Enables a base clock source.
BaseClock | : CGU_BASE_CLK_T value indicating which base clock to enable |
Definition at line 456 of file clock_18xx_43xx.c.
void Chip_Clock_EnableCrystal | ( | void | ) |
void Chip_Clock_EnableOpts | ( | CCU_CLK_T | clk, |
bool | autoen, | ||
bool | wakeupen, | ||
int | div | ||
) |
Enables a peripheral clock and sets clock states.
clk | : CCU_CLK_T value indicating which clock to enable |
autoen | : true to enable autoblocking on a clock rate change, false to disable |
wakeupen | : true to enable wakeup mechanism, false to disable |
div | : Divider for the clock, must be 1 for most clocks, 2 supported on others |
Definition at line 489 of file clock_18xx_43xx.c.
CGU_CLKIN_T Chip_Clock_GetBaseClock | ( | CGU_BASE_CLK_T | BaseClock | ) |
Gets a CGU Base Clock clock source.
BaseClock | : CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for |
Definition at line 472 of file clock_18xx_43xx.c.
uint32_t Chip_Clock_GetBaseClocktHz | ( | CGU_BASE_CLK_T | clock | ) |
Returns the frequency of the specified base clock source.
clock | : which base clock to return the frequency of. |
Definition at line 422 of file clock_18xx_43xx.c.
uint32_t Chip_Clock_GetClockInputHz | ( | CGU_CLKIN_T | input | ) |
Returns the frequency of the specified input clock source.
input | : Which clock input to return the frequency of |
Definition at line 334 of file clock_18xx_43xx.c.
uint32_t Chip_Clock_GetDividerDivisor | ( | CGU_IDIV_T | Divider | ) |
Gets a CGU clock divider divisor.
Divider | : CGU_IDIV_T value indicating which divider to get the source of |
Definition at line 328 of file clock_18xx_43xx.c.
CGU_CLKIN_T Chip_Clock_GetDividerSource | ( | CGU_IDIV_T | Divider | ) |
Gets a CGU clock divider source.
Divider | : CGU_IDIV_T value indicating which divider to get the source of |
Definition at line 316 of file clock_18xx_43xx.c.
uint32_t Chip_Clock_GetMainPLLHz | ( | void | ) |
Returns the frequency of the main PLL.
Definition at line 252 of file clock_18xx_43xx.c.
Returns a peripheral clock rate.
clk | : CCU_CLK_T value indicating which clock to get rate for |
Definition at line 540 of file clock_18xx_43xx.c.
bool Chip_Clock_MainPLLLocked | ( | void | ) |
Returns the lock status of the main PLL.
Definition at line 290 of file clock_18xx_43xx.c.
void Chip_Clock_SetBaseClock | ( | CGU_BASE_CLK_T | BaseClock, |
CGU_CLKIN_T | Input, | ||
bool | autoblocken, | ||
bool | powerdn | ||
) |
Sets a CGU Base Clock clock source.
BaseClock | : CGU_BASE_CLK_T value indicating which base clock to set |
Input | : CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock |
autoblocken | : Enables autoblocking during frequency change if true |
powerdn | : The clock base is setup, but powered down if true |
Definition at line 428 of file clock_18xx_43xx.c.
void Chip_Clock_SetDivider | ( | CGU_IDIV_T | Divider, |
CGU_CLKIN_T | Input, | ||
uint32_t | Divisor | ||
) |
Sets up a CGU clock divider and it's input clock.
Divider | : CGU_IDIV_T value indicating which divider to configure |
Input | : CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider |
Divisor | : value to divide Input clock by |
Definition at line 297 of file clock_18xx_43xx.c.
uint32_t Chip_Clock_SetupMainPLLHz | ( | CGU_CLKIN_T | Input, |
uint32_t | MinHz, | ||
uint32_t | DesiredHz, | ||
uint32_t | MaxHz | ||
) |
Configures the main PLL.
Input | : Which clock input to use as the PLL input |
MinHz | : Minimum allowable PLL output frequency |
DesiredHz | : Desired PLL output frequency |
MaxHz | : Maximum allowable PLL output frequency |
Definition at line 152 of file clock_18xx_43xx.c.
uint32_t Chip_Clock_SetupMainPLLMult | ( | CGU_CLKIN_T | Input, |
uint32_t | mult | ||
) |
Directly set the PLL multipler.
Input | : Which clock input to use as the PLL input |
mult | : How many times to multiply the input clock |
Definition at line 212 of file clock_18xx_43xx.c.