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ssp_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx SSP driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SSP_18XX_43XX_H_
33 #define __SSP_18XX_43XX_H_
34 
35 #include "chip.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
46 /*
47  * @brief SSP clock format
48  */
49 typedef enum SSP_ClockFormat {
50  SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),
51  SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
52  SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
53  SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
59 
60 /*
61  * @brief SSP frame format
62  */
63 typedef enum SSP_FrameFormat {
64  SSP_FRAMEFORMAT_SPI = (0 << 4),
65  SSP_FRAMEFORMAT_TI = (1u << 4),
68 
69 /*
70  * @brief Number of bits per frame
71  */
72 typedef enum SSP_Bits {
73  SSP_BITS_4 = (3u << 0),
74  SSP_BITS_5 = (4u << 0),
75  SSP_BITS_6 = (5u << 0),
76  SSP_BITS_7 = (6u << 0),
77  SSP_BITS_8 = (7u << 0),
78  SSP_BITS_9 = (8u << 0),
79  SSP_BITS_10 = (9u << 0),
80  SSP_BITS_11 = (10u << 0),
81  SSP_BITS_12 = (11u << 0),
82  SSP_BITS_13 = (12u << 0),
83  SSP_BITS_14 = (13u << 0),
84  SSP_BITS_15 = (14u << 0),
85  SSP_BITS_16 = (15u << 0),
86 } SSP_Bits;
87 
88 /*
89  * @brief SSP config format
90  */
91 typedef struct SSP_ConfigFormat {
96 
97 /*
98  * @brief SSP mode
99  */
100 typedef enum SSP_Mode {
101  SSP_MODE_MASTER = (0 << 2),
102  SSP_MODE_SLAVE = (1u << 2),
103 } SSP_Mode;
104 
105 /*
106  * @brief SPI address
107  */
108 typedef struct {
109  uint8_t port;
110  uint8_t pin;
111 } SPI_Address_t;
112 
113 /*
114  * @brief SSP data setup structure
115  */
116 typedef struct {
117  void *tx_data;
119  void *rx_data;
123 
126 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
127 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
128 
130 /* There's no bug here!!!
131  * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
132  * That means the active clock is in HI state.
133  * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
134  * high between frames. That means the active clock is in LO state.
135  */
136 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
137 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
138 
140 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
141 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN
142 
155 {
156  return IP_SSP_GetStatus(pSSP, Stat);
157 }
158 
166 {
167  IP_SSP_Cmd(pSSP, NewState);
168 }
169 
177 {
178  IP_SSP_DeInit(pSSP);
179 }
180 
190 {
191  IP_SSP_LoopBackCmd(pSSP, NewState);
192 }
193 
200 
209 
218 
231 
242 uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len);
243 
254 uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len);
255 
261 void Chip_SSP_Init(LPC_SSP_Type *pSSP);
262 
269 void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master);
270 
277 void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate);
278 
286 
293 void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState);
294 
301 void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState);
302 
307 #ifdef __cplusplus
308 }
309 #endif
310 
311 #endif /* __SSP_18XX_43XX_H_ */