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sysinit_ngx_xplorer_18304330.c
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1 /*
2  * Copyright(C) NXP Semiconductors, 2012
3  * All rights reserved.
4  *
5  * Software that is described herein is for illustrative purposes only
6  * which provides customers with programming information regarding the
7  * LPC products. This software is supplied "AS IS" without any warranties of
8  * any kind, and NXP Semiconductors and its licensor disclaim any and
9  * all warranties, express or implied, including all implied warranties of
10  * merchantability, fitness for a particular purpose and non-infringement of
11  * intellectual property rights. NXP Semiconductors assumes no responsibility
12  * or liability for the use of the software, conveys no license or rights under any
13  * patent, copyright, mask work right, or any other intellectual property rights in
14  * or to any products. NXP Semiconductors reserves the right to make changes
15  * in the software without notification. NXP Semiconductors also makes no
16  * representation or warranty that such application will be suitable for the
17  * specified use without further testing or modification.
18  *
19  * Permission to use, copy, modify, and distribute this software and its
20  * documentation is hereby granted, under NXP Semiconductors' and its
21  * licensor's relevant copyrights in the software, without fee, provided that it
22  * is used in conjunction with NXP Semiconductors microcontrollers. This
23  * copyright, permission, and disclaimer notice must appear in all copies of
24  * this code.
25  */
26 
27 #include "board.h"
28 
50 #ifndef CORE_M0
51 /* SCR pin definitions for pin muxing */
52 typedef struct {
53  uint8_t pingrp; /* Pin group */
54  uint8_t pinnum; /* Pin number */
55  uint8_t pincfg; /* Pin configuration for SCU */
56  uint8_t funcnum;/* Function number */
57 } PINMUX_GRP_T;
58 
59 /* Structure for initial base clock states */
60 struct CLK_BASE_STATES {
61  CGU_BASE_CLK_T clk; /* Base clock */
62  CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
63  bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
64  bool powerdn; /* Set to true if the base clock is initially powered down */
65 };
66 
67 /* Initial base clock states are mostly on */
69  {CLK_BASE_SAFE, CLKIN_IRC, true, false},
70  {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
71  {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
72  {CLK_BASE_USB0, CLKIN_USBPLL, true, false},
73 #if defined(CHIP_LPC43XX)
74  {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
75 #endif
76  {CLK_BASE_USB1, CLKIN_USBPLL, true, false},
77 #if defined(CHIP_LPC43XX)
78  {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
79 #endif
80  {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
81 #if defined(USE_RMII)
82  {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
83 #else
84  {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
85 #endif
86  {CLK_BASE_LCD, CLKIN_MAINPLL, false, true},
87 #if defined(CHIP_LPC43XX)
88  {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
89 #endif
90  {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
91  {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
92  {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
93  {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
94  {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
95  {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
96  {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
97  {CLK_BASE_OUT, CLKINPUT_PD, true, false},
98  {CLK_BASE_APLL, CLKINPUT_PD, true, false},
99  {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
100  {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
101 };
102 
103 /* SPIFI high speed pin mode setup */
105  {0x3, 3, (MD_PLN_FAST), FUNC3}, /* SPIFI CLK */
106  {0x3, 4, (MD_PLN_FAST), FUNC3}, /* SPIFI D3 */
107  {0x3, 5, (MD_PLN_FAST), FUNC3}, /* SPIFI D2 */
108  {0x3, 6, (MD_PLN_FAST), FUNC3}, /* SPIFI D1 */
109  {0x3, 7, (MD_PLN_FAST), FUNC3}, /* SPIFI D0 */
110  {0x3, 8, (MD_PLN_FAST), FUNC3} /* SPIFI CS/SSEL */
111 };
112 
113 /* Setup system clocking */
115 {
116  int i;
117 
118  /* Switch main system clocking to crystal */
121 
122  /* Setup PLL for 100MHz and switch main system clocking */
123  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
125 
126  /* Setup PLL for maximum clock */
128 
129  /* Setup system base clocks and initial states. This won't enable and
130  disable individual clocks, but sets up the base clock sources for
131  each individual peripheral clock. */
132  for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
133  Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
134  InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
135  }
136 
137  /* Reset and enable 32Khz oscillator */
138  LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
139  LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
140 
141  /* SPIFI pin setup is done prior to setting up system clocking */
142  for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
143  Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
144  spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
145  }
146 
147  /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
148  Divide rate is based on CPU speed and speed of SPI FLASH part. */
149 #if (MAX_CLOCK_FREQ > 180000000)
151 #else
153 #endif
155 }
156 
158  /* RMII pin group */
159  {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
160  {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2},
161  {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7},
162  {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6},
163  {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0},
164  {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
165  {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
166  {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
167  {0x2, 0, (MD_EHS | MD_PLN | MD_ZI), FUNC7},
168  /* Board LEDs */
169  {0x2, 11, MD_PDN, FUNC0},
170  {0x2, 12, MD_PDN, FUNC0},
171  /* I2S */
172  {0x3, 0, MD_PLN_FAST, FUNC2},
173  {0x6, 0, MD_PLN_FAST, FUNC4},
174  {0x7, 2, MD_PLN_FAST, FUNC2},
175  {0x6, 2, MD_PLN_FAST, FUNC3},
176  {0x7, 1, MD_PLN_FAST, FUNC2},
177  {0x6, 1, MD_PLN_FAST, FUNC3},
178 };
179 
180 /* Sets up system pin muxing */
182 {
183  int i;
184 
185  /* Setup system level pin muxing */
186  for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
187  Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
188  pinmuxing[i].pincfg, pinmuxing[i].funcnum);
189  }
190 }
191 
192 /* Nothing to do for the Xplorer board */
194 {}
195 
196 #endif
197 
205 void SystemInit(void)
206 {
207 #if defined(CORE_M3) || defined(CORE_M4)
208  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
209 
210 #if defined(__IAR_SYSTEMS_ICC__)
211  extern void *__vector_table;
212 
213  *pSCB_VTOR = (unsigned int) &__vector_table;
214 #elif defined(__CODE_RED)
215  extern void *g_pfnVectors;
216 
217  *pSCB_VTOR = (unsigned int) &g_pfnVectors;
218 #elif defined(__ARMCC_VERSION)
219  extern void *__Vectors;
220 
221  *pSCB_VTOR = (unsigned int) &__Vectors;
222 #endif
223 
224 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
225  fpuInit();
226 #endif
227 
228  /* Setup system clocking and memory. This is done early to allow the
229  application and tools to clear memory and use scatter loading to
230  external memory. */
234 #endif
235 }
236