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gpdma_001.c
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1 /*
2  * @brief GPDMA Registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #include "gpdma_001.h"
33 
34 /*****************************************************************************
35  * Private types/enumerations/variables
36  ****************************************************************************/
37 
38 /*****************************************************************************
39  * Public types/enumerations/variables
40  ****************************************************************************/
41 
42 /*****************************************************************************
43  * Private functions
44  ****************************************************************************/
45 
46 /*****************************************************************************
47  * Public functions
48  ****************************************************************************/
49 
50 /* Initialize the GPDMA */
52  uint8_t i;
53  /* Reset all channel configuration register */
54  for (i = 8; i > 0; i--) {
55  pGPDMA->CH[i - 1].CONFIG = 0;
56  }
57 
58  /* Clear all DMA interrupt and error flag */
59  pGPDMA->INTTCCLEAR = 0xFF;
60  pGPDMA->INTERRCLR = 0xFF;
61 }
62 
63 /* Read the status from different registers according to the type */
68  switch (type) {
69  case GPDMA_STAT_INT:/* check status of DMA channel interrupts */
70  return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF)));
71 
72  case GPDMA_STAT_INTTC: /* check terminal count interrupt request status for DMA */
73  return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF)));
74 
75  case GPDMA_STAT_INTERR: /* check interrupt status for DMA channels */
76  return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF)));
77 
78  case GPDMA_STAT_RAWINTTC: /* check status of the terminal count interrupt for DMA channels */
79  return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF)));
80 
81  case GPDMA_STAT_RAWINTERR: /* check status of the error interrupt for DMA channels */
82  return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF)));
83 
84  default:/* check enable status for DMA channels */
85  return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF)));
86  }
87 }
88 
89 /* Clear the Interrupt Flag from different registers according to the type */
91  if (type == GPDMA_STATCLR_INTTC) {
92  /* clears the terminal count interrupt request on DMA channel */
93  pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF));
94  }
95  else {
96  /* clear the error interrupt request */
97  pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF));
98  }
99 }
100 
101 /* Enable or Disable the GPDMA Channel */
102 void IP_GPDMA_ChannelCmd(IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState) {
103  IP_GPDMA_001_CH_Type *pDMAch;
104 
105  /* Get Channel pointer */
106  pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[channelNum]);
107 
108  if (NewState == ENABLE) {
109  pDMAch->CONFIG |= GPDMA_DMACCxConfig_E;
110  }
111  else {
112  pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E;
113  }
114 }
115 
116 /* Set up the DPDMA according to the specification configuration details */
118  GPDMA_Channel_CFG_Type *GPDMAChannelConfig,
119  uint32_t GPDMA_LUTPerBurstSrcConn,
120  uint32_t GPDMA_LUTPerBurstDstConn,
121  uint32_t GPDMA_LUTPerWidSrcConn,
122  uint32_t GPDMA_LUTPerWidDstConn,
123  uint32_t GPDMA_LUTPerAddrSrcConn,
124  uint32_t GPDMA_LUTPerAddrDstConn,
125  uint8_t SrcPeripheral,
126  uint8_t DstPeripheral)
127 {
128  IP_GPDMA_001_CH_Type *pDMAch;
129 
130  if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) {
131  /* This channel is enabled, return ERROR, need to release this channel first */
132  return ERROR;
133  }
134 
135  /* Get Channel pointer */
136  pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]);
137 
138  /* Reset the Interrupt status */
139  pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
140  pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
141 
142  /* Assign Linker List Item value */
143  pDMAch->LLI = 0;/* Fixed to 0 (no link list) */
144 
145  /* Enable DMA channels, little endian */
146  pGPDMA->CONFIG = GPDMA_DMACConfig_E;
147  while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {}
148 
149  pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr;
150  pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr;
151 
152  /* Configure DMA Channel, enable Error Counter and Terminate counter */
153  pDMAch->CONFIG = GPDMA_DMACCxConfig_IE
154  | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/
155  | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType)
156  | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
157  | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);
158 
159  switch (GPDMAChannelConfig->TransferType) {
160  /* Memory to memory */
162  pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize)
165  | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth)
166  | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth)
170  break;
171 
174  pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
175  | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn)
176  | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
177  | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn)
178  | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
182  break;
183 
186  pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
187  | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
188  | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn)
189  | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
190  | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn)
194  break;
195 
199  pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
200  | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
201  | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
202  | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
203  | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
207 
208  break;
209 
210  /* Do not support any more transfer type, return ERROR */
211  default:
212  return ERROR;
213  }
214 
215  return SUCCESS;
216 }