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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Data Structures | |
struct | IP_I2C_001_Type |
I2C register block structure. More... | |
struct | I2C_M_SETUP_Type |
Master transfer setup data structure definitions. More... | |
struct | I2C_S_SETUP_Type |
Slave transfer setup data structure definitions. More... | |
struct | I2C_OWNSLAVEADDR_CFG_Type |
I2C Own slave address setting structure. More... | |
Macros | |
#define | I2C_STA_STO_RECV 0x20 |
I2C state handle return values. | |
#define | I2C_STA_STO_RECV 0x20 |
I2C state handle return values. | |
#define | I2C_I2CONSET_AA ((0x04)) |
I2C Control Set register description. | |
#define | I2C_I2CONSET_SI ((0x08)) |
#define | I2C_I2CONSET_STO ((0x10)) |
#define | I2C_I2CONSET_STA ((0x20)) |
#define | I2C_I2CONSET_I2EN ((0x40)) |
#define | I2C_I2CONCLR_AAC ((1 << 2)) |
I2C Control Clear register description. | |
#define | I2C_I2CONCLR_SIC ((1 << 3)) |
#define | I2C_I2CONCLR_STOC ((1 << 4)) |
#define | I2C_I2CONCLR_STAC ((1 << 5)) |
#define | I2C_I2CONCLR_I2ENC ((1 << 6)) |
#define | I2C_STAT_CODE_BITMASK ((0xF8)) |
I2C Status Code definition (I2C Status register) | |
#define | I2C_STAT_CODE_ERROR ((0xFF)) |
#define | I2C_I2STAT_NO_INF ((0xF8)) |
I2C return status code definitions. | |
#define | I2C_I2STAT_BUS_ERROR ((0x00)) |
#define | I2C_I2STAT_M_TX_START ((0x08)) |
I2C Master transmit mode. | |
#define | I2C_I2STAT_M_TX_RESTART ((0x10)) |
#define | I2C_I2STAT_M_TX_SLAW_ACK ((0x18)) |
#define | I2C_I2STAT_M_TX_SLAW_NACK ((0x20)) |
#define | I2C_I2STAT_M_TX_DAT_ACK ((0x28)) |
#define | I2C_I2STAT_M_TX_DAT_NACK ((0x30)) |
#define | I2C_I2STAT_M_TX_ARB_LOST ((0x38)) |
#define | I2C_I2STAT_M_RX_START ((0x08)) |
I2C Master receive mode. | |
#define | I2C_I2STAT_M_RX_RESTART ((0x10)) |
#define | I2C_I2STAT_M_RX_ARB_LOST ((0x38)) |
#define | I2C_I2STAT_M_RX_SLAR_ACK ((0x40)) |
#define | I2C_I2STAT_M_RX_SLAR_NACK ((0x48)) |
#define | I2C_I2STAT_M_RX_DAT_ACK ((0x50)) |
#define | I2C_I2STAT_M_RX_DAT_NACK ((0x58)) |
#define | I2C_I2STAT_S_RX_SLAW_ACK ((0x60)) |
I2C Slave receive mode. | |
#define | I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68)) |
#define | I2C_I2STAT_S_RX_GENCALL_ACK ((0x70)) |
#define | I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78)) |
#define | I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80)) |
#define | I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88)) |
#define | I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90)) |
#define | I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98)) |
#define | I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0)) |
#define | I2C_I2STAT_S_TX_SLAR_ACK ((0xA8)) |
I2C Slave transmit mode. | |
#define | I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0)) |
#define | I2C_I2STAT_S_TX_DAT_ACK ((0xB8)) |
#define | I2C_I2STAT_S_TX_DAT_NACK ((0xC0)) |
#define | I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8)) |
#define | I2C_SLAVE_TIME_OUT 0x10000000UL |
#define | I2C_I2DAT_BITMASK ((0xFF)) |
I2C Data register definition. | |
#define | I2C_I2DAT_IDLE_CHAR (0xFF) |
#define | I2C_I2MMCTRL_MM_ENA ((1 << 0)) |
I2C Monitor mode control register description. | |
#define | I2C_I2MMCTRL_ENA_SCL ((1 << 1)) |
#define | I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) |
#define | I2C_I2MMCTRL_BITMASK ((0x07)) |
#define | I2DATA_BUFFER_BITMASK ((0xFF)) |
I2C Data buffer register description. | |
#define | I2C_I2ADR_GC ((1 << 0)) |
I2C Slave Address registers definition. | |
#define | I2C_I2ADR_BITMASK ((0xFF)) |
#define | I2C_I2MASK_MASK(n) ((n & 0xFE)) |
I2C Mask Register definition. | |
#define | I2C_I2SCLH_BITMASK ((0xFFFF)) |
I2C SCL HIGH duty cycle Register definition. | |
#define | I2C_I2SCLL_BITMASK ((0xFFFF)) |
I2C SCL LOW duty cycle Register definition. | |
#define | I2C_SETUP_STATUS_ARBF (1 << 8) |
I2C status values. | |
#define | I2C_SETUP_STATUS_NOACKF (1 << 9) |
#define | I2C_SETUP_STATUS_DONE (1 << 10) |
#define | I2C_OK 0x00 |
I2C state handle return values. | |
#define | I2C_BYTE_SENT 0x01 |
#define | I2C_BYTE_RECV 0x02 |
#define | I2C_LAST_BYTE_RECV 0x04 |
#define | I2C_SEND_END 0x08 |
#define | I2C_RECV_END 0x10 |
#define | I2C_ERR (0x10000000) |
#define | I2C_NAK_RECV (0x10000000 | 0x01) |
#define | I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000) |
#define | I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL |
I2C monitor control configuration defines. | |
#define | I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL |
Enumerations | |
enum | I2C_TRANSFER_OPT_Type { I2C_TRANSFER_POLLING = 0, I2C_TRANSFER_INTERRUPT } |
Transfer option type definitions. More... | |
enum | I2C_Mode { I2C_MASTER_MODE, I2C_SLAVE_MODE, I2C_GENERAL_MODE } |
enum | I2C_ID_Type { I2C0 = 0 } |
Functions | |
void | IP_I2C_Init (IP_I2C_001_Type *LPC_I2C) |
Initializes the LPC_I2C peripheral. | |
void | IP_I2C_DeInit (IP_I2C_001_Type *LPC_I2C) |
De-initializes the I2C peripheral registers to their default reset values. | |
void | IP_I2C_SetClockRate (IP_I2C_001_Type *LPC_I2C, uint32_t SCLValue) |
Set up clock rate for I2Cx. | |
void | IP_I2C_Cmd (IP_I2C_001_Type *LPC_I2C, I2C_Mode Mode, FunctionalState NewState) |
Enable or disable I2C peripheral's operation. | |
void | IP_I2C_Interrupt_MasterHandler (IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num) |
General Master Interrupt handler for I2C peripheral. | |
void | IP_I2C_Interrupt_SlaveHandler (IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num) |
General Slave Interrupt handler for I2C peripheral. | |
Status | IP_I2C_MasterTransferData (IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) |
Transmit and Receive data in master mode. | |
Status | IP_I2C_SlaveTransferData (IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) |
Receive and Transmit data in slave mode. | |
bool | IP_I2C_Interrupt_MasterTransferComplete (I2C_ID_Type I2C_Num) |
Get status of Master Transfer. | |
bool | IP_I2C_Interrupt_SlaveTransferComplete (I2C_ID_Type I2C_Num) |
Get status of Slave Transfer. | |
void | IP_I2C_SetOwnSlaveAddr (IP_I2C_001_Type *LPC_I2C, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct) |
Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct. | |
#define I2C_CheckError | ( | ErrorCode | ) | (ErrorCode & 0x10000000) |
#define I2C_I2ADR_BITMASK ((0xFF)) |
#define I2C_I2ADR_GC ((1 << 0)) |
#define I2C_I2CONCLR_AAC ((1 << 2)) |
#define I2C_I2CONCLR_I2ENC ((1 << 6)) |
#define I2C_I2CONCLR_SIC ((1 << 3)) |
#define I2C_I2CONSET_AA ((0x04)) |
#define I2C_I2DAT_BITMASK ((0xFF)) |
#define I2C_I2DAT_IDLE_CHAR (0xFF) |
#define I2C_I2MASK_MASK | ( | n | ) | ((n & 0xFE)) |
#define I2C_I2MMCTRL_BITMASK ((0x07)) |
#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) |
#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) |
#define I2C_I2SCLH_BITMASK ((0xFFFF)) |
#define I2C_I2SCLL_BITMASK ((0xFFFF)) |
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38)) |
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50)) |
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58)) |
#define I2C_I2STAT_M_RX_RESTART ((0x10)) |
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40)) |
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48)) |
#define I2C_I2STAT_M_RX_START ((0x08)) |
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38)) |
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28)) |
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30)) |
#define I2C_I2STAT_M_TX_RESTART ((0x10)) |
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18)) |
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20)) |
#define I2C_I2STAT_M_TX_START ((0x08)) |
#define I2C_I2STAT_NO_INF ((0xF8)) |
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78)) |
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68)) |
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70)) |
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90)) |
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98)) |
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80)) |
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88)) |
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60)) |
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0)) |
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0)) |
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8)) |
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0)) |
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8)) |
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8)) |
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL |
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL |
#define I2C_SETUP_STATUS_ARBF (1 << 8) |
#define I2C_SLAVE_TIME_OUT 0x10000000UL |
#define I2C_STA_STO_RECV 0x20 |
#define I2C_STA_STO_RECV 0x20 |
#define I2C_STAT_CODE_BITMASK ((0xF8)) |
#define I2C_STAT_CODE_ERROR ((0xFF)) |
#define I2DATA_BUFFER_BITMASK ((0xFF)) |
enum I2C_ID_Type |
enum I2C_Mode |
void IP_I2C_Cmd | ( | IP_I2C_001_Type * | LPC_I2C, |
I2C_Mode | Mode, | ||
FunctionalState | NewState | ||
) |
Enable or disable I2C peripheral's operation.
LPC_I2C | : Pointer to selected I2Cx peripheral |
Mode | : I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE |
NewState | : New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE |
void IP_I2C_DeInit | ( | IP_I2C_001_Type * | LPC_I2C | ) |
void IP_I2C_Init | ( | IP_I2C_001_Type * | LPC_I2C | ) |
void IP_I2C_Interrupt_MasterHandler | ( | IP_I2C_001_Type * | LPC_I2C, |
I2C_ID_Type | I2C_Num | ||
) |
bool IP_I2C_Interrupt_MasterTransferComplete | ( | I2C_ID_Type | I2C_Num | ) |
void IP_I2C_Interrupt_SlaveHandler | ( | IP_I2C_001_Type * | LPC_I2C, |
I2C_ID_Type | I2C_Num | ||
) |
bool IP_I2C_Interrupt_SlaveTransferComplete | ( | I2C_ID_Type | I2C_Num | ) |
Status IP_I2C_MasterTransferData | ( | IP_I2C_001_Type * | LPC_I2C, |
I2C_ID_Type | I2C_Num, | ||
I2C_M_SETUP_Type * | TransferCfg, | ||
I2C_TRANSFER_OPT_Type | Opt | ||
) |
Transmit and Receive data in master mode.
LPC_I2C | : Pointer to selected I2Cx peripheral |
I2C_Num | : I2C port number, should be I2C0, I2C1 or I2C2 |
TransferCfg | : Pointer to a I2C_M_SETUP_Type structure that contains specified information about the configuration for master transfer. |
Opt | : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. |
Note:
void IP_I2C_SetClockRate | ( | IP_I2C_001_Type * | LPC_I2C, |
uint32_t | SCLValue | ||
) |
void IP_I2C_SetOwnSlaveAddr | ( | IP_I2C_001_Type * | LPC_I2C, |
I2C_OWNSLAVEADDR_CFG_Type * | OwnSlaveAddrConfigStruct | ||
) |
Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct.
LPC_I2C | : I2C peripheral selected |
OwnSlaveAddrConfigStruct | : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the configuration information for the specified I2C slave address. |
Status IP_I2C_SlaveTransferData | ( | IP_I2C_001_Type * | LPC_I2C, |
I2C_ID_Type | I2C_Num, | ||
I2C_S_SETUP_Type * | TransferCfg, | ||
I2C_TRANSFER_OPT_Type | Opt | ||
) |
Receive and Transmit data in slave mode.
LPC_I2C | : Pointer to selected I2Cx peripheral |
I2C_Num | : I2C port number, should be I2C0, I2C1 or I2C2 |
TransferCfg | : Pointer to a I2C_S_SETUP_Type structure that contains specified information about the configuration for master transfer. |
Opt | : I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. |
Note: The mode of slave's operation depends on the command sent from master on the I2C bus. If the master send a SLA+W command, this sub-routine will use receive data length and receive data pointer. If the master send a SLA+R command, this sub-routine will use transmit data length and transmit data pointer. If the master issue an repeat start command or a stop command, the slave will enable an time out condition, during time out condition, if there's no activity on I2C bus, the slave will exit, otherwise (i.e. the master send a SLA+R/W), the slave then switch to relevant operation mode. The time out should be used because the return status code can not show difference from stop and repeat start command in slave operation. In case of the expected data length from master is greater than data length that slave can support: