50 #if defined(CHIP_LPC43XX)
51 {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},
55 #if defined(CHIP_LPC43XX)
56 {CLK_SPI, CLK_SPI, CLK_BASE_SPI},
57 {CLK_VADC, CLK_VADC, CLK_BASE_VADC},
82 uint32_t TestHz = TestMult * InputHz;
84 if ((TestHz < MinHz) || (TestHz >
MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {
108 while ((baseclk ==
CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {
109 if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {
110 baseclk = periph_to_base[i].
clkbase;
130 OldCrystalConfig &= (~2);
131 if (OldCrystalConfig !=
LPC_CGU->XTAL_OSC_CTRL) {
132 LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
136 OldCrystalConfig &= (~1);
138 OldCrystalConfig |= 4;
141 LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
148 LPC_CGU->XTAL_OSC_CTRL &= (~1);
158 if (DesiredHz != 0xFFFFFFFF) {
160 Mult = DesiredHz / freqin;
167 if (freqout && !freqout2) {
171 if (!freqout && freqout2) {
175 if (freqout && freqout2) {
176 if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {
188 Mult = MinHz / freqin;
189 MultEnd = MaxHz / freqin;
198 if (Mult >= MultEnd) {
215 uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
221 PLLReg &= ~(0x1F << 24);
222 PLLReg |= Input << 24;
225 PLLReg &= ~((1 << 6) |
228 (0x03 << 8) | (0xFF << 16) | (0x03 << 12));
230 if (freq < 156000000) {
232 while ((2 * (pval) * freq) < 156000000) {
237 PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6);
239 else if (freq < 320000000) {
240 PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6);
246 LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);
256 uint32_t msel, nsel, psel, direct, fbsel;
258 const uint8_t ptab[] = {1, 2, 4, 8};
261 if (!(
LPC_CGU->PLL1_STAT & 1)) {
265 msel = (PLLReg >> 16) & 0xFF;
266 nsel = (PLLReg >> 12) & 0x3;
267 psel = (PLLReg >> 8) & 0x3;
268 direct = (PLLReg >> 7) & 0x1;
269 fbsel = (PLLReg >> 6) & 0x1;
275 if (direct || fbsel) {
276 return m * (freq / n);
279 return (m / (2 * p)) * (freq / n);
293 return (
bool) (
LPC_CGU->PLL1_STAT & 1);
305 reg &= ~((0x1F << 24) | 1 | (0xF << 2));
308 LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);
311 LPC_CGU->IDIV_CTRL[Divider] = reg | 1;
348 #if defined(USE_RMII)
357 #if defined(USE_RMII)
367 #if defined(EXTERNAL_CLKIN_FREQ_IN)
435 reg &= ~((0x1F << 24) | 1 | (1 << 11));
445 reg |= (Input << 24);
447 LPC_CGU->BASE_CLK[BaseClock] = reg;
451 LPC_CGU->BASE_CLK[BaseClock] = reg | 1;
459 LPC_CGU->BASE_CLK[BaseClock] &= ~1;
467 LPC_CGU->BASE_CLK[BaseClock] |= 1;
562 if (((reg >> 5) & 0x7) == 0) {