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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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LPC18XX/43XX CGU register block structure. More...
#include "cguccu_18xx_43xx.h"
Data Fields | |
__I uint32_t | RESERVED0 [5] |
__IO uint32_t | FREQ_MON |
__IO uint32_t | XTAL_OSC_CTRL |
__I uint32_t | PLL0USB_STAT |
__IO uint32_t | PLL0USB_CTRL |
__IO uint32_t | PLL0USB_MDIV |
__IO uint32_t | PLL0USB_NP_DIV |
__I uint32_t | PLL0AUDIO_STAT |
__IO uint32_t | PLL0AUDIO_CTRL |
__IO uint32_t | PLL0AUDIO_MDIV |
__IO uint32_t | PLL0AUDIO_NP_DIV |
__IO uint32_t | PLL0AUDIO_FRAC |
__I uint32_t | PLL1_STAT |
__IO uint32_t | PLL1_CTRL |
__IO uint32_t | IDIV_CTRL [CLK_IDIV_LAST] |
__IO uint32_t | BASE_CLK [CLK_BASE_LAST] |
LPC18XX/43XX CGU register block structure.
Definition at line 49 of file cguccu_18xx_43xx.h.
__IO uint32_t BASE_CLK[CLK_BASE_LAST] |
(@ 0x4005005C) Start of base clock registers
Definition at line 65 of file cguccu_18xx_43xx.h.
__IO uint32_t FREQ_MON |
(@ 0x40050014) Frequency monitor register
Definition at line 51 of file cguccu_18xx_43xx.h.
__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST] |
(@ 0x40050048) Integer divider A-E control registers
Definition at line 64 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0AUDIO_CTRL |
(@ 0x40050030) PLL0 (audio) control register
Definition at line 58 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0AUDIO_FRAC |
(@ 0x4005003C) PLL0 (audio)
Definition at line 61 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0AUDIO_MDIV |
(@ 0x40050034) PLL0 (audio) M-divider register
Definition at line 59 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0AUDIO_NP_DIV |
(@ 0x40050038) PLL0 (audio) N/P-divider register
Definition at line 60 of file cguccu_18xx_43xx.h.
__I uint32_t PLL0AUDIO_STAT |
(@ 0x4005002C) PLL0 (audio) status register
Definition at line 57 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0USB_CTRL |
(@ 0x40050020) PLL0 (USB) control register
Definition at line 54 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0USB_MDIV |
(@ 0x40050024) PLL0 (USB) M-divider register
Definition at line 55 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL0USB_NP_DIV |
(@ 0x40050028) PLL0 (USB) N/P-divider register
Definition at line 56 of file cguccu_18xx_43xx.h.
__I uint32_t PLL0USB_STAT |
(@ 0x4005001C) PLL0 (USB) status register
Definition at line 53 of file cguccu_18xx_43xx.h.
__IO uint32_t PLL1_CTRL |
(@ 0x40050044) PLL1 control register
Definition at line 63 of file cguccu_18xx_43xx.h.
__I uint32_t PLL1_STAT |
(@ 0x40050040) PLL1 status register
Definition at line 62 of file cguccu_18xx_43xx.h.
__I uint32_t RESERVED0[5] |
< (@ 0x40050000) CGU Structure
Definition at line 50 of file cguccu_18xx_43xx.h.
__IO uint32_t XTAL_OSC_CTRL |
(@ 0x40050018) Crystal oscillator control register
Definition at line 52 of file cguccu_18xx_43xx.h.