LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
ssp_001.c
Go to the documentation of this file.
1 /*
2  * @brief SSP Registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #include "ssp_001.h"
33 
34 /*****************************************************************************
35  * Private types/enumerations/variables
36  ****************************************************************************/
37 
38 /*****************************************************************************
39  * Public types/enumerations/variables
40  ****************************************************************************/
41 
42 /*****************************************************************************
43  * Private functions
44  ****************************************************************************/
45 
46 /*****************************************************************************
47  * Public functions
48  ****************************************************************************/
49 
50 /*Set up output clocks per bit for SSP bus*/
51 void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale)
52 {
53  pSSP->CR0 &= ~(SSP_CR0_SCR(0xFF));
54  pSSP->CR0 |= SSP_CR0_SCR(clk_rate);
55  pSSP->CPSR = prescale;
56 }
57 
58 /* Set up the SSP frame format */
59 void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat)
60 {
61  pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockFormat;
62 }
63 
64 /* Set the SSP working as master or slave mode */
66 {
67  pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
68 }
69 
70 /* Disable SSP operation */
72 {
73  pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
74 }
75 
76 /* Enable/Disable SSP operation */
78 {
79  if (NewState == ENABLE) {
80  pSSP->CR1 |= SSP_CR1_SSP_EN;
81  }
82  else {
83  pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
84  }
85 }
86 
87 /* Send SSP 16-bit data */
88 void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data)
89 {
90  pSSP->DR = SSP_DR_BITMASK(tx_data);
91 }
92 
93 /* Get received SSP data */
95 {
96  return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
97 }
98 
99 /* Enable/Disable loopback mode */
101 {
102 
103  if (NewState == ENABLE) {
104  pSSP->CR1 |= SSP_CR1_LBM_EN;
105  }
106  else {
107  pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
108  }
109 }
110 
111 /* Get the raw interrupt status */
113 {
114  return (pSSP->RIS & RawInt) ? SET : RESET;
115 }
116 
117 /* Get the masked interrupt status */
119 {
120  return pSSP->MIS;
121 }
122 
123 /* Clear the corresponding interrupt condition(s) in the SSP controller */
125 {
126  pSSP->ICR = IntClear;
127 }
128 
129 /* Get the current status of SSP controller */
131 {
132  return (pSSP->SR & Stat) ? SET : RESET;
133 }
134 
135 /* Get the number of bits transferred in each frame */
137 {
138  return SSP_CR0_DSS(pSSP->CR0);
139 }
140 
141 /* Enable/Disable interrupt for the SSP */
143 {
144  if (NewState == ENABLE) {
145  pSSP->IMSC |= IntType;
146  }
147  else {
148  pSSP->IMSC &= (~IntType);
149  }
150 }
151 
152 /* Enable/Disable DMA for SSP */
154 {
155 #if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX)
156  if (NewState == ENABLE) {
157  pSSP->DMACR |= ssp_dma_t;
158  }
159  else {
160  pSSP->DMACR &= (~ssp_dma_t);
161  }
162 #endif
163 }