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i2s_001.h
Go to the documentation of this file.
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/*
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* @brief I2S Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __I2S_001_H_
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#define __I2S_001_H_
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#include "sys_config.h"
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#include "
cmsis.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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__IO
uint32_t
DAO
;
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__IO
uint32_t
DAI
;
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__O
uint32_t
TXFIFO
;
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__I
uint32_t
RXFIFO
;
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__I
uint32_t
STATE
;
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__IO
uint32_t
DMA1
;
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__IO
uint32_t
DMA2
;
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__IO
uint32_t
IRQ
;
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__IO
uint32_t
TXRATE
;
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__IO
uint32_t
RXRATE
;
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__IO
uint32_t
TXBITRATE
;
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__IO
uint32_t
RXBITRATE
;
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__IO
uint32_t
TXMODE
;
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__IO
uint32_t
RXMODE
;
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}
IP_I2S_001_Type
;
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#define I2S_WORDWIDTH_8 (0UL << 0)
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#define I2S_WORDWIDTH_16 (1UL << 0)
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#define I2S_WORDWIDTH_32 (3UL << 0)
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#define I2S_STEREO (0UL << 2)
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#define I2S_MONO (1UL << 2)
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#define I2S_MASTER_MODE (0UL << 5)
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#define I2S_SLAVE_MODE (1UL << 5)
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#define I2S_STOP_ENABLE (0UL << 3)
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#define I2S_STOP_DISABLE (1UL << 3)
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#define I2S_RESET_ENABLE (1UL << 4)
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#define I2S_RESET_DISABLE (0UL << 4)
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#define I2S_MUTE_ENABLE (1UL << 15)
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#define I2S_MUTE_DISABLE (0UL << 15)
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#define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0))
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#define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1))
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#define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3))
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#define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
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#define I2S_DAO_MONO ((uint32_t) (1 << 2))
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#define I2S_DAO_STOP ((uint32_t) (1 << 3))
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#define I2S_DAO_RESET ((uint32_t) (1 << 4))
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#define I2S_DAO_SLAVE ((uint32_t) (1 << 5))
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#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))
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#define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
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#define I2S_DAO_MUTE ((uint32_t) (1 << 15))
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#define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0))
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#define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1))
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#define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3))
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#define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3))
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#define I2S_DAI_MONO ((uint32_t) (1 << 2))
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#define I2S_DAI_STOP ((uint32_t) (1 << 3))
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#define I2S_DAI_RESET ((uint32_t) (1 << 4))
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#define I2S_DAI_SLAVE ((uint32_t) (1 << 5))
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#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6))
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#define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
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#define I2S_STATE_IRQ ((uint32_t) (1))
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#define I2S_STATE_DMA1 ((uint32_t) (1 << 1))
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#define I2S_STATE_DMA2 ((uint32_t) (1 << 2))
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#define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))
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#define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16))
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#define I2S_DMA1_RX_ENABLE ((uint32_t) (1))
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#define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1))
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#define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
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#define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
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#define I2S_DMA2_RX_ENABLE ((uint32_t) (1))
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#define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1))
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#define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
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#define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
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#define I2S_IRQ_RX_ENABLE ((uint32_t) (1))
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#define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1))
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#define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8))
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#define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
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#define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16))
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#define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
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#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
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#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
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#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
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#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
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#define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
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#define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
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#define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
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#define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
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#define I2S_TXMODE_MCENA ((uint32_t) (1 << 3))
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#define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
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#define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
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#define I2S_RXMODE_MCENA ((uint32_t) (1 << 3))
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typedef
enum
{
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I2S_TX_MODE
,
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I2S_RX_MODE
,
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}
IP_I2S_TRxMode_Type
;
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typedef
enum
{
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IP_I2S_DMA_REQUEST_NUMBER_1
,
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IP_I2S_DMA_REQUEST_NUMBER_2
,
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}
IP_I2S_DMARequestNumber_Type
;
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/**********************************************************************************
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* I2S Init/DeInit functions
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*********************************************************************************/
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void
IP_I2S_Init
(
IP_I2S_001_Type
*pI2S);
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void
IP_I2S_DeInit
(
IP_I2S_001_Type
*pI2S);
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/**********************************************************************************
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* I2S configuration functions
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*********************************************************************************/
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void
IP_I2S_SetWordWidth
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
wordwidth);
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void
IP_I2S_SetMono
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
mono);
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void
IP_I2S_SetMasterSlaveMode
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
mode
);
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void
IP_I2S_SetBitRate
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
mclk_divider);
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void
IP_I2S_SetXYDivider
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider);
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void
IP_I2S_SetWS_Halfperiod
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
ws_halfperiod);
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void
IP_I2S_ModeConfig
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
clksel,
uint32_t
fpin,
uint32_t
mcena);
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uint8_t
IP_I2S_GetLevel
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode);
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/**********************************************************************************
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* I2S operate functions
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*********************************************************************************/
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void
IP_I2S_Send
(
IP_I2S_001_Type
*pI2S,
uint32_t
data);
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uint32_t
IP_I2S_Receive
(
IP_I2S_001_Type
*pI2S);
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void
IP_I2S_Start
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode);
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void
IP_I2S_Pause
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode);
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void
IP_I2S_Mute
(
IP_I2S_001_Type
*pI2S,
FunctionalState
NewState);
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void
IP_I2S_Stop
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode);
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/**********************************************************************************
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* I2S DMA functions
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*********************************************************************************/
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void
IP_I2S_SetFIFODepthDMA
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
IP_I2S_DMARequestNumber_Type
DMANum,
uint32_t
depth);
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void
IP_I2S_DMACmd
(
IP_I2S_001_Type
*pI2S,
IP_I2S_DMARequestNumber_Type
DMANum, uint8_t TRMode,
FunctionalState
NewState);
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/**********************************************************************************
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* I2S IRQ functions
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*********************************************************************************/
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void
IP_I2S_InterruptCmd
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
FunctionalState
NewState);
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void
IP_I2S_SetFIFODepthIRQ
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode,
uint32_t
depth);
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Status
IP_I2S_GetIntStatus
(
IP_I2S_001_Type
*pI2S, uint8_t TRMode);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __I2S_001_H_ */
software
lpc_core
lpc_ip
i2s_001.h
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