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scu_18xx_43xx.h
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1 /*
2  * Copyright(C) NXP Semiconductors, 2012
3  * All rights reserved.
4  *
5  * Software that is described herein is for illustrative purposes only
6  * which provides customers with programming information regarding the
7  * LPC products. This software is supplied "AS IS" without any warranties of
8  * any kind, and NXP Semiconductors and its licensor disclaim any and
9  * all warranties, express or implied, including all implied warranties of
10  * merchantability, fitness for a particular purpose and non-infringement of
11  * intellectual property rights. NXP Semiconductors assumes no responsibility
12  * or liability for the use of the software, conveys no license or rights under any
13  * patent, copyright, mask work right, or any other intellectual property rights in
14  * or to any products. NXP Semiconductors reserves the right to make changes
15  * in the software without notification. NXP Semiconductors also makes no
16  * representation or warranty that such application will be suitable for the
17  * specified use without further testing or modification.
18  *
19  * Permission to use, copy, modify, and distribute this software and its
20  * documentation is hereby granted, under NXP Semiconductors' and its
21  * licensor's relevant copyrights in the software, without fee, provided that it
22  * is used in conjunction with NXP Semiconductors microcontrollers. This
23  * copyright, permission, and disclaimer notice must appear in all copies of
24  * this code.
25  */
26 
27 #ifndef __SCU_18XX_43XX_H_
28 #define __SCU_18XX_43XX_H_
29 
30 #include "chip.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
44 typedef struct {
45  __IO uint32_t SFSP[16][32];
46  __I uint32_t RESERVED0[256];
47  __IO uint32_t SFSCLK[4];
48  __I uint32_t RESERVED16[28];
51  __IO uint32_t ENAIO[3];
52  __I uint32_t RESERVED17[27];
54  __I uint32_t RESERVED18[63];
57 } LPC_SCU_Type;
58 
60 #define PORT_OFFSET 0x80
61 
63 #define PIN_OFFSET 0x04
64 
66 #define MD_PUP (0x0 << 3)
67 
69 #define MD_BUK (0x1 << 3)
70 
72 #define MD_PLN (0x2 << 3)
73 
75 #define MD_PDN (0x3 << 3)
76 
78 #define MD_EHS (0x1 << 5)
79 
81 #define MD_EZI (0x1 << 6)
82 
84 #define MD_ZI (0x1 << 7)
85 
87 #define MD_EHD0 (0x1 << 8)
88 
90 #define MD_EHD1 (0x1 << 8)
91 
92 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
93 
95 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11)
96 
98 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
99 
100 #define FUNC0 0x0
101 #define FUNC1 0x1
102 #define FUNC2 0x2
103 #define FUNC3 0x3
104 #define FUNC4 0x4
105 #define FUNC5 0x5
106 #define FUNC6 0x6
107 #define FUNC7 0x7
110 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
111 
113 #define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
114 
115 #define PINMUX_CLK 0xFF
116 
129 void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
130 
138 void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
139 
148 {
149  LPC_SCU->SFSI2C0 = I2C0Mode;
150 }
151 
158 STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
159 {
160  LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
161 }
162 
167 #ifdef __cplusplus
168 }
169 #endif
170 
171 #endif /* __SCU_18XX_43XX_H_ */