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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Go to the source code of this file.
Data Structures | |
struct | IP_USART_001_Type |
USART register block structure. More... | |
struct | UART_RingBuffer_Type |
UART Ring buffer structure. More... | |
struct | UART_FIFO_CFG_Type |
UART FIFO Configuration Structure definition. More... | |
Macros | |
#define | UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) |
#define | UART_ACCEPTED_BAUDRATE_ERROR (3) |
#define | UART_RBR_MASKBIT ((uint8_t) 0xFF) |
Macro defines for UARTn Receiver Buffer Register. | |
#define | UART_THR_MASKBIT ((uint8_t) 0xFF) |
Macro defines for UARTn Transmit Holding Register. | |
#define | UART_LOAD_DLL(div) ((div) & 0xFF) |
Macro defines for UARTn Divisor Latch LSB register. | |
#define | UART_DLL_MASKBIT ((uint8_t) 0xFF) |
#define | UART_DLM_MASKBIT ((uint8_t) 0xFF) |
Macro defines for UARTn Divisor Latch MSB register. | |
#define | UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) |
#define | UART_IER_RBRINT_EN ((uint32_t) (1 << 0)) |
Macro defines for UART interrupt enable register. | |
#define | UART_IER_THREINT_EN ((uint32_t) (1 << 1)) |
#define | UART_IER_RLSINT_EN ((uint32_t) (1 << 2)) |
#define | UART_IER_MSINT_EN ((uint32_t) (1 << 3)) |
#define | UART_IER_CTSINT_EN ((uint32_t) (1 << 7)) |
#define | UART_IER_ABEOINT_EN ((uint32_t) (1 << 8)) |
#define | UART_IER_ABTOINT_EN ((uint32_t) (1 << 9)) |
#define | UART_IER_BITMASK ((uint32_t) (0x307)) |
#define | UART1_IER_BITMASK ((uint32_t) (0x38F)) |
#define | UART_IIR_INTSTAT_PEND ((uint32_t) (1 << 0)) |
Macro defines for UART interrupt identification register. | |
#define | UART_IIR_INTID_RLS ((uint32_t) (3 << 1)) |
#define | UART_IIR_INTID_RDA ((uint32_t) (2 << 1)) |
#define | UART_IIR_INTID_CTI ((uint32_t) (6 << 1)) |
#define | UART_IIR_INTID_THRE ((uint32_t) (1 << 1)) |
#define | UART_IIR_INTID_MODEM ((uint32_t) (0 << 1)) |
#define | UART_IIR_INTID_MASK ((uint32_t) (7 << 1)) |
#define | UART_IIR_FIFO_EN ((uint32_t) (3 << 6)) |
#define | UART_IIR_ABEO_INT ((uint32_t) (1 << 8)) |
#define | UART_IIR_ABTO_INT ((uint32_t) (1 << 9)) |
#define | UART_IIR_BITMASK ((uint32_t) (0x3CF)) |
#define | UART_FCR_FIFO_EN ((uint8_t) (1 << 0)) |
Macro defines for UART FIFO control register. | |
#define | UART_FCR_RX_RS ((uint8_t) (1 << 1)) |
#define | UART_FCR_TX_RS ((uint8_t) (1 << 2)) |
#define | UART_FCR_DMAMODE_SEL ((uint8_t) (1 << 3)) |
#define | UART_FCR_TRG_LEV0 ((uint8_t) (0)) |
#define | UART_FCR_TRG_LEV1 ((uint8_t) (1 << 6)) |
#define | UART_FCR_TRG_LEV2 ((uint8_t) (2 << 6)) |
#define | UART_FCR_TRG_LEV3 ((uint8_t) (3 << 6)) |
#define | UART_FCR_BITMASK ((uint8_t) (0xCF)) |
#define | UART_TX_FIFO_SIZE (16) |
#define | UART_LCR_WLEN5 ((uint8_t) (0)) |
Macro defines for UART line control register. | |
#define | UART_LCR_WLEN6 ((uint8_t) (1 << 0)) |
#define | UART_LCR_WLEN7 ((uint8_t) (2 << 0)) |
#define | UART_LCR_WLEN8 ((uint8_t) (3 << 0)) |
#define | UART_LCR_SBS_1BIT ((uint8_t) (0 << 2)) |
#define | UART_LCR_SBS_2BIT ((uint8_t) (1 << 2)) |
#define | UART_LCR_PARITY_EN ((uint8_t) (1 << 3)) |
#define | UART_LCR_PARITY_DIS ((uint8_t) (0 << 3)) |
#define | UART_LCR_PARITY_ODD ((uint8_t) (0)) |
#define | UART_LCR_PARITY_EVEN ((uint8_t) (1 << 4)) |
#define | UART_LCR_PARITY_F_1 ((uint8_t) (2 << 4)) |
#define | UART_LCR_PARITY_F_0 ((uint8_t) (3 << 4)) |
#define | UART_LCR_BREAK_EN ((uint8_t) (1 << 6)) |
#define | UART_LCR_DLAB_EN ((uint8_t) (1 << 7)) |
#define | UART_LCR_BITMASK ((uint8_t) (0xFF)) |
#define | UART_MCR_DTR_CTRL ((uint8_t) (1 << 0)) |
Macro defines for UART Modem control register. | |
#define | UART_MCR_RTS_CTRL ((uint8_t) (1 << 1)) |
#define | UART_MCR_LOOPB_EN ((uint8_t) (1 << 4)) |
#define | UART_MCR_AUTO_RTS_EN ((uint8_t) (1 << 6)) |
#define | UART_MCR_AUTO_CTS_EN ((uint8_t) (1 << 7)) |
#define | UART_MCR_BITMASK ((uint8_t) (0x0F3)) |
#define | UART_LSR_RDR ((uint8_t) (1 << 0)) |
Macro defines for UART line status register. | |
#define | UART_LSR_OE ((uint8_t) (1 << 1)) |
#define | UART_LSR_PE ((uint8_t) (1 << 2)) |
#define | UART_LSR_FE ((uint8_t) (1 << 3)) |
#define | UART_LSR_BI ((uint8_t) (1 << 4)) |
#define | UART_LSR_THRE ((uint8_t) (1 << 5)) |
#define | UART_LSR_TEMT ((uint8_t) (1 << 6)) |
#define | UART_LSR_RXFE ((uint8_t) (1 << 7)) |
#define | UART_LSR_BITMASK ((uint8_t) (0xFF)) |
#define | UART_MSR_DELTA_CTS ((uint8_t) (1 << 0)) |
Macro defines for UART Modem status register. | |
#define | UART_MSR_DELTA_DSR ((uint8_t) (1 << 1)) |
#define | UART_MSR_LO2HI_RI ((uint8_t) (1 << 2)) |
#define | UART_MSR_DELTA_DCD ((uint8_t) (1 << 3)) |
#define | UART_MSR_CTS ((uint8_t) (1 << 4)) |
#define | UART_MSR_DSR ((uint8_t) (1 << 5)) |
#define | UART_MSR_RI ((uint8_t) (1 << 6)) |
#define | UART_MSR_DCD ((uint8_t) (1 << 7)) |
#define | UART_MSR_BITMASK ((uint8_t) (0xFF)) |
#define | UART_SCR_BIMASK ((uint8_t) (0xFF)) |
Macro defines for UART Scratch Pad register. | |
#define | UART_ACR_START ((uint32_t) (1 << 0)) |
Macro defines for UART Auto baudrate control register. | |
#define | UART_ACR_MODE ((uint32_t) (1 << 1)) |
#define | UART_ACR_AUTO_RESTART ((uint32_t) (1 << 2)) |
#define | UART_ACR_ABEOINT_CLR ((uint32_t) (1 << 8)) |
#define | UART_ACR_ABTOINT_CLR ((uint32_t) (1 << 9)) |
#define | UART_ACR_BITMASK ((uint32_t) (0x307)) |
#define | UART_ICR_IRDAEN ((uint32_t) (1 << 0)) |
Macro defines for UART IrDA control register. | |
#define | UART_ICR_IRDAINV ((uint32_t) (1 << 1)) |
#define | UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2)) |
#define | UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3)) |
#define | UART_ICR_BITMASK ((uint32_t) (0x3F)) |
#define | UART_HDEN_HDEN ((uint32_t) (1 << 0)) |
Macro defines for UART half duplex register. | |
#define | UART_SCICTRL_SCIEN ((uint32_t) (1 << 0)) |
Macro defines for UART smart card interface control register. | |
#define | UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1)) |
#define | UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2)) |
#define | UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5)) |
#define | UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8)) |
#define | UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0)) |
Macro defines for UART synchronous control register. | |
#define | UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1)) |
#define | UART_SYNCCTRL_FES ((uint32_t) (1 << 2)) |
#define | UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3)) |
#define | UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4)) |
#define | UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5)) |
#define | UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6)) |
#define | UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F)) |
Macro defines for UART Fractional divider register. | |
#define | UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0)) |
#define | UART_FDR_BITMASK ((uint32_t) (0xFF)) |
#define | UART_TER1_TXEN ((uint8_t) (1 << 7)) |
Macro defines for UART Tx Enable register. | |
#define | UART_TER1_BITMASK ((uint8_t) (0x80)) |
#define | UART_TER2_TXEN ((uint8_t) (1 << 0)) |
#define | UART_TER2_BITMASK ((uint8_t) (0x01)) |
#define | UART_RS485CTRL_NMM_EN ((uint32_t) (1 << 0)) |
Macro defines for UART1 RS485 Control register. | |
#define | UART_RS485CTRL_RX_DIS ((uint32_t) (1 << 1)) |
#define | UART_RS485CTRL_AADEN ((uint32_t) (1 << 2)) |
#define | UART_RS485CTRL_SEL_DTR ((uint32_t) (1 << 3)) |
#define | UART_RS485CTRL_DCTRL_EN ((uint32_t) (1 << 4)) |
#define | UART_RS485CTRL_OINV_1 ((uint32_t) (1 << 5)) |
#define | UART_RS485CTRL_BITMASK ((uint32_t) (0x3F)) |
#define | UART_RS485ADRMATCH_BITMASK ((uint8_t) (0xFF)) |
Macro defines for UART1 RS-485 Address Match register. | |
#define | UART_RS485DLY_BITMASK ((uint8_t) (0xFF)) |
Macro defines for UART1 RS-485 Delay value register. | |
#define | UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t) (n & 0x0F)) |
Macro defines for UART FIFO Level register. | |
#define | UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t) ((n >> 8) & 0x0F)) |
#define | UART_FIFOLVL_BITMASK ((uint32_t) (0x0F0F)) |
#define | UART_RING_BUFSIZE 256 |
Macro defines for Ring Buffer. | |
Functions | |
void | IP_UART_Init (IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort) |
Initializes the UARTx peripheral according to the specified parameters in the UART_ConfigStruct. | |
void | IP_UART_DeInit (IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort) |
De-initializes the UARTx peripheral registers to their default reset values. | |
Status | IP_UART_SetBaud (IP_USART_001_Type *LPC_UART, uint32_t baudrate, uint32_t uClk) |
Determines best dividers to get a target clock rate. | |
void | IP_UART_ConfigData (IP_USART_001_Type *LPC_UART, UART_DATABIT_Type Databits, UART_PARITY_Type Parity, UART_STOPBIT_Type Stopbits) |
Configure data width, parity mode and stop bits. | |
Status | IP_UART_SendByte (IP_USART_001_Type *LPC_UART, uint8_t Data) |
Transmit a single data through UART peripheral. | |
Status | IP_UART_ReceiveByte (IP_USART_001_Type *LPC_UART, uint8_t *Data) |
Receive a single data from UART peripheral. | |
uint32_t | IP_UART_Send (IP_USART_001_Type *LPC_UART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag) |
Send a block of data via UART peripheral. | |
uint32_t | IP_UART_Receive (IP_USART_001_Type *LPC_UART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag) |
Receive a block of data via UART peripheral. | |
void | IP_UART_IntConfig (IP_USART_001_Type *LPC_UART, UART_INT_Type UARTIntCfg, FunctionalState NewState) |
Enable or disable specified UART interrupt. | |
uint32_t | IP_UART_IntGetStatus (IP_USART_001_Type *LPC_UART) |
Get Source Interrupt. | |
void | IP_UART_ForceBreak (IP_USART_001_Type *LPC_UART) |
Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0. | |
uint8_t | IP_UART_GetLineStatus (IP_USART_001_Type *LPC_UART) |
Get current value of Line Status register in UART peripheral. | |
FlagStatus | IP_UART_CheckBusy (IP_USART_001_Type *LPC_UART) |
Check whether if UART is busy or not. | |
void | IP_UART_TxCmd (IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort, FunctionalState NewState) |
Enable/Disable transmission on UART TxD pin. | |
void | IP_UART_FIFOConfig (IP_USART_001_Type *LPC_UART, UART_FIFO_CFG_Type *FIFOCfg) |
Configure FIFO function on selected UART peripheral. | |
void | IP_UART_FIFOConfigStructInit (UART_FIFO_CFG_Type *UART_FIFOInitStruct) |
Fills each UART_FIFOInitStruct member with its default value: | |