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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Go to the source code of this file.
Data Structures | |
union | NextLinkPointer |
struct | PHCD_QTD |
struct | st_EHCD_QHD |
struct | st_EHCD_ITD |
struct | st_EHCD_SITD |
struct | EHCI_HOST_DATA_Type |
struct | Pipe_Handle_Type |
Macros | |
#define | HCD_MAX_QHD HCD_MAX_ENDPOINT /* USBD_USB_HC_EHCI */ |
#define | HCD_MAX_QTD (HCD_MAX_ENDPOINT + 3) /* USBD_USB_HC_EHCI */ |
#define | HCD_MAX_HS_ITD 4 /* USBD_USB_HC_EHCI */ |
#define | HCD_MAX_SITD 16 /* USBD_USB_HC_EHCI */ |
#define | FRAMELIST_SIZE_BITS 5 /* (0:1024) - (1:512) - (2:256) - (3:128) - (4:64) - (5:32) - (6:16) - (7:8) */ |
#define | FRAME_LIST_SIZE (1024 >> FRAMELIST_SIZE_BITS) |
#define | INT_THRESHOLD_CTRL 0x00080000UL/* Max Int Interval = 8 uframes */ |
#define | ASYNC_SCHEDULE_PARK_MODE_ENABLE NO |
#define | ASYNC_SCHEDULE_PARK_MODE_COUNT 0 |
#define | INT_SOF_RECEIVED_ENABLE NO |
#define | INT_FRAME_ROLL_OVER_ENABLE NO |
#define | PORT_WAKE_OVER_CURRENT NO |
#define | PORT_WAKE_ON_DISCONNECT NO |
#define | PORT_WAKE_ON_CONNECT NO |
#define | PORT_INDICATOR NO |
#define | USBMODE_DeviceController (2) |
#define | USBMODE_HostController (3) |
#define | USBMODE_VBusPowerSelect_High (1 << 5) |
#define | EHC_USBCMD_RunStop 0x00000001UL /* Run or Stop */ |
#define | EHC_USBCMD_HostReset 0x00000002UL /* Host Controller Reset */ |
#define | EHC_USBCMD_FrameListSize 0x0000000CUL /* Frame List Size */ |
#define | EHC_USBCMD_PeriodScheduleEnable 0x00000010UL /* Periodic Schedule Enable */ |
#define | EHC_USBCMD_AsynScheduleEnable 0x00000020UL /* Asynchronous Schedule Enable */ |
#define | EHC_USBCMD_IntAsyncAdvanceDoorbell 0x00000040UL /* Interrupt on Async Advance Doorbell */ |
#define | EHC_USBCMD_LightReset 0x00000080UL /* Light Host Controller Reset */ |
#define | EHC_USBCMD_AsyncScheduleParkCount 0x00000300UL /* Asynchronous Schedule Park Mode Count */ |
#define | EHC_USBCMD_AsyncScheduleParkEnable 0x00000800UL /* Asynchronous Schedule Park Mode Enable */ |
#define | EHC_USBCMD_FrameListSizeBit2 0x00008000UL /* Frame List Size bit 2 - EHCI derivation */ |
#define | EHC_USBCMD_InterruptThresholdControl 0x00FF0000UL /* Interrupt Threshold control */ |
#define | EHC_USBSTS_UsbInt 0x00000001UL /* USB Interrupt */ |
#define | EHC_USBSTS_UsbErrorInt 0x00000002UL /* USB Error Interrupt */ |
#define | EHC_USBSTS_PortChangeDetect 0x00000004UL /* Port Change Detect */ |
#define | EHC_USBSTS_FrameListRollover 0x00000008UL /* Frame List Rollover */ |
#define | EHC_USBSTS_HostSystemError 0x00000010UL /* Host System Error */ |
#define | EHC_USBSTS_IntAsyncAdvance 0x00000020UL /* Interrupt on Async Advance */ |
#define | EHC_USBSTS_SofRecieveInt 0x00000080UL /* SOF - EHCI derivation */ |
#define | EHC_USBSTS_HCHalted 0x00001000UL /* HCHalted */ |
#define | EHC_USBSTS_Reclamation 0x00002000UL /* Reclamation */ |
#define | EHC_USBSTS_PeriodScheduleStatus 0x00004000UL /* Periodic Schedule Status */ |
#define | EHC_USBSTS_AsyncScheduleStatus 0x00008000UL /* Asynchronous Schedule Status */ |
#define | EHC_USBSTS_UsbAsyncInt 0x00040000UL /* USB Asynchronous Interrupt - EHCI derivation */ |
#define | EHC_USBSTS_UsbPeriodInt 0x00080000UL /* USB Period Interrupt - EHCI derivation */ |
#define | EHC_USBINTR_UsbIntEnable 0x00000001UL /* USB Interrupt Enable */ |
#define | EHC_USBINTR_UsbErroIntEnable 0x00000002UL /* USB Error Interrupt Enable */ |
#define | EHC_USBINTR_PortChangeIntEnable 0x00000004UL /* Port Change Interrupt Enable */ |
#define | EHC_USBINTR_FrameListRolloverEnable 0x00000008UL /* Frame List Rollover Enable */ |
#define | EHC_USBINTR_HostSystemErrorEnable 0x00000010UL /* Host System Error Enable */ |
#define | EHC_USBINTR_IntAsyncAdvanceEnable 0x00000020UL /* Interrupt on Async Advance Enable */ |
#define | EHC_USBINTR_SofRecieveEnable 0x00000080UL /* SOF - EHCI derivation */ |
#define | EHC_USBINTR_UsbAsyncEnable 0x00040000UL /* USB Asynchronous Interrupt - EHCI derivation */ |
#define | EHC_USBINTR_UsbPeriodEnable 0x00080000UL /* USB Period Interrupt - EHCI derivation */ |
#define | EHC_USBINTR_ALL 0x000C00BFUL /* All Interrupt */ |
#define | EHC_FRINDEX_MASK 0x000003FFUL /* Frame Index */ |
#define | EHC_UFRAME_MASK 0x00000007UL /* u-Frame Index */ |
#define | EHC_MFRAME_MASK 0x00001FF8UL /* m-Frame Index */ |
#define | EHC_PORTSC_CurrentConnectStatus 0x00000001UL /* Current Connect Status */ |
#define | EHC_PORTSC_ConnectStatusChange 0x00000002UL /* Connect Status Change */ |
#define | EHC_PORTSC_PortEnable 0x00000004UL /* Port Enabled Status */ |
#define | EHC_PORTSC_PortEnableChange 0x00000008UL /* Port Enabled/Disabled Change */ |
#define | EHC_PORTSC_OvercurrentActive 0x00000010UL /* Over-current Status */ |
#define | EHC_PORTSC_OvercurrentChange 0x00000020UL /* Over-current Change */ |
#define | EHC_PORTSC_ForcePortResume 0x00000040UL /* Force Port Resume */ |
#define | EHC_PORTSC_PortSuspend 0x00000080UL /* Port Suspend */ |
#define | EHC_PORTSC_PortReset 0x00000100UL /* Port Reset */ |
#define | EHC_PORTSC_LineStatus 0x00000C00UL /* Line Status */ |
#define | EHC_PORTSC_PortPowerControl 0x00001000UL /* Port Power Status */ |
#define | EHC_PORTSC_PortOwner 0x00002000UL /* Port Owner Status */ |
#define | EHC_PORTSC_PortIndicatorControl 0x0000C000UL /* Port Indicator Control */ |
#define | EHC_PORTSC_PortTestControl 0x000F0000UL /* Port Test Control */ |
#define | EHC_PORTSC_WakeonConnectEnable 0x00100000UL /* Wake on Connect Enable */ |
#define | EHC_PORTSC_WakeonDisconnectEnable 0x00200000UL /* Wake on Disconnect Enable */ |
#define | EHC_PORTSC_WakeonOvercurrentEnable 0x00400000UL /* Wake on Over-Current Enable */ |
#define | EHC_PORTSC_PhyClockDisable 0x00800000UL /* PHY Clock Disable - EHCI derivation */ |
#define | EHC_PORTSC_PortForceFullspeedConnect 0x01000000UL /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */ |
#define | EHC_PORTSC_PortSpeed 0x0C000000UL /* Device Speed - EHCI derivation */ |
#define | QTD_MAX_XFER_LENGTH 0x5000 |
#define | FRAMELIST_ALIGNMENT 4096 /* Frame List Alignment */ |
#define | SPLIT_MAX_LEN_UFRAME 188 |
#define | EHCI_FRAME_LIST(HostID) ((HostID) ? PeriodFrameList1 : PeriodFrameList0 ) |
Enumerations | |
enum | TD_TYPE { ITD_TYPE = 0, QHD_TYPE, SITD_TYPE, FSTN_TYPE } |
Functions | |
struct st_EHCD_QHD | ATTR_ALIGNED (32) HCD_QHD |
void | USB_Host_Enumerate (uint8_t HostID) |
void | USB_Host_DeEnumerate (uint8_t HostID) |
static INLINE HCD_STATUS | EHciHostInit (uint8_t HostID) |
static INLINE HCD_STATUS | EHciHostRun (uint8_t HostID) |
static INLINE HCD_STATUS | EHciHostStop (uint8_t HostID) |
static INLINE HCD_STATUS | EHciHostReset (uint8_t HostID) |
static void | DisableAsyncSchedule (uint8_t HostID) |
static void | EnableAsyncSchedule (uint8_t HostID) |
static void | DisablePeriodSchedule (uint8_t HostID) __attribute__((unused)) |
static void | EnablePeriodSchedule (uint8_t HostID) __attribute__((unused)) |
static INLINE void | DisableSchedule (uint8_t HostID, uint8_t isPeriod) |
static INLINE void | EnableSchedule (uint8_t HostID, uint8_t isPeriod) |
static INLINE PHCD_QHD | HcdAsyncHead (uint8_t HostID) |
static INLINE PHCD_QHD | HcdIntHead (uint8_t HostID) |
static INLINE PHCD_QHD | HcdQHD (uint8_t HostID, uint8_t idx) |
static INLINE PHCD_QTD | HcdQTD (uint8_t HostID, uint8_t idx) |
static INLINE PHCD_HS_ITD | HcdHsITD (uint8_t HostID, uint8_t idx) |
static INLINE PHCD_SITD | HcdSITD (uint8_t HostID, uint8_t idx) |
static INLINE bool | isValidLink (uint32_t link) |
static INLINE bool | IsInterruptQhd (uint8_t HostID, uint8_t QhdIdx) |
static void | FreeQhd (uint8_t HostID, uint8_t QhdIdx) |
static HCD_STATUS | AllocQhd (uint8_t HostID, uint8_t DeviceAddr, HCD_USB_SPEED DeviceSpeed, uint8_t EndpointNumber, HCD_TRANSFER_TYPE TransferType, HCD_TRANSFER_DIR TransferDir, uint16_t MaxPacketSize, uint8_t Interval, uint8_t Mult, uint8_t HSHubDevAddr, uint8_t HSHubPortNum, uint32_t *pQhdIdx) |
static HCD_STATUS | InsertLinkPointer (NextLinkPointer *pList, NextLinkPointer *pNew, uint8_t type) |
static HCD_STATUS | RemoveQueueHead (uint8_t HostID, uint8_t QhdIdx) |
static void | FreeQtd (PHCD_QTD pQtd) |
static HCD_STATUS | AllocQTD (uint8_t HostID, uint32_t *pTdIdx, uint8_t *const BufferPointer, uint32_t xferLen, HCD_TRANSFER_DIR PIDCode, uint8_t DataToggle, uint8_t IOC) |
static void | FreeHsItd (PHCD_HS_ITD pItd) |
static HCD_STATUS | AllocHsItd (uint8_t HostID, uint32_t *pTdIdx, uint8_t IhdIdx, uint8_t *dataBuff, uint32_t TDLen, uint8_t XactPerITD, uint8_t IntOnComplete) |
static HCD_STATUS | QueueITDs (uint8_t HostID, uint8_t IhdIdx, uint8_t *dataBuff, uint32_t xferLen) |
static void | FreeSItd (PHCD_SITD pSItd) |
static HCD_STATUS | AllocSItd (uint8_t HostID, uint32_t *TdIdx, uint8_t HeadIdx, uint8_t *dataBuff, uint32_t TDLen, uint8_t IntOnComplete) |
static HCD_STATUS | QueueSITDs (uint8_t HostID, uint8_t HeadIdx, uint8_t *dataBuff, uint32_t xferLen) |
static HCD_STATUS | WaitForTransferComplete (uint8_t HostID, uint8_t EpIdx) |
static HCD_STATUS | PipehandleParse (uint32_t Pipehandle, uint8_t *pHostID, HCD_TRANSFER_TYPE *XferType, uint8_t *pIdx) |
static void | PipehandleCreate (uint32_t *pPipeHandle, uint8_t HostID, HCD_TRANSFER_TYPE XferType, uint8_t idx) |
static void | AsyncScheduleIsr (uint8_t HostID) |
static void | PeriodScheduleIsr (uint8_t HostID) |
static HCD_STATUS | PortStatusChangeIsr (uint8_t HostID, uint32_t deviceConnect) |
static void | AsyncAdvanceIsr (uint8_t HostID) |
static void | UsbErrorIsr (uint8_t HostID) |
NextLinkPointer Horizontal |
struct { ... } Transaction[8] |