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ssp_001.h
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1 /*
2  * @brief SSP Registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SSP_001_H_
33 #define __SSP_001_H_
34 
35 #include "sys_config.h"
36 #include "cmsis.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
50 typedef struct {
51  __IO uint32_t CR0;
52  __IO uint32_t CR1;
53  __IO uint32_t DR;
54  __I uint32_t SR;
55  __IO uint32_t CPSR;
56  __IO uint32_t IMSC;
57  __I uint32_t RIS;
58  __I uint32_t MIS;
59  __O uint32_t ICR;
60 #if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX) /* no DMA on LPC11xx or LPC11Uxx */
61  __IO uint32_t DMACR;
62 #endif
64 
70 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
71 
72 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
73 
74 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
75 
76 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
77 
79 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
80 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
81 
83 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
84 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
85 
87 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
88 
89 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
90 
91 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
92 
94 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
95 
101 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
102 
103 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
104 
105 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
106 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
107 
109 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
110 
111 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
112 
114 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
115 
120 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
121 
127 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
128 
130 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
131 
135 typedef enum {
136  SSP_STAT_TFE = ((uint32_t)(1 << 0)),
137  SSP_STAT_TNF = ((uint32_t)(1 << 1)),
138  SSP_STAT_RNE = ((uint32_t)(1 << 2)),
139  SSP_STAT_RFF = ((uint32_t)(1 << 3)),
140  SSP_STAT_BSY = ((uint32_t)(1 << 4)),
142 
146 typedef enum {
147  SSP_RORIM = ((uint32_t)(1 << 0)),
148  SSP_RTIM = ((uint32_t)(1 << 1)),
149  SSP_RXIM = ((uint32_t)(1 << 2)),
150  SSP_TXIM = ((uint32_t)(1 << 3)),
153 
157 typedef enum {
158  SSP_RORMIS = ((uint32_t)(1 << 0)),
159  SSP_RTMIS = ((uint32_t)(1 << 1)),
160  SSP_RXMIS = ((uint32_t)(1 << 2)),
161  SSP_TXMIS = ((uint32_t)(1 << 3)),
164 
168 typedef enum {
169  SSP_RORRIS = ((uint32_t)(1 << 0)),
170  SSP_RTRIS = ((uint32_t)(1 << 1)),
171  SSP_RXRIS = ((uint32_t)(1 << 2)),
172  SSP_TXRIS = ((uint32_t)(1 << 3)),
175 
176 typedef enum {
177  SSP_RORIC = 0x0,
178  SSP_RTIC = 0x1,
181 
182 typedef enum SSP_DMA_Type {
183  SSP_DMA_RX = (1u),
184  SSP_DMA_TX = (1u << 1),
185 } SSP_DMA_Type;
186 
193 void IP_SSP_DeInit(IP_SSP_001_Type *pSSP);
194 
201 void IP_SSP_Cmd(IP_SSP_001_Type *pSSP, FunctionalState NewState);
202 
212 
225 
233 
246 
253 uint8_t IP_SSP_GetDataSize(IP_SSP_001_Type *pSSP);
254 
265 
278 
284 uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_Type *pSSP);
285 
292 void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data);
293 
302 void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale);
303 
320 void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat);
321 
331 
341 void IP_SSP_DMA_Cmd(IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState);
342 
347 #ifdef __cplusplus
348 }
349 #endif
350 
351 #endif /* __SSP_001_H_ */