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Endpoint_LPC18xx.h
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1 /*
2  * @brief USB Endpoint definitions for the LPC18xx microcontrollers
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
65 #ifndef __ENDPOINT_LPC18XX_H__
66 #define __ENDPOINT_LPC18XX_H__
67 
68  #include "../EndpointCommon.h"
69 
70 /* Enable C linkage for C++ Compilers: */
71  #if defined(__cplusplus)
72 extern "C" {
73  #endif
74 
75 /* Preprocessor Checks: */
76  #if !defined(__INCLUDE_FROM_USB_DRIVER)
77  #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.
78  #endif
79 
80 /* Private Interface - For use in library only: */
81  #if !defined(__DOXYGEN__)
82 /* Macros: */
83  #define ENDPOINT_DETAILS_MAXEP 6
84 
85  #if defined(USB_DEVICE_ROM_DRIVER)
86 /*==========================================================================*/
87 /* USB ROM DRIVER DEFINITIONS */
88 
89 /* A table of pointers to the chip's main ROM functions contained in ROM is located at the
90  address contained at this location */
91 typedef struct _ROM {
92  const unsigned p_otp;
93  const unsigned p_aes;
94  const unsigned p_pwd;
95  const unsigned p_clk;
96  const unsigned p_ipc;
97  const unsigned p_spifi;
98  const unsigned p_usbd;
99 } ROM_FUNCTION_TABLE;
100 
101 /* A table of pointers to the USBD functions contained in ROM is located at the
102  address contained at this location */
103  #define ROM_FUNCTION_TABLE_PTR_ADDR (0x10400104UL)
104  #define ROM_USBD_PTR (((ROM_FUNCTION_TABLE *) (ROM_FUNCTION_TABLE_PTR_ADDR))->p_usbd)
105 
106  #define ROMDRIVER_USB0_BASE LPC_USB0_BASE
107  #define ROMDRIVER_USB1_BASE LPC_USB1_BASE
108  #define ROMDRIVER_MEM_SIZE 0x1000
109 extern uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE];
110 
111  #define ROMDRIVER_MSC_MEM_SIZE 0x1000
112 extern uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE];
113 
114  #define ROMDRIVER_CDC_MEM_SIZE 0x800
115 extern uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE];
116  #define ROMDRIVER_CDC_DATA_BUFFER_SIZE 640
117  #if (USB_FORCED_FULLSPEED)
118  #define CDC_MAX_BULK_EP_SIZE 64
119  #else
120  #define CDC_MAX_BULK_EP_SIZE 512
121  #endif
122 extern uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE];
123 extern uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE];
124 
125  #define ROMDRIVER_HID_MEM_SIZE 0x800
126 extern uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE];
127 /*==========================================================================*/
128  #endif
129 
130 /*==========================================================================*/
131 /* DEVICE REGISTER DEFINITIONS */
132 /*==========================================================================*/
133 /*---------- USBCMD ----------*/
134  #define USBCMD_D_RunStop (1 << 0) /* Run or Stop */
135  #define USBCMD_D_Reset (1 << 1) /* Host Controller Reset */
136  #define USBCMD_D_SetupTripWire (1 << 13)
137  #define USBCMD_D_AddTDTripWire (1 << 14)
138  #define USBCMD_D_IntThreshold (0xff << 16)
139 
140 /*---------- USBSTS ----------*/
141  #define USBSTS_D_UsbInt 0x00000001UL /* USB Interrupt */
142  #define USBSTS_D_UsbErrorInt 0x00000002UL /* USB Error Interrupt */
143  #define USBSTS_D_PortChangeDetect 0x00000004UL /* Port Change Detect */
144  #define USBSTS_D_ResetReceived (1 << 6)
145  #define USBSTS_D_SofReceived (1 << 7)
146  #define USBSTS_D_SuspendInt (1 << 8)
147  #define USBSTS_D_NAK (1 << 16)
148 
149 /*---------- USBINTR ----------*/
150  #define USBINTR_D_UsbIntEnable (1 << 0)
151  #define USBINTR_D_UsbErrorIntEnable (1 << 1)
152  #define USBINTR_D_PortChangeIntEnable (1 << 2)
153  #define USBINTR_D_UsbResetEnable (1 << 6)
154  #define USBINTR_D_SofReceivedEnable (1 << 7)
155  #define USBINTR_D_SuspendEnable (1 << 8)
156  #define USBINTR_D_NAKEnable (1 << 16)
157 
158 /*---------- DEVICEADDR ----------*/
159  #define DEVICEADDR_AddressAdvance (1 << 24)
160  #define DEVICEADDR_DeviceAddr (0xff << 25)
161 
162 /*---------- ENDPTNAK ----------*/
163  #define ENDPTNAK_RX (0x3f)
164  #define ENDPTNAK_TX (0x3f << 16)
165 
166 /*---------- ENDPTNAKEN ----------*/
167  #define ENDPTNAKEN_RX (0x3f)
168  #define ENDPTNAKEN_TX (0x3f << 16)
169 
170 /*---------- PORTSC ----------*/
171  #define PORTSC_D_CurrentConnectStatus 0x00000001UL /* Current Connect Status */
172  #define PORTSC_D_ForcePortResume 0x00000040UL /* Force Port Resume */
173  #define PORTSC_D_PortSuspend 0x00000080UL /* Port Suspend */
174  #define PORTSC_D_PortReset 0x00000100UL /* Port Reset */
175  #define PORTSC_D_HighSpeedStatus 0x00000200UL /* Line Status */
176  #define PORTSC_D_PortIndicatorControl 0x0000C000UL /* Port Indicator Control */
177  #define PORTSC_D_PortTestControl 0x000F0000UL /* Port Test Control */
178  #define PORTSC_D_PhyClockDisable 0x00800000UL /* PHY Clock Disable - EHCI derivation */
179  #define PORTSC_D_PortForceFullspeedConnect 0x01000000UL /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */
180  #define PORTSC_D_PortSpeed 0x0C000000UL /* Device Speed - EHCI derivation */
181 
182 /*---------- USBMODE_D ----------*/
183 /*---------- ENDPSETUPSTAT ----------*/
184 
185 /*---------- ENDPTPRIME ----------*/
186  #define ENDPTPRIME_RX (0x3f)
187  #define ENDPTPRIME_TX (0x3f << 16)
188 
189 /*---------- ENDPTFLUSH ----------*/
190  #define ENDPTFLUSH_RX (0x3f)
191  #define ENDPTFLUSH_TX (0x3f << 16)
192 
193 /*---------- ENDPTSTAT ----------*/
194  #define ENDPTSTAT_RX (0x3f)
195  #define ENDPTSTAT_TX (0x3f << 16)
196 
197 /*---------- ENDPTCOMPLETE ----------*/
198  #define ENDPTCOMPLETE_RX (0x3f)
199  #define ENDPTCOMPLETE_TX (0x3f << 16)
200 
201 /*---------- ENDPTCTRL ----------*/
202  #define ENDPTCTRL_RxStall (1)
203  #define ENDPTCTRL_RxType (3 << 2)
204  #define ENDPTCTRL_RxToggleInhibit (1 << 5)
205  #define ENDPTCTRL_RxToggleReset (1 << 6)
206  #define ENDPTCTRL_RxEnable (1 << 7)
207 
208  #define ENDPTCTRL_TxStall (1 << 16)
209  #define ENDPTCTRL_TxType (3 << 18)
210  #define ENDPTCTRL_TxToggleInhibit (1 << 21)
211  #define ENDPTCTRL_TxToggleReset (1 << 22)
212  #define ENDPTCTRL_TxEnable (1 << 23)
213  #define ENDPTCTRL_REG(LogicalAddr) ( ((__IO uint32_t *) &(USB_REG(USBPortNum)->ENDPTCTRL[0]))[ \
214  LogicalAddr] )
215  #define EP_Physical2Logical(n) ((n) / 2)
216 /* Total physical endpoints*/
217  #define USED_PHYSICAL_ENDPOINTS (ENDPOINT_DETAILS_MAXEP * 2)/* This macro effect memory size of the DCD */
218  #define EP_Physical2BitPosition(n) ( EP_Physical2Logical(n) + ((n) % 2 ? 16 : 0 ) )
219 // #define LINK_TERMINATE 1
220 
221 /*---------- Device TD ----------*/
222 typedef struct {
223  /*---------- Word 1 ----------*/
225 
226  /*---------- Word 2 ----------*/
227  uint32_t : 3;
228  __IO uint32_t TransactionErr : 1;
229  uint32_t : 1;
230  __IO uint32_t BufferErr : 1;
231  __IO uint32_t Halted : 1;
232  __IO uint32_t Active : 1;
233  uint32_t : 2;
234  uint32_t MultiplierOverride : 2;
235  uint32_t : 3;
236  __IO uint32_t IntOnComplete : 1;
237  __IO uint32_t TotalBytes : 15;
238  uint32_t : 0; /* force next member alinged on the next word */
239 
240  /*---------- Word 3 - 7 ----------*/
241  uint32_t BufferPage[5];
242 
244 } DeviceTransferDescriptor, *PDeviceTransferDescriptor;
245 
246 /*---------- Device Qhd ----------*/
247 typedef struct {
248  /*---------- Word 1: Capability/Characteristics ----------*/
249  uint32_t : 15;
250  __IO uint32_t IntOnSetup : 1;
251  uint32_t MaxPacketSize : 11;
252  uint32_t : 2;
253  __IO uint32_t ZeroLengthTermination : 1;
254  uint32_t Mult : 2;
255  uint32_t : 0;
256 
257  /*---------- Word 2 ----------*/
258  uint32_t currentTD;
259 
260  /*---------- Word 3 - 10 ----------*/
261  __IO DeviceTransferDescriptor overlay;
262 
263  /*---------- Word 11-12 ----------*/
264  __IO uint8_t SetupPackage[8];
265 
266  uint16_t TransferCount;
267  __IO uint16_t IsOutReceived; // === TODO: IsOutReceived should be refractor to QueueHead Status ===
268  uint16_t reserved[6];
269 } DeviceQueueHead, *PDeviceQueueHead;
270 
271 extern volatile DeviceQueueHead dQueueHead[USED_PHYSICAL_ENDPOINTS];
272 extern DeviceTransferDescriptor dTransferDescriptor[USED_PHYSICAL_ENDPOINTS];
273 void DcdDataTransfer(uint8_t EPNum, uint8_t *pData, uint32_t cnt);
274 
275 void Endpoint_Streaming(uint8_t *buffer, uint16_t packetsize,
276  uint16_t totalpackets, uint16_t dummypackets);
277 
278 /* Inline Functions: */
279 
280 /* Function Prototypes: */
281 void Endpoint_ClearEndpoints(void);
282 
283 bool Endpoint_ConfigureEndpoint_Prv(const uint8_t Number,
284  const uint8_t UECFG0XData,
285  const uint8_t UECFG1XData);
286 
287  #endif
288 
289 /* Inline Functions: */
309 /*static inline */ bool Endpoint_ConfigureEndpoint(const uint8_t Number,
310  const uint8_t Type,
311  const uint8_t Direction,
312  const uint16_t Size,
313  const uint8_t Banks) /*ATTR_ALWAYS_INLINE*/;
314 
315 // static inline bool Endpoint_ConfigureEndpoint(const uint8_t Number,
316 // const uint8_t Type,
317 // const uint8_t Direction,
318 // const uint16_t Size,
319 // const uint8_t Banks)
320 // {
321 // endpointhandle[Number] = HAL17XX_ConfigureEndpoint(Number,Type,Direction,Size,Banks);
322 // return true;
323 // }
324 
332 static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;
333 
334 static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber)
335 {}
336 
342 static inline void Endpoint_EnableEndpoint(void) ATTR_ALWAYS_INLINE;
343 
344 static inline void Endpoint_EnableEndpoint(void)
345 {}
346 
350 static inline void Endpoint_DisableEndpoint(void) ATTR_ALWAYS_INLINE;
351 
352 static inline void Endpoint_DisableEndpoint(void)
353 {}
354 
359 static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
360 
361 static inline bool Endpoint_IsEnabled(void)
362 {
363  return true;
364 }
365 
375 static inline uint8_t Endpoint_GetBusyBanks(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
376 
377 static inline uint8_t Endpoint_GetBusyBanks(void)
378 {
379  return 0;
380 }
381 
389 static inline void Endpoint_AbortPendingIN(void)
390 {}
391 
397 static inline bool Endpoint_IsConfigured(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
398 
399 static inline bool Endpoint_IsConfigured(void)
400 {
401  // return ((UESTA0X & (1 << CFGOK)) ? true : false);
402  return true;
403 }
404 
412 static inline uint8_t Endpoint_GetEndpointInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
413 
414 static inline uint8_t Endpoint_GetEndpointInterrupts(void)
415 {
416  return 0; // TODO not yet implemented
417 }
418 
427 
428 static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber)
429 {
430  return (Endpoint_GetEndpointInterrupts() & (1 << EndpointNumber)) ? true : false;
431 }
432 
443 static inline uint16_t Endpoint_BytesInEndpoint(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
444 
445 static inline uint16_t Endpoint_BytesInEndpoint(void)
446 {
447  // return usb_data_buffer_index; // TODO not implemented yet
448  // uint8_t PhyEP = (endpointselected==ENDPOINT_CONTROLEP ? 1: endpointhandle[endpointselected]);
450  return usb_data_buffer_size;
451  }
452  else {
454  }
455 }
456 
464 static inline bool Endpoint_IsINReady(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
465 
466 static inline bool Endpoint_IsINReady(void)
467 {
469  return (dQueueHead[PhyEP].overlay.NextTD & LINK_TERMINATE) &&
470  (dQueueHead[PhyEP].overlay.Active == 0);
471 }
472 
480 static inline bool Endpoint_IsOUTReceived(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
481 
482 static inline bool Endpoint_IsOUTReceived(void)
483 {
484  // return (dQueueHead[ endpointhandle[endpointselected] ].overlay.NextTD == LINK_TERMINATE &&
485  // dQueueHead[ endpointhandle[endpointselected] ].overlay.Active == 0 );
486  return dQueueHead[endpointhandle[endpointselected]].IsOutReceived ? true : false; // TODO refractor IsOutReceived
487 }
488 
496 static inline bool Endpoint_IsSETUPReceived(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
497 
498 static inline bool Endpoint_IsSETUPReceived(void)
499 {
500  return USB_REG(USBPortNum)->ENDPTSETUPSTAT ? true : false;
501 }
502 
510 static inline void Endpoint_ClearSETUP(void) ATTR_ALWAYS_INLINE;
511 
512 static inline void Endpoint_ClearSETUP(void)
513 {
514  USB_REG(USBPortNum)->ENDPTSETUPSTAT = USB_REG(USBPortNum)->ENDPTSETUPSTAT;
516  USB_REG(USBPortNum)->ENDPTNAKEN |= (1 << 0);
517 }
518 
524 static inline void Endpoint_ClearIN(void) ATTR_ALWAYS_INLINE;
525 
526 static inline void Endpoint_ClearIN(void)
527 {
532  }
533  else {
536  }
537 }
538 
544 static inline void Endpoint_ClearOUT(void) ATTR_ALWAYS_INLINE;
545 
546 static inline void Endpoint_ClearOUT(void)
547 {
550  dQueueHead[endpointhandle[endpointselected]].IsOutReceived = 0;
551  }
552  else {
554  dQueueHead[endpointhandle[endpointselected]].IsOutReceived = 0;
555  USB_REG(USBPortNum)->ENDPTNAKEN |= (1 << endpointselected);
556  }
557 
558 }
559 
571 static inline void Endpoint_StallTransaction(void) ATTR_ALWAYS_INLINE;
572 
573 static inline void Endpoint_StallTransaction(void)
574 {
575  ENDPTCTRL_REG(EP_Physical2Logical(endpointhandle[endpointselected]) ) |= ENDPTCTRL_RxStall | ENDPTCTRL_TxStall;
576 }
577 
582 static inline void Endpoint_ClearStall(void) ATTR_ALWAYS_INLINE;
583 
584 static inline void Endpoint_ClearStall(void)
585 {
586  // === TODO: Only clear stall correct endpoint ===
587  ENDPTCTRL_REG(EP_Physical2Logical(endpointhandle[endpointselected]) ) &= ~(ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);
588 }
589 
597 static inline bool Endpoint_IsStalled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;
598 
599 static inline bool Endpoint_IsStalled(void)
600 {
601  return ENDPTCTRL_REG(EP_Physical2Logical(endpointhandle[endpointselected]) ) &
602  (ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);
603 }
604 
606 static inline void Endpoint_ResetDataToggle(void) ATTR_ALWAYS_INLINE;
607 
608 static inline void Endpoint_ResetDataToggle(void)
609 {
610  ENDPTCTRL_REG(EP_Physical2Logical(endpointhandle[endpointselected]) ) |= ENDPTCTRL_RxToggleReset |
611  ENDPTCTRL_TxToggleReset;
612 }
613 
614 /* External Variables: */
630  #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))
631 extern uint8_t USB_Device_ControlEndpointSize;
632  #else
633  #define USB_Device_ControlEndpointSize FIXED_CONTROL_ENDPOINT_SIZE
634  #endif
635 
636 /* Function Prototypes: */
641 void Endpoint_ClearStatusStage(void);
642 
653 uint8_t Endpoint_WaitUntilReady(void);
654 
655 /* Disable C linkage for C++ Compilers: */
656  #if defined(__cplusplus)
657 }
658  #endif
659 
660 #endif
661