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enet_001.c
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1 /*
2  * @brief Ethernet control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #include "enet_001.h"
33 
34 /*****************************************************************************
35  * Private types/enumerations/variables
36  ****************************************************************************/
37 
38 /* Saved address for PHY and clock divider */
40 
41 /*****************************************************************************
42  * Public types/enumerations/variables
43  ****************************************************************************/
44 
45 /*****************************************************************************
46  * Private functions
47  ****************************************************************************/
48 
49 /*****************************************************************************
50  * Public functions
51  ****************************************************************************/
52 
53 /* Resets ethernet interface */
55 {
56  /* This should be called prior to IP_ENET_Init. The MAC controller may
57  not be ready for a call to init right away so a small delay should
58  occur after this call. */
59  LPC_ENET->DMA_BUS_MODE |= DMA_BM_SWR;
60 }
61 
62 /* Sets the address of the interface */
63 void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr)
64 {
65  /* Save MAC address */
66  LPC_ENET->MAC_ADDR0_LOW = ((uint32_t) macAddr[3] << 24) |
67  ((uint32_t) macAddr[2] << 16) | ((uint32_t) macAddr[1] << 8) |
68  ((uint32_t) macAddr[0]);
69  LPC_ENET->MAC_ADDR0_HIGH = ((uint32_t) macAddr[5] << 8) |
70  ((uint32_t) macAddr[4]);
71 }
72 
73 /* Initialize ethernet interface */
75 {
76  /* Enhanced descriptors, burst length = 1 */
77  LPC_ENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1);
78 
79  /* Initial MAC configuration for checksum offload, full duplex,
80  100Mbps, disable receive own in half duplex, inter-frame gap
81  of 64-bits */
82  LPC_ENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM |
84 
85  /* Setup default filter */
86  LPC_ENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA;
87 
88  /* Flush transmit FIFO */
89  LPC_ENET->DMA_OP_MODE = DMA_OM_FTF;
90 
91  /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at
92  64 bytes */
93  LPC_ENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0);
94 
95  /* Clear all MAC interrupts */
96  LPC_ENET->DMA_STAT = DMA_ST_ALL;
97 
98  /* Enable MAC interrupts */
99  LPC_ENET->DMA_INT_EN = 0;
100 }
101 
102 /* Sets up the PHY link clock divider and PHY address */
103 void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr)
104 {
105  /* Save clock divider and PHY address in MII address register */
106  phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div);
107 }
108 
109 /*De-initialize the ethernet interface */
111 {
112  /* Disable packet reception */
113  LPC_ENET->MAC_CONFIG = 0;
114 
115  /* Flush transmit FIFO */
116  LPC_ENET->DMA_OP_MODE = DMA_OM_FTF;
117 
118  /* Disable receive and transmit DMA processes */
119  LPC_ENET->DMA_OP_MODE = 0;
120 }
121 
122 /* Starts a PHY write via the MII */
123 void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data)
124 {
125  /* Write value at PHY address and register */
126  LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W;
127  LPC_ENET->MAC_MII_DATA = (uint32_t) data;
128  LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
129 }
130 
131 /*Starts a PHY read via the MII */
132 void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg)
133 {
134  /* Read value at PHY address and register */
135  LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg);
136  LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB;
137 }
138 
139 /* Returns MII link (PHY) busy status */
141 {
142  if (LPC_ENET->MAC_MII_ADDR & MAC_MIIA_GB) {
143  return true;
144  }
145 
146  return false;
147 }
148 
149 /* Enables or disables ethernet transmit */
150 void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable)
151 {
152  if (Enable) {
153  /* Descriptor list head pointers must be setup prior to enable */
154  LPC_ENET->MAC_CONFIG |= MAC_CFG_TE;
155  LPC_ENET->DMA_OP_MODE |= DMA_OM_ST;
156  }
157  else {
158  LPC_ENET->MAC_CONFIG &= ~MAC_CFG_TE;
159  }
160 }
161 
162 /* Enables or disables ethernet packet reception */
163 void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable)
164 {
165  if (Enable) {
166  /* Descriptor list head pointers must be setup prior to enable */
167  LPC_ENET->MAC_CONFIG |= MAC_CFG_RE;
168  LPC_ENET->DMA_OP_MODE |= DMA_OM_SR;
169  }
170  else {
171  LPC_ENET->MAC_CONFIG &= ~MAC_CFG_RE;
172  }
173 }
174 
175 /* Sets full or half duplex for the interface */
176 void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full)
177 {
178  if (full) {
179  LPC_ENET->MAC_CONFIG |= MAC_CFG_DM;
180  }
181  else {
182  LPC_ENET->MAC_CONFIG &= ~MAC_CFG_DM;
183  }
184 }
185 
186 /* Sets speed for the interface */
187 void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100)
188 {
189  if (speed100) {
190  LPC_ENET->MAC_CONFIG |= MAC_CFG_FES;
191  }
192  else {
193  LPC_ENET->MAC_CONFIG &= ~MAC_CFG_FES;
194  }
195 }
196 
197 /* Configures the initial ethernet descriptors */
200 {
201  /* Setup descriptor list base addresses */
202  LPC_ENET->DMA_TRANS_DES_ADDR = (uint32_t) pTXDescs;
203  LPC_ENET->DMA_REC_DES_ADDR = (uint32_t) pRXDescs;
204 }