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creg_18xx_43xx.h
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1 /*
2  * @brief LPC18XX/43XX CREG control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CREG_18XX_43XX_H_
33 #define __CREG_18XX_43XX_H_
34 
35 #include "chip.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
49 typedef struct {
51  __IO uint32_t CREG0;
52  __I uint32_t RESERVED1[62];
54 #if defined(CHIP_LPC18XX)
55  __I uint32_t RESERVED2[5];
56 #else
62 #endif
63  __IO uint32_t CREG5;
68  __IO uint32_t CREG6;
69 #if defined(CHIP_LPC18XX)
70  __I uint32_t RESERVED4[52];
71 #else
73  __I uint32_t RESERVED4[51];
74 #endif
76 #if defined(CHIP_LPC18XX)
77  __I uint32_t RESERVED5[191];
78 #else
79  __I uint32_t RESERVED5[127];
82  __I uint32_t RESERVED6[62];
83 #endif
85  __I uint32_t RESERVED7[63];
87 } LPC_CREG_T;
88 
94 {
95  return LPC_CREG->CHIPID != 0x3284E02B;
96 }
97 
107 {
108  uint32_t FAValue = Hz / 21510000;
109 
110  LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
111  LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
112 }
113 
122 {
123  if (Enable) {
124  LPC_CREG->CREG0 &= ~(1 << 5);
125  }
126  else {
127  LPC_CREG->CREG0 |= (1 << 5);
128  }
129 }
130 
138 {
139  LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
140 }
141 
142 #if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
143 
148 STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
149 {
150  LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
151 }
152 
157 STATIC INLINE void Chip_CREG_ClearM4Event(void)
158 {
159  LPC_CREG->M4TXEVENT = 0;
160 }
161 
166 STATIC INLINE void Chip_CREG_ClearM0Event(void)
167 {
168  LPC_CREG->M0TXEVENT = 0;
169 }
170 
171 #endif
172 
177 #ifdef __cplusplus
178 }
179 #endif
180 
181 #endif /* __CREG_18XX_43XX_H_ */