33 #include "lpc43xx_dualcore_config.h"
36 #if defined(OS_FREE_RTOS)
40 #elif defined(OS_UCOS_III)
53 #define SHMEMM0 LOCATE_AT(SHARED_MEM_M0)
54 #define SHMEMM4 LOCATE_AT(SHARED_MEM_M4)
78 #define IPC_IRQ_Priority IRQ_PRIO_IPC
94 #define IPC_IRQHandler MX_CORE_IRQHandler
95 #define ClearTXEvent Chip_CREG_ClearM0Event
96 #define IPC_IRQn M0CORE_IRQn
98 #elif defined(CORE_M0)
101 #define IPC_IRQHandler MX_CORE_IRQHandler
102 #define ClearTXEvent Chip_CREG_ClearM4Event
103 #define IPC_IRQn M0_M4CORE_IRQn
106 #error "For LPC43XX, CORE_M0 or CORE_M4 must be defined!"
112 static xSemaphoreHandle event_tx, event_rx;
114 #elif defined(OS_UCOS_III)
115 static OS_SEM event_tx, event_rx;
134 portBASE_TYPE wake1 = pdFALSE, wake2 = pdFALSE;
137 xSemaphoreGiveFromISR(event_rx, &wake1);
141 xSemaphoreGiveFromISR(event_tx, &wake2);
144 portEND_SWITCHING_ISR(wake1 || wake2);
150 vSemaphoreCreateBinary(event_tx);
151 vSemaphoreCreateBinary(event_rx);
153 if (!event_tx || !event_rx) {
154 DEBUGSTR(
"ERROR: Unable to create FreeRTOS IPC event semaphores.\r\n");
161 #define ipc_wait_event(evt, sem) while ((evt)) xSemaphoreTake(sem, 100)
163 #define ipc_wait_event_tout(evt, tout, sem) \
166 if ((evt) && xSemaphoreTake(sem, tout) != pdTRUE) \
167 {tout = 0; break; }} \
170 #elif defined(OS_UCOS_III)
178 OSSemCreate(&event_tx,
"TX Sema", 0, &ret);
179 if (ret != OS_ERR_NONE) {
182 OSSemCreate(&event_rx,
"RX Sema", 0, &ret);
183 if (ret != OS_ERR_NONE) {
192 OSSemPost(&event_rx, OS_OPT_POST_ALL, &ret);
196 OSSemPost(&event_tx, OS_OPT_POST_ALL, &ret);
201 #define ipc_wait_event(evt, sem) \
202 while ((evt)) {OS_ERR ret; \
203 OSSemPend(&(sem), (OS_TICK) 100, OS_OPT_PEND_BLOCKING, (CPU_TS *) 0, &ret); }
204 #define ipc_wait_event_tout(evt, tout, sem) \
208 OSSemPend(&(sem), (OS_TICK) tout, OS_OPT_PEND_BLOCKING, (CPU_TS *) 0, &ret); \
209 if ((evt) && ret == OS_ERR_TIMEOUT) {tout = 0; break; } \
224 #define ipc_wait_event(evt, sem) while ((evt))
226 #define ipc_wait_event_tout(evt, tout, sem) \
228 uint32_t cnt = Chip_RIT_GetCounter() + (tout * (SystemCoreClock / 1000)); \
229 if (cnt + 5000 < cnt) {cnt += 5000; } \
230 while ((evt) && Chip_RIT_GetCounter() < cnt) {} \
231 if (evt) {tout = 0; } \
265 if (!size || !count || !data) {
266 DEBUGSTR(
"ERROR:IPC Queue size invalid parameters\r\n");
271 if (count & (count - 1)) {
272 DEBUGSTR(
"ERROR:IPC Queue size not power of 2\r\n");
277 memset(qwr, 0,
sizeof(*qwr));
283 NVIC_EnableIRQ(IPC_IRQn);
379 #ifdef __IAR_SYSTEMS_ICC__
407 static const char *ipc_errstr[] = {
409 "Queue Pop OK/Valid",
412 "Queue Error/Not initialized",
413 "Queue operation timed out",
418 return ipc_errstr[errnum];