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LPCOpen Platform
LPCOpen Platform for NXP LPC Microcontrollers
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Data Structures | |
struct | IP_SDMMC_001_Type |
SD/MMC & SDIO register block structure. More... | |
struct | pSDMMC_DMA_Type |
SDIO chained DMA descriptor. More... | |
struct | sdif_device |
SDIO device type. More... | |
Macros | |
#define | MCI_DMADES0_OWN (1UL << 31) |
SDIO DMA descriptor control (des0) register defines. | |
#define | MCI_DMADES0_CES (1 << 30) |
#define | MCI_DMADES0_ER (1 << 5) |
#define | MCI_DMADES0_CH (1 << 4) |
#define | MCI_DMADES0_FS (1 << 3) |
#define | MCI_DMADES0_LD (1 << 2) |
#define | MCI_DMADES0_DIC (1 << 1) |
#define | MCI_DMADES1_BS1(x) (x) |
SDIO DMA descriptor size (des1) register defines. | |
#define | MCI_DMADES1_BS2(x) ((x) << 13) |
#define | MCI_DMADES1_MAXTR 4096 |
#define | MCI_CTRL_USE_INT_DMAC (1 << 25) |
SDIO control register defines. | |
#define | MCI_CTRL_CARDV_MASK (0x7 << 16) |
#define | MCI_CTRL_CEATA_INT_EN (1 << 11) |
#define | MCI_CTRL_SEND_AS_CCSD (1 << 10) |
#define | MCI_CTRL_SEND_CCSD (1 << 9) |
#define | MCI_CTRL_ABRT_READ_DATA (1 << 8) |
#define | MCI_CTRL_SEND_IRQ_RESP (1 << 7) |
#define | MCI_CTRL_READ_WAIT (1 << 6) |
#define | MCI_CTRL_INT_ENABLE (1 << 4) |
#define | MCI_CTRL_DMA_RESET (1 << 2) |
#define | MCI_CTRL_FIFO_RESET (1 << 1) |
#define | MCI_CTRL_RESET (1 << 0) |
#define | MCI_POWER_ENABLE 0x1 |
SDIO Power Enable register defines. | |
#define | MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) |
SDIO Clock divider register defines. | |
#define | MCI_CLKSRC_CLKDIV0 0 |
SDIO Clock source register defines. | |
#define | MCI_CLKSRC_CLKDIV1 1 |
#define | MCI_CLKSRC_CLKDIV2 2 |
#define | MCI_CLKSRC_CLKDIV3 3 |
#define | MCI_CLK_SOURCE(clksrc) (clksrc) |
#define | MCI_CLKEN_LOW_PWR (1 << 16) |
SDIO Clock Enable register defines. | |
#define | MCI_CLKEN_ENABLE (1 << 0) |
#define | MCI_TMOUT_DATA(clks) ((clks) << 8) |
SDIO time-out register defines. | |
#define | MCI_TMOUT_DATA_MSK 0xFFFFFF00 |
#define | MCI_TMOUT_RESP(clks) ((clks) & 0xFF) |
#define | MCI_TMOUT_RESP_MSK 0xFF |
#define | MCI_CTYPE_8BIT (1 << 16) |
SDIO card-type register defines. | |
#define | MCI_CTYPE_4BIT (1 << 0) |
#define | MCI_INT_SDIO (1 << 16) |
SDIO Interrupt status & mask register defines. | |
#define | MCI_INT_EBE (1 << 15) |
#define | MCI_INT_ACD (1 << 14) |
#define | MCI_INT_SBE (1 << 13) |
#define | MCI_INT_HLE (1 << 12) |
#define | MCI_INT_FRUN (1 << 11) |
#define | MCI_INT_HTO (1 << 10) |
#define | MCI_INT_DTO (1 << 9) |
#define | MCI_INT_RTO (1 << 8) |
#define | MCI_INT_DCRC (1 << 7) |
#define | MCI_INT_RCRC (1 << 6) |
#define | MCI_INT_RXDR (1 << 5) |
#define | MCI_INT_TXDR (1 << 4) |
#define | MCI_INT_DATA_OVER (1 << 3) |
#define | MCI_INT_CMD_DONE (1 << 2) |
#define | MCI_INT_RESP_ERR (1 << 1) |
#define | MCI_INT_CD (1 << 0) |
#define | MCI_CMD_START (1UL << 31) |
SDIO Command register defines. | |
#define | MCI_CMD_VOLT_SWITCH (1 << 28) |
#define | MCI_CMD_BOOT_MODE (1 << 27) |
#define | MCI_CMD_DISABLE_BOOT (1 << 26) |
#define | MCI_CMD_EXPECT_BOOT_ACK (1 << 25) |
#define | MCI_CMD_ENABLE_BOOT (1 << 24) |
#define | MCI_CMD_CCS_EXP (1 << 23) |
#define | MCI_CMD_CEATA_RD (1 << 22) |
#define | MCI_CMD_UPD_CLK (1 << 21) |
#define | MCI_CMD_INIT (1 << 15) |
#define | MCI_CMD_STOP (1 << 14) |
#define | MCI_CMD_PRV_DAT_WAIT (1 << 13) |
#define | MCI_CMD_SEND_STOP (1 << 12) |
#define | MCI_CMD_STRM_MODE (1 << 11) |
#define | MCI_CMD_DAT_WR (1 << 10) |
#define | MCI_CMD_DAT_EXP (1 << 9) |
#define | MCI_CMD_RESP_CRC (1 << 8) |
#define | MCI_CMD_RESP_LONG (1 << 7) |
#define | MCI_CMD_RESP_EXP (1 << 6) |
#define | MCI_CMD_INDX(n) ((n) & 0x1F) |
#define | MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF) |
SDIO status register definess. | |
#define | MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF) |
SDIO FIFO threshold defines. | |
#define | MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16) |
#define | MCI_FIFOTH_DMA_MTS_1 (0UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_4 (1UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_8 (2UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_16 (3UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_32 (4UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_64 (5UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_128 (6UL << 28) |
#define | MCI_FIFOTH_DMA_MTS_256 (7UL << 28) |
#define | MCI_BMOD_PBL1 (0 << 8) |
Bus mode register defines. | |
#define | MCI_BMOD_PBL4 (1 << 8) |
#define | MCI_BMOD_PBL8 (2 << 8) |
#define | MCI_BMOD_PBL16 (3 << 8) |
#define | MCI_BMOD_PBL32 (4 << 8) |
#define | MCI_BMOD_PBL64 (5 << 8) |
#define | MCI_BMOD_PBL128 (6 << 8) |
#define | MCI_BMOD_PBL256 (7 << 8) |
#define | MCI_BMOD_DE (1 << 7) |
#define | MCI_BMOD_DSL(len) ((len) << 2) |
#define | MCI_BMOD_FB (1 << 1) |
#define | MCI_BMOD_SWR (1 << 0) |
#define | SD_FIFO_SZ 32 |
Commonly used definitions. | |
Typedefs | |
typedef uint32_t(* | MCI_IRQ_CB_FUNC_T )(uint32_t) |
typedef int32_t(* | PSCHECK_FUNC_T )(void) |
typedef void(* | PS_POWER_FUNC_T )(int32_t enable) |
Functions | |
void | IP_SDMMC_Init (IP_SDMMC_001_Type *pSDMMC) |
Initializes the MCI card controller. | |
void | IP_SDMMC_DeInit (IP_SDMMC_001_Type *pSDMMC) |
Close the MCI. | |
void | IP_SDMMC_SetBlkSize (IP_SDMMC_001_Type *pSDMMC, uint32_t bytes) |
Set block size for transfer. | |
void | IP_SDMMC_Reset (IP_SDMMC_001_Type *pSDMMC, int32_t reset) |
Reset card in slot. | |
void | IP_SDMMC_PowerOnOff (IP_SDMMC_001_Type *pSDMMC, int32_t enable) |
Enable or disable slot power. | |
int32_t | IP_SDMMC_CardWpOn (IP_SDMMC_001_Type *pSDMMC) |
Detect if write protect is enabled. | |
int32_t | IP_SDMMC_CardNDetect (IP_SDMMC_001_Type *pSDMMC) |
Detect if an SD card is inserted. | |
int32_t | IP_SDMMC_SendCmd (IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg) |
Function to send command to Card interface unit (CIU) | |
void | IP_SDMMC_GetResponse (IP_SDMMC_001_Type *pSDMMC, uint32_t *resp) |
Read the response from the last command. | |
void | IP_SDMMC_SetClock (IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed) |
Sets the SD bus clock speed. | |
void | IP_SDMMC_SetCardType (IP_SDMMC_001_Type *pSDMMC, uint32_t ctype) |
Function to set card type. | |
void | IP_SDMMC_SetClearIntFifo (IP_SDMMC_001_Type *pSDMMC) |
Function to clear interrupt & FIFOs. | |
uint32_t | IP_SDMMC_GetRawIntStatus (IP_SDMMC_001_Type *pSDMMC) |
Returns the raw SD interface interrupt status. | |
void | IP_SDMMC_SetRawIntStatus (IP_SDMMC_001_Type *pSDMMC, uint32_t iVal) |
Sets the raw SD interface interrupt status. | |
void | IP_SDMMC_SetIntMask (IP_SDMMC_001_Type *pSDMMC, uint32_t iVal) |
Sets the SD interface interrupt mask. | |
void | IP_SDMMC_DmaSetup (IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size) |
Setup DMA descriptors. | |
void | IP_SDMMC_SetBlockSize (IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size) |
Sets the transfer block size. | |
#define MCI_BMOD_DE (1 << 7) |
Enable internal DMAC
Definition at line 226 of file sdmmc_001.h.
#define MCI_BMOD_DSL | ( | len | ) | ((len) << 2) |
Descriptor skip length
Definition at line 227 of file sdmmc_001.h.
#define MCI_BMOD_FB (1 << 1) |
Fixed bursts
Definition at line 228 of file sdmmc_001.h.
#define MCI_BMOD_PBL1 (0 << 8) |
#define MCI_BMOD_PBL128 (6 << 8) |
Burst length = 128
Definition at line 224 of file sdmmc_001.h.
#define MCI_BMOD_PBL16 (3 << 8) |
Burst length = 16
Definition at line 221 of file sdmmc_001.h.
#define MCI_BMOD_PBL256 (7 << 8) |
Burst length = 256
Definition at line 225 of file sdmmc_001.h.
#define MCI_BMOD_PBL32 (4 << 8) |
Burst length = 32
Definition at line 222 of file sdmmc_001.h.
#define MCI_BMOD_PBL4 (1 << 8) |
Burst length = 4
Definition at line 219 of file sdmmc_001.h.
#define MCI_BMOD_PBL64 (5 << 8) |
Burst length = 64
Definition at line 223 of file sdmmc_001.h.
#define MCI_BMOD_PBL8 (2 << 8) |
Burst length = 8
Definition at line 220 of file sdmmc_001.h.
#define MCI_BMOD_SWR (1 << 0) |
Software reset of internal registers
Definition at line 229 of file sdmmc_001.h.
#define MCI_CLK_SOURCE | ( | clksrc | ) | (clksrc) |
Set cklock divider source
Definition at line 137 of file sdmmc_001.h.
#define MCI_CLKEN_ENABLE (1 << 0) |
Enable slot clock
Definition at line 142 of file sdmmc_001.h.
#define MCI_CLKEN_LOW_PWR (1 << 16) |
SDIO Clock Enable register defines.
Enable clock idle for slot
Definition at line 141 of file sdmmc_001.h.
#define MCI_CLKSRC_CLKDIV0 0 |
SDIO Clock source register defines.
Definition at line 133 of file sdmmc_001.h.
#define MCI_CLKSRC_CLKDIV1 1 |
Definition at line 134 of file sdmmc_001.h.
#define MCI_CLKSRC_CLKDIV2 2 |
Definition at line 135 of file sdmmc_001.h.
#define MCI_CLKSRC_CLKDIV3 3 |
Definition at line 136 of file sdmmc_001.h.
#define MCI_CLOCK_DIVIDER | ( | dn, | |
d2 | |||
) | ((d2) << ((dn) * 8)) |
#define MCI_CMD_BOOT_MODE (1 << 27) |
Boot mode
Definition at line 180 of file sdmmc_001.h.
#define MCI_CMD_CCS_EXP (1 << 23) |
CCS expected
Definition at line 184 of file sdmmc_001.h.
#define MCI_CMD_CEATA_RD (1 << 22) |
CE-ATA read in progress
Definition at line 185 of file sdmmc_001.h.
#define MCI_CMD_DAT_EXP (1 << 9) |
Data expected
Definition at line 193 of file sdmmc_001.h.
#define MCI_CMD_DAT_WR (1 << 10) |
Read(0)/Write(1) selection
Definition at line 192 of file sdmmc_001.h.
#define MCI_CMD_DISABLE_BOOT (1 << 26) |
Disable boot
Definition at line 181 of file sdmmc_001.h.
#define MCI_CMD_ENABLE_BOOT (1 << 24) |
Enable boot
Definition at line 183 of file sdmmc_001.h.
#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) |
Expect boot ack
Definition at line 182 of file sdmmc_001.h.
#define MCI_CMD_INDX | ( | n | ) | ((n) & 0x1F) |
Definition at line 197 of file sdmmc_001.h.
#define MCI_CMD_INIT (1 << 15) |
Send init sequence
Definition at line 187 of file sdmmc_001.h.
#define MCI_CMD_PRV_DAT_WAIT (1 << 13) |
Wait before send
Definition at line 189 of file sdmmc_001.h.
#define MCI_CMD_RESP_CRC (1 << 8) |
Check response CRC
Definition at line 194 of file sdmmc_001.h.
#define MCI_CMD_RESP_EXP (1 << 6) |
Response expected
Definition at line 196 of file sdmmc_001.h.
#define MCI_CMD_RESP_LONG (1 << 7) |
Response length
Definition at line 195 of file sdmmc_001.h.
#define MCI_CMD_SEND_STOP (1 << 12) |
Send auto-stop
Definition at line 190 of file sdmmc_001.h.
#define MCI_CMD_START (1UL << 31) |
#define MCI_CMD_STOP (1 << 14) |
Stop/abort command
Definition at line 188 of file sdmmc_001.h.
#define MCI_CMD_STRM_MODE (1 << 11) |
Stream transfer mode
Definition at line 191 of file sdmmc_001.h.
#define MCI_CMD_UPD_CLK (1 << 21) |
Update clock register only
Definition at line 186 of file sdmmc_001.h.
#define MCI_CMD_VOLT_SWITCH (1 << 28) |
Voltage switch bit
Definition at line 179 of file sdmmc_001.h.
#define MCI_CTRL_ABRT_READ_DATA (1 << 8) |
Abort read data
Definition at line 115 of file sdmmc_001.h.
#define MCI_CTRL_CARDV_MASK (0x7 << 16) |
SD_VOLT[2:0} pins output state mask
Definition at line 111 of file sdmmc_001.h.
#define MCI_CTRL_CEATA_INT_EN (1 << 11) |
Enable CE-ATA interrupts
Definition at line 112 of file sdmmc_001.h.
#define MCI_CTRL_DMA_RESET (1 << 2) |
Reset internal DMA
Definition at line 119 of file sdmmc_001.h.
#define MCI_CTRL_FIFO_RESET (1 << 1) |
Reset data FIFO pointers
Definition at line 120 of file sdmmc_001.h.
#define MCI_CTRL_INT_ENABLE (1 << 4) |
Global interrupt enable
Definition at line 118 of file sdmmc_001.h.
#define MCI_CTRL_READ_WAIT (1 << 6) |
Assert read-wait for SDIO
Definition at line 117 of file sdmmc_001.h.
#define MCI_CTRL_RESET (1 << 0) |
Reset controller
Definition at line 121 of file sdmmc_001.h.
#define MCI_CTRL_SEND_AS_CCSD (1 << 10) |
Send auto-stop
Definition at line 113 of file sdmmc_001.h.
#define MCI_CTRL_SEND_CCSD (1 << 9) |
Send CCSD
Definition at line 114 of file sdmmc_001.h.
#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) |
Send auto-IRQ response
Definition at line 116 of file sdmmc_001.h.
#define MCI_CTRL_USE_INT_DMAC (1 << 25) |
#define MCI_CTYPE_4BIT (1 << 0) |
Enable 8-bit mode
Definition at line 154 of file sdmmc_001.h.
#define MCI_CTYPE_8BIT (1 << 16) |
#define MCI_DMADES0_CES (1 << 30) |
Card Error Summary bit
Definition at line 95 of file sdmmc_001.h.
#define MCI_DMADES0_CH (1 << 4) |
Second address chained bit
Definition at line 97 of file sdmmc_001.h.
#define MCI_DMADES0_DIC (1 << 1) |
Disable interrupt on completion bit
Definition at line 100 of file sdmmc_001.h.
#define MCI_DMADES0_ER (1 << 5) |
End of descriptopr ring bit
Definition at line 96 of file sdmmc_001.h.
#define MCI_DMADES0_FS (1 << 3) |
First descriptor bit
Definition at line 98 of file sdmmc_001.h.
#define MCI_DMADES0_LD (1 << 2) |
Last descriptor bit
Definition at line 99 of file sdmmc_001.h.
#define MCI_DMADES0_OWN (1UL << 31) |
SDIO DMA descriptor control (des0) register defines.
DMA owns descriptor bit
Definition at line 94 of file sdmmc_001.h.
#define MCI_DMADES1_BS1 | ( | x | ) | (x) |
SDIO DMA descriptor size (des1) register defines.
Size of buffer 1
Definition at line 104 of file sdmmc_001.h.
#define MCI_DMADES1_BS2 | ( | x | ) | ((x) << 13) |
Size of buffer 2
Definition at line 105 of file sdmmc_001.h.
#define MCI_DMADES1_MAXTR 4096 |
Max transfer size per buffer
Definition at line 106 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28) |
Definition at line 207 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28) |
Definition at line 213 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28) |
Definition at line 210 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28) |
Definition at line 214 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28) |
Definition at line 211 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28) |
Definition at line 208 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28) |
Definition at line 212 of file sdmmc_001.h.
#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28) |
Definition at line 209 of file sdmmc_001.h.
#define MCI_FIFOTH_RX_WM | ( | x | ) | (((x) & 0xFFF) << 16) |
Definition at line 206 of file sdmmc_001.h.
#define MCI_FIFOTH_TX_WM | ( | x | ) | ((x) & 0xFFF) |
SDIO FIFO threshold defines.
Definition at line 205 of file sdmmc_001.h.
#define MCI_INT_ACD (1 << 14) |
Auto command done
Definition at line 160 of file sdmmc_001.h.
#define MCI_INT_CD (1 << 0) |
Card detect
Definition at line 174 of file sdmmc_001.h.
#define MCI_INT_CMD_DONE (1 << 2) |
Command done
Definition at line 172 of file sdmmc_001.h.
#define MCI_INT_DATA_OVER (1 << 3) |
Data transfer over
Definition at line 171 of file sdmmc_001.h.
#define MCI_INT_DCRC (1 << 7) |
Data CRC error
Definition at line 167 of file sdmmc_001.h.
#define MCI_INT_DTO (1 << 9) |
Data timeout error
Definition at line 165 of file sdmmc_001.h.
#define MCI_INT_EBE (1 << 15) |
End-bit error
Definition at line 159 of file sdmmc_001.h.
#define MCI_INT_FRUN (1 << 11) |
FIFO overrun/underrun error
Definition at line 163 of file sdmmc_001.h.
#define MCI_INT_HLE (1 << 12) |
Hardware locked error
Definition at line 162 of file sdmmc_001.h.
#define MCI_INT_HTO (1 << 10) |
Host data starvation error
Definition at line 164 of file sdmmc_001.h.
#define MCI_INT_RCRC (1 << 6) |
Response CRC error
Definition at line 168 of file sdmmc_001.h.
#define MCI_INT_RESP_ERR (1 << 1) |
Command response error
Definition at line 173 of file sdmmc_001.h.
#define MCI_INT_RTO (1 << 8) |
Response timeout error
Definition at line 166 of file sdmmc_001.h.
#define MCI_INT_RXDR (1 << 5) |
RX data ready
Definition at line 169 of file sdmmc_001.h.
#define MCI_INT_SBE (1 << 13) |
Start bit error
Definition at line 161 of file sdmmc_001.h.
#define MCI_INT_SDIO (1 << 16) |
SDIO Interrupt status & mask register defines.
SDIO interrupt
Definition at line 158 of file sdmmc_001.h.
#define MCI_INT_TXDR (1 << 4) |
TX data needed
Definition at line 170 of file sdmmc_001.h.
#define MCI_POWER_ENABLE 0x1 |
SDIO Power Enable register defines.
Enable slot power signal (SD_POW)
Definition at line 125 of file sdmmc_001.h.
#define MCI_STS_GET_FCNT | ( | x | ) | (((x) >> 17) & 0x1FF) |
SDIO status register definess.
Definition at line 201 of file sdmmc_001.h.
#define MCI_TMOUT_DATA | ( | clks | ) | ((clks) << 8) |
#define MCI_TMOUT_DATA_MSK 0xFFFFFF00 |
Definition at line 147 of file sdmmc_001.h.
#define MCI_TMOUT_RESP | ( | clks | ) | ((clks) & 0xFF) |
Response timeout clocks
Definition at line 148 of file sdmmc_001.h.
#define MCI_TMOUT_RESP_MSK 0xFF |
Definition at line 149 of file sdmmc_001.h.
#define SD_FIFO_SZ 32 |
Commonly used definitions.
Size of SDIO FIFOs (32-bit wide)
Definition at line 233 of file sdmmc_001.h.
Function prototype for SD interface IRQ callback
Definition at line 236 of file sdmmc_001.h.
typedef void(* PS_POWER_FUNC_T)(int32_t enable) |
Function prototype for SD slot power enable or slot reset
Definition at line 242 of file sdmmc_001.h.
typedef int32_t(* PSCHECK_FUNC_T)(void) |
Function prototype for SD detect and write protect status check
Definition at line 239 of file sdmmc_001.h.
int32_t IP_SDMMC_CardNDetect | ( | IP_SDMMC_001_Type * | pSDMMC | ) |
Detect if an SD card is inserted.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
Definition at line 123 of file sdmmc_001.c.
int32_t IP_SDMMC_CardWpOn | ( | IP_SDMMC_001_Type * | pSDMMC | ) |
Detect if write protect is enabled.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
Definition at line 114 of file sdmmc_001.c.
void IP_SDMMC_DeInit | ( | IP_SDMMC_001_Type * | pSDMMC | ) |
Close the MCI.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
Definition at line 82 of file sdmmc_001.c.
void IP_SDMMC_DmaSetup | ( | IP_SDMMC_001_Type * | pSDMMC, |
sdif_device * | psdif_dev, | ||
uint32_t | addr, | ||
uint32_t | size | ||
) |
Setup DMA descriptors.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
psdif_dev | : SD interface device |
addr | : Address of buffer (source or destination) |
size | : size of buffer in bytes (64K max) |
Definition at line 240 of file sdmmc_001.c.
uint32_t IP_SDMMC_GetRawIntStatus | ( | IP_SDMMC_001_Type * | pSDMMC | ) |
Returns the raw SD interface interrupt status.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
Definition at line 222 of file sdmmc_001.c.
void IP_SDMMC_GetResponse | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t * | resp | ||
) |
Read the response from the last command.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
resp | : Pointer to response array to fill |
Definition at line 159 of file sdmmc_001.c.
void IP_SDMMC_Init | ( | IP_SDMMC_001_Type * | pSDMMC | ) |
Initializes the MCI card controller.
pSDMMC | Pointer to IP_SDMMC_001_Type structure |
Definition at line 51 of file sdmmc_001.c.
void IP_SDMMC_PowerOnOff | ( | IP_SDMMC_001_Type * | pSDMMC, |
int32_t | enable | ||
) |
Enable or disable slot power.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
enable | : !0 to enable, or 0 to disable |
Definition at line 103 of file sdmmc_001.c.
void IP_SDMMC_Reset | ( | IP_SDMMC_001_Type * | pSDMMC, |
int32_t | reset | ||
) |
Reset card in slot.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
reset | : Sets SD_RST to passed state |
Definition at line 92 of file sdmmc_001.c.
int32_t IP_SDMMC_SendCmd | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | cmd, | ||
uint32_t | arg | ||
) |
Function to send command to Card interface unit (CIU)
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
cmd | : Command with all flags set |
arg | : Argument for the command |
Definition at line 134 of file sdmmc_001.c.
void IP_SDMMC_SetBlkSize | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | bytes | ||
) |
Set block size for transfer.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
bytes | : block size in bytes |
Definition at line 86 of file sdmmc_001.c.
void IP_SDMMC_SetBlockSize | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | blk_size | ||
) |
Sets the transfer block size.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
blk_size | : Block Size value |
Definition at line 295 of file sdmmc_001.c.
void IP_SDMMC_SetCardType | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | ctype | ||
) |
Function to set card type.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
ctype | : card type |
Definition at line 203 of file sdmmc_001.c.
void IP_SDMMC_SetClearIntFifo | ( | IP_SDMMC_001_Type * | pSDMMC | ) |
Function to clear interrupt & FIFOs.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
Definition at line 209 of file sdmmc_001.c.
void IP_SDMMC_SetClock | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | clk_rate, | ||
uint32_t | speed | ||
) |
Sets the SD bus clock speed.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
clk_rate | : Input clock rate into the IP block |
speed | : Desired clock speed to the card |
Definition at line 169 of file sdmmc_001.c.
void IP_SDMMC_SetIntMask | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | iVal | ||
) |
Sets the SD interface interrupt mask.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
iVal | : Interrupts to enable, Or'ed values MCI_INT_* |
Definition at line 234 of file sdmmc_001.c.
void IP_SDMMC_SetRawIntStatus | ( | IP_SDMMC_001_Type * | pSDMMC, |
uint32_t | iVal | ||
) |
Sets the raw SD interface interrupt status.
pSDMMC | : Pointer to IP_SDMMC_001_Type structure |
iVal | : Raw interrupts to set, Or'ed values MCI_INT_* |
Definition at line 228 of file sdmmc_001.c.