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sysinit_hitex_eva_18504350.c
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1 /*
2  * Copyright(C) NXP Semiconductors, 2012
3  * All rights reserved.
4  *
5  * Software that is described herein is for illustrative purposes only
6  * which provides customers with programming information regarding the
7  * LPC products. This software is supplied "AS IS" without any warranties of
8  * any kind, and NXP Semiconductors and its licensor disclaim any and
9  * all warranties, express or implied, including all implied warranties of
10  * merchantability, fitness for a particular purpose and non-infringement of
11  * intellectual property rights. NXP Semiconductors assumes no responsibility
12  * or liability for the use of the software, conveys no license or rights under any
13  * patent, copyright, mask work right, or any other intellectual property rights in
14  * or to any products. NXP Semiconductors reserves the right to make changes
15  * in the software without notification. NXP Semiconductors also makes no
16  * representation or warranty that such application will be suitable for the
17  * specified use without further testing or modification.
18  *
19  * Permission to use, copy, modify, and distribute this software and its
20  * documentation is hereby granted, under NXP Semiconductors' and its
21  * licensor's relevant copyrights in the software, without fee, provided that it
22  * is used in conjunction with NXP Semiconductors microcontrollers. This
23  * copyright, permission, and disclaimer notice must appear in all copies of
24  * this code.
25  */
26 
27 #include "board.h"
28 
51 #ifndef CORE_M0
52 /* SCR pin definitions for pin muxing */
53 typedef struct {
54  uint8_t pingrp; /* Pin group */
55  uint8_t pinnum; /* Pin number */
56  uint8_t pincfg; /* Pin configuration for SCU */
57  uint8_t funcnum;/* Function number */
58 } PINMUX_GRP_T;
59 
60 /* Structure for initial base clock states */
62  CGU_BASE_CLK_T clk; /* Base clock */
63  CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
64  bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
65  bool powerdn; /* Set to true if the base clock is initially powered down */
66 };
67 
68 /* Initial base clock states are mostly on */
70  {CLK_BASE_SAFE, CLKIN_IRC, true, false},
71  {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
72  {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
73  {CLK_BASE_USB0, CLKIN_USBPLL, true, false},
74 #if defined(CHIP_LPC43XX)
75  {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
76 #endif
77  {CLK_BASE_USB1, CLKIN_USBPLL, true, false},
78 #if defined(CHIP_LPC43XX)
79  {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
80 #endif
81  {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
82 #if defined(USE_RMII)
83  {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
84 #else
85  {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
86 #endif
87  {CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
88 #if defined(CHIP_LPC43XX)
89  {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
90 #endif
91  {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
92  {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
93  {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
94  {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
95  {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
96  {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
97  {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
98  {CLK_BASE_OUT, CLKINPUT_PD, true, false},
99  {CLK_BASE_APLL, CLKINPUT_PD, true, false},
100  {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
101  {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
102 };
103 
104 /* SPIFI high speed pin mode setup */
106  {0x3, 3, (MD_PLN_FAST), FUNC3}, /* SPIFI CLK */
107  {0x3, 4, (MD_PLN_FAST), FUNC3}, /* SPIFI D3 */
108  {0x3, 5, (MD_PLN_FAST), FUNC3}, /* SPIFI D2 */
109  {0x3, 6, (MD_PLN_FAST), FUNC3}, /* SPIFI D1 */
110  {0x3, 7, (MD_PLN_FAST), FUNC3}, /* SPIFI D0 */
111  {0x3, 8, (MD_PLN_FAST), FUNC3} /* SPIFI CS/SSEL */
112 };
113 
114 /* Setup system clocking */
116 {
117  int i;
118 
119  /* Switch main system clocking to crystal */
122 
123  /* Setup PLL for 100MHz and switch main system clocking */
124  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
126 
127  /* Setup PLL for maximum clock */
129 
130  /* Setup system base clocks and initial states. This won't enable and
131  disable individual clocks, but sets up the base clock sources for
132  each individual peripheral clock. */
133  for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
134  Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
135  InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
136  }
137 
138  /* Reset and enable 32Khz oscillator */
139  LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
140  LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
141 
142  /* SPIFI pin setup is done prior to setting up system clocking */
143  for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
144  Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
145  spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
146  }
147 
148  /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
149  Divide rate is based on CPU speed and speed of SPI FLASH part. */
150 #if (MAX_CLOCK_FREQ > 180000000)
152 #else
154 #endif
156 }
157 
159 #if defined(USE_RMII)
160  /* RMII pin group */
161  {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0},
162  {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6},
163  {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
164  {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
165  {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
166  {0xC, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
167  {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7},
168  {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
169  {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2},
170 #else
171  /* MII pin group */
172  {0x1, 19, (MD_PLN | MD_EZI), FUNC0},
173  {0x0, 1, (MD_PLN), FUNC6},
174  {0x1, 18, (MD_PLN), FUNC3},
175  {0x1, 20, (MD_PLN), FUNC3},
176  {0x1, 17, (MD_PLN | MD_EZI), FUNC3},
177  {0xC, 1, (MD_PLN), FUNC3},
178  {0x1, 16, (MD_PLN | MD_EZI), FUNC7},
179  {0x1, 15, (MD_PLN | MD_EZI), FUNC3},
180  {0x0, 0, (MD_PLN | MD_EZI), FUNC2},
181  {0x9, 4, (MD_PLN), FUNC5},
182  {0x9, 5, (MD_PLN), FUNC5},
183  {0xC, 0, (MD_PLN | MD_EZI), FUNC3},
184  {0x9, 0, (MD_PLN | MD_EZI), FUNC5},
185  {0x9, 1, (MD_PLN | MD_EZI), FUNC5},
186  {0x9, 6, (MD_PLN | MD_EZI), FUNC5},
187  {0x9, 3, (MD_PLN | MD_EZI), FUNC5},
188  {0x9, 2, (MD_PLN | MD_EZI), FUNC5},
189  {0xC, 8, (MD_PLN | MD_EZI), FUNC4},
190 #endif
191  /* External data lines D0 .. D15 */
192  {0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
193  {0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
194  {0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
195  {0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
196  {0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
197  {0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
198  {0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
199  {0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
200  {0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
201  {0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
202  {0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
203  {0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
204  {0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
205  {0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
206  {0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
207  {0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
208  /* Address lines A0 .. A23 */
209  {0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
210  {0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
211  {0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
212  {0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
213  {0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
214  {0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
215  {0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
216  {0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
217  {0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
218  {0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
219  {0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
220  {0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
221  {0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
222  {0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
223  {0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
224  {0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
225  {0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
226  {0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
227  {0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
228  {0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
229  {0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
230  {0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
231  {0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
232  {0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
233  /* EMC control signals */
234  {0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
235  {0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
236  {0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
237  {0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
238  {0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
239  {0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
240  {0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
241  {0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
242  {PINMUX_CLK, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
243  {PINMUX_CLK, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
244  {PINMUX_CLK, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
245  {PINMUX_CLK, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
246  {0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
247  {0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
248  {0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
249  {0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
250  {0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
251  {0x1, 3, MD_PLN_FAST, FUNC3},
252  {0x1, 4, MD_PLN_FAST, FUNC3},
253  {0x6, 6, MD_PLN_FAST, FUNC3},
254  {0x1, 5, MD_PLN_FAST, FUNC3},
255  /* LCD interface, 24bpp */
256  {0x7, 7, MD_PUP, FUNC3},
257  {0x4, 7, MD_PUP, FUNC0},
258  {0x4, 5, MD_PUP, FUNC2},
259  {0x4, 6, MD_PUP, FUNC2},
260  {0x7, 6, MD_PUP, FUNC3},
261  {0x4, 1, MD_PUP, FUNC2},
262  {0x4, 4, MD_PUP, FUNC2},
263  {0x4, 2, MD_PUP, FUNC2},
264  {0x8, 7, MD_PUP, FUNC3},
265  {0x8, 6, MD_PUP, FUNC3},
266  {0x8, 5, MD_PUP, FUNC3},
267  {0x8, 4, MD_PUP, FUNC3},
268  {0x7, 5, MD_PUP, FUNC3},
269  {0x4, 8, MD_PUP, FUNC2},
270  {0x4, 10, MD_PUP, FUNC2},
271  {0x4, 9, MD_PUP, FUNC2},
272  {0x8, 3, MD_PUP, FUNC3},
273  {0xB, 6, MD_PUP, FUNC2},
274  {0xB, 5, MD_PUP, FUNC2},
275  {0xB, 4, MD_PUP, FUNC2},
276  {0x7, 4, MD_PUP, FUNC3},
277  {0x7, 2, MD_PUP, FUNC3},
278  {0x7, 1, MD_PUP, FUNC3},
279  {0xB, 3, MD_PUP, FUNC2},
280  {0xB, 2, MD_PUP, FUNC2},
281  {0xB, 1, MD_PUP, FUNC2},
282  {0xB, 0, MD_PUP, FUNC2},
283  {0x7, 0, MD_PUP, FUNC3},
284  {0x4, 4, MD_PUP, FUNC0},
285  {0x7, 3, MD_PUP, FUNC0},
286  {0x4, 1, MD_PUP, FUNC0},
287  /* Board LEDs */
288  {0x8, 1, MD_PDN, FUNC0},
289  {0xE, 6, MD_PDN, FUNC4}, /* GPIO7.6, green */
290  {0xE, 8, MD_PDN, FUNC4}, /* GPIO7.8, blue */
291  {0xE, 5, MD_PDN, FUNC4}, /* GPIO7.5, red */
292  /* Board ADC */
293  {0xF, 9, MD_PLN, FUNC7},
294  /* I2S */
295  {0x3, 0, MD_PLN_FAST, FUNC2},
296  {0x6, 0, MD_PLN_FAST, FUNC4},
297  {0x7, 2, MD_PLN_FAST, FUNC2},
298  {0x6, 2, MD_PLN_FAST, FUNC3},
299  {0x7, 1, MD_PLN_FAST, FUNC2},
300  {0x6, 1, MD_PLN_FAST, FUNC3},
301 };
302 
303 /* Sets up system pin muxing */
305 {
306  int i;
307 
308  /* Setup system level pin muxing */
309  for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
310  Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
311  pinmuxing[i].pincfg, pinmuxing[i].funcnum);
312  }
313 }
314 
315 /* EMC clock delay */
316 #define CLK0_DELAY 7
317 
318 /* Hitex SDRAM timing and chip Config */
320  EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
321  0x01, /* Command Delayed */
322  EMC_NANOSECOND(20),
323  EMC_NANOSECOND(60),
324  EMC_NANOSECOND(63),
325  EMC_CLOCK(0x05),
326  EMC_CLOCK(0x05),
327  EMC_CLOCK(0x04),
328  EMC_NANOSECOND(63),
329  EMC_NANOSECOND(63),
330  EMC_NANOSECOND(63),
331  EMC_NANOSECOND(14),
332  EMC_CLOCK(0x02),
333  {
334  {
335  EMC_ADDRESS_DYCS0, /* Hitex Board uses DYCS0 for SDRAM */
336  3, /* RAS */
337 
343 
348  },
349  {0, 0, 0, 0},
350  {0, 0, 0, 0},
351  {0, 0, 0, 0}
352  }
353 };
354 
355 /* Hitex Static RAM timing and chip Config */
357  2,
361  EMC_CONFIG_BUFFER_ENABLE*/,
362 
363  EMC_NANOSECOND(0),
364  EMC_NANOSECOND(30),
365  EMC_NANOSECOND(90),
366  EMC_NANOSECOND(55),
367  EMC_NANOSECOND(55),
368  EMC_NANOSECOND(55)
369 };
370 
371 /* Hitex NorFlash timing and chip Config */
373  0,
377  EMC_CONFIG_BUFFER_ENABLE*/,
378 
379  EMC_NANOSECOND(0),
380  EMC_NANOSECOND(35),
381  EMC_NANOSECOND(70),
382  EMC_NANOSECOND(70),
383  EMC_NANOSECOND(40),
384  EMC_CLOCK(4)
385 };
386 
387 /* Setup external memories */
389 {
390  /* Setup EMC Delays */
391  /* Move all clock delays together */
392  LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
393 
394  /* Setup EMC Clock Divider for divide by 2 */
395  Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
396  LPC_CREG->CREG6 |= (1 << 16);
398 
399  /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
400  Chip_EMC_Init(1, 0, 0);
401  /* Init EMC Dynamic Controller */
402  Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config);
403  /* Init EMC Static Controller CS2 */
404  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config);
405  /* Init EMC Static Controller CS0 */
406  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config);
407 
408  /* Enable Buffer for External Flash */
409  LPC_EMC->STATICCONFIG0 |= 1 << 19;
410 }
411 
412 #endif
413 
421 void SystemInit(void)
422 {
423 #if defined(CORE_M3) || defined(CORE_M4)
424  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
425 
426 #if defined(__IAR_SYSTEMS_ICC__)
427  extern void *__vector_table;
428 
429  *pSCB_VTOR = (unsigned int) &__vector_table;
430 #elif defined(__CODE_RED)
431  extern void *g_pfnVectors;
432 
433  *pSCB_VTOR = (unsigned int) &g_pfnVectors;
434 #elif defined(__ARMCC_VERSION)
435  extern void *__Vectors;
436 
437  *pSCB_VTOR = (unsigned int) &__Vectors;
438 #endif
439 
440 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
441  fpuInit();
442 #endif
443 
444  /* Setup system clocking and memory. This is done early to allow the
445  application and tools to clear memory and use scatter loading to
446  external memory. */
450 #endif
451 }
452