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sysinit_keil_mcb_18574357.c
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1 /*
2  * Copyright(C) NXP Semiconductors, 2012
3  * All rights reserved.
4  *
5  * Software that is described herein is for illustrative purposes only
6  * which provides customers with programming information regarding the
7  * LPC products. This software is supplied "AS IS" without any warranties of
8  * any kind, and NXP Semiconductors and its licensor disclaim any and
9  * all warranties, express or implied, including all implied warranties of
10  * merchantability, fitness for a particular purpose and non-infringement of
11  * intellectual property rights. NXP Semiconductors assumes no responsibility
12  * or liability for the use of the software, conveys no license or rights under any
13  * patent, copyright, mask work right, or any other intellectual property rights in
14  * or to any products. NXP Semiconductors reserves the right to make changes
15  * in the software without notification. NXP Semiconductors also makes no
16  * representation or warranty that such application will be suitable for the
17  * specified use without further testing or modification.
18  *
19  * Permission to use, copy, modify, and distribute this software and its
20  * documentation is hereby granted, under NXP Semiconductors' and its
21  * licensor's relevant copyrights in the software, without fee, provided that it
22  * is used in conjunction with NXP Semiconductors microcontrollers. This
23  * copyright, permission, and disclaimer notice must appear in all copies of
24  * this code.
25  */
26 
27 #include "board.h"
28 
51 #ifndef CORE_M0
52 /* SCR pin definitions for pin muxing */
53 typedef struct {
54  uint8_t pingrp; /* Pin group */
55  uint8_t pinnum; /* Pin number */
56  uint8_t pincfg; /* Pin configuration for SCU */
57  uint8_t funcnum;/* Function number */
58 } PINMUX_GRP_T;
59 
60 /* Structure for initial base clock states */
61 struct CLK_BASE_STATES {
62  CGU_BASE_CLK_T clk; /* Base clock */
63  CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
64  bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
65  bool powerdn; /* Set to true if the base clock is initially powered down */
66 };
67 
68 /* Initial base clock states are mostly on */
70  {CLK_BASE_SAFE, CLKIN_IRC, true, false},
71  {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
72  {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
73  {CLK_BASE_USB0, CLKIN_USBPLL, true, false},
74 #if defined(CHIP_LPC43XX)
75  {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
76 #endif
77  {CLK_BASE_USB1, CLKIN_USBPLL, true, false},
78 #if defined(CHIP_LPC43XX)
79  {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
80 #endif
81  {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
82 #if defined(USE_RMII)
83  {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
84 #else
85  {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
86 #endif
87  {CLK_BASE_LCD, CLKIN_MAINPLL, true, true},
88 #if defined(CHIP_LPC43XX)
89  {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
90 #endif
91  {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
92  {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
93  {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
94  {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
95  {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
96  {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
97  {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
98  {CLK_BASE_OUT, CLKINPUT_PD, true, false},
99  {CLK_BASE_APLL, CLKINPUT_PD, true, false},
100  {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
101  {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false}
102 };
103 
104 /* SPIFI high speed pin mode setup */
106  {0x3, 3, (MD_PLN_FAST), FUNC3},
107  {0x3, 4, (MD_PLN_FAST), FUNC3},
108  {0x3, 5, (MD_PLN_FAST), FUNC3},
109  {0x3, 6, (MD_PLN_FAST), FUNC3},
110  {0x3, 7, (MD_PLN_FAST), FUNC3},
111  {0x3, 8, (MD_PLN_FAST), FUNC3}
112 };
113 
114 /* Setup system clocking */
116 {
117  int i;
118 
119  /* Setup FLASH acceleration to target clock rate prior to clock switch */
121 
122  /* Switch main system clocking to crystal */
125 
126  /* Setup PLL for 100MHz and switch main system clocking */
127  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
129 
130  /* Setup PLL for maximum clock */
132 
133  /* Setup system base clocks and initial states. This won't enable and
134  disable individual clocks, but sets up the base clock sources for
135  each individual peripheral clock. */
136  for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
137  Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
138  InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
139  }
140 
141  /* Reset and enable 32Khz oscillator */
142  LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
143  LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
144 
145  /* SPIFI pin setup is done prior to setting up system clocking */
146  for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
147  Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
148  spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
149  }
150 
151  /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
152  Divide rate is based on CPU speed and speed of SPI FLASH part. */
153 #if (MAX_CLOCK_FREQ > 180000000)
155 #else
157 #endif
159 }
160 
162  /* RMII pin group */
163  {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0},
164  {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6},
165  {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
166  {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
167  {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
168  {0xC, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC3},
169  {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7},
170  {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3},
171  {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2},
172  /* External data lines D0 .. D15 */
173  {0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
174  {0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
175  {0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
176  {0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
177  {0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
178  {0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
179  {0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
180  {0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
181  {0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
182  {0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
183  {0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
184  {0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
185  {0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
186  {0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
187  {0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
188  {0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
189  {0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
190  {0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
191  {0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
192  {0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
193  {0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
194  {0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
195  {0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
196  {0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
197  {0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
198  {0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
199  {0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
200  {0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
201  {0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
202  {0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
203  {0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
204  {0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
205  /* Address lines A0 .. A23 */
206  {0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
207  {0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
208  {0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
209  {0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
210  {0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
211  {0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
212  {0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
213  {0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
214  {0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
215  {0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
216  {0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
217  {0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
218  {0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
219  {0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
220  {0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
221  {0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
222  {0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
223  {0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
224  {0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
225  {0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
226  {0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
227  {0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
228  {0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
229  {0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
230  /* EMC control signals */
231  {0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
232  {0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1},
233  {0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
234  {0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
235  {0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
236  {0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
237  {0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
238  {0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
239  {PINMUX_CLK, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
240  {PINMUX_CLK, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
241  {PINMUX_CLK, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
242  {PINMUX_CLK, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0},
243  {0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
244  {0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
245  {0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
246  {0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2},
247  {0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3},
248  {0x1, 3, MD_PLN_FAST, FUNC3},
249  {0x1, 4, MD_PLN_FAST, FUNC3},
250  {0x6, 6, MD_PLN_FAST, FUNC1},
251  {0x1, 5, MD_PLN_FAST, FUNC3},
252  {0x1, 6, MD_PLN_FAST, FUNC3},
253  /* Board LEDs */
254  {0xD, 10, (MD_PLN), FUNC4},
255  {0xD, 11, (MD_PLN), FUNC4},
256  {0xD, 12, (MD_PLN), FUNC4},
257  {0xD, 13, (MD_PLN), FUNC4},
258  {0xD, 14, (MD_PLN), FUNC4},
259  {0x9, 0, (MD_PLN), FUNC0},
260  {0x9, 1, (MD_PLN), FUNC0},
261  {0x9, 2, (MD_PLN), FUNC0},
262  /* SSP0 */
263  {0xF, 0, (MD_PLN_FAST), FUNC0},
264  {0xF, 1, (MD_PLN_FAST), FUNC4},
265  {0xF, 2, (MD_PLN_FAST), FUNC2},
266  {0xF, 3, (MD_PLN_FAST), FUNC2},
267  /* LCD interface, 16bpp */
268  {0x4, 1, MD_PUP, FUNC5},
269  {0x4, 2, MD_PUP, FUNC2},
270  {0x4, 5, MD_PUP, FUNC2},
271  {0x4, 6, MD_PUP, FUNC2},
272  {0x4, 7, MD_PUP, FUNC0},
273  {0x4, 9, MD_PUP, FUNC2},
274  {0x4, 10, MD_PUP, FUNC2},
275  {0x7, 0, MD_PUP, FUNC0},
276  {0x7, 6, MD_PUP, FUNC3},
277  {0x8, 3, MD_PUP, FUNC3},
278  {0x8, 4, MD_PUP, FUNC3},
279  {0x8, 5, MD_PUP, FUNC3},
280  {0x8, 6, MD_PUP, FUNC3},
281  {0x8, 7, MD_PUP, FUNC3},
282  {0xB, 0, MD_PUP, FUNC2},
283  {0xB, 1, MD_PUP, FUNC2},
284  {0xB, 2, MD_PUP, FUNC2},
285  {0xB, 3, MD_PUP, FUNC2},
286  {0xB, 4, MD_PUP, FUNC2},
287  {0xB, 5, MD_PUP, FUNC2},
288  {0xB, 6, MD_PUP, FUNC2},
289  /* I2S */
290  {0x3, 0, MD_PLN_FAST, FUNC2},
291  {0x6, 0, MD_PLN_FAST, FUNC4},
292  {0x7, 2, MD_PLN_FAST, FUNC2},
293  {0x6, 2, MD_PLN_FAST, FUNC3},
294  {0x7, 1, MD_PLN_FAST, FUNC2},
295  {0x6, 1, MD_PLN_FAST, FUNC3},
296 };
297 
298 /* Sets up system pin muxing */
300 {
301  int i;
302 
303  /* Setup system level pin muxing */
304  for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
305  Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
306  pinmuxing[i].pincfg, pinmuxing[i].funcnum);
307  }
308 }
309 
310 /* EMC clock delay */
311 #define CLK0_DELAY 7
312 
313 /* Keil SDRAM timing and chip Config */
315  EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
316  0x01, /* Command Delayed */
317  EMC_NANOSECOND(18),
318  EMC_NANOSECOND(42),
319  EMC_NANOSECOND(70),
320  EMC_CLOCK(0x01),
321  EMC_CLOCK(0x05),
322  EMC_NANOSECOND(12),
323  EMC_NANOSECOND(60),
324  EMC_NANOSECOND(60),
325  EMC_NANOSECOND(70),
326  EMC_NANOSECOND(12),
327  EMC_CLOCK(0x02),
328  {
329  {
330  EMC_ADDRESS_DYCS0, /* Keil Board uses DYCS0 for SDRAM */
331  3, /* RAS */
332 
338 
343  },
344  {0, 0, 0, 0},
345  {0, 0, 0, 0},
346  {0, 0, 0, 0}
347  }
348 };
349 
350 /* Keil NorFlash timing and chip Config */
351 /* FIXME : Keil NOR FLASH not yet tested */
353  0,
357  EMC_CONFIG_BUFFER_ENABLE*/,
358 
359  EMC_NANOSECOND(0),
360  EMC_NANOSECOND(65),
361  EMC_NANOSECOND(90),
362  EMC_NANOSECOND(90),
363  EMC_NANOSECOND(35),
364  EMC_CLOCK(4)
365 };
366 
367 /* Setup external memories */
369 {
370  /* Setup EMC Delays */
371  /* Move all clock delays together */
372  LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
373 
374  /* Setup EMC Clock Divider for divide by 2 */
375  Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
376  LPC_CREG->CREG6 |= (1 << 16);
378 
379  /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
380  Chip_EMC_Init(1, 0, 0);
381  /* Init EMC Dynamic Controller */
382  Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &MT48LC4M32_config);
383  /* Init EMC Static Controller CS0 */
384  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &S29GL64N90_config);
385 
386  /* Enable Buffer for External Flash */
387  LPC_EMC->STATICCONFIG0 |= 1 << 19;
388 }
389 
390 #endif
391 
399 void SystemInit(void)
400 {
401 #if defined(CORE_M3) || defined(CORE_M4)
402  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
403 
404 #if defined(__IAR_SYSTEMS_ICC__)
405  extern void *__vector_table;
406 
407  *pSCB_VTOR = (unsigned int) &__vector_table;
408 #elif defined(__CODE_RED)
409  extern void *g_pfnVectors;
410 
411  *pSCB_VTOR = (unsigned int) &g_pfnVectors;
412 #elif defined(__ARMCC_VERSION)
413  extern void *__Vectors;
414 
415  *pSCB_VTOR = (unsigned int) &__Vectors;
416 #endif
417 
418 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
419  fpuInit();
420 #endif
421 
422  /* Setup system clocking and memory. This is done early to allow the
423  application and tools to clear memory and use scatter loading to
424  external memory. */
428 #endif
429 }
430