In order to run this functional model you need to have a  
simulation license from Denali.  Refer the the DenaliSoft 
website for more information at 
 
http://www.denalisoft.com/partners.htm 
  
 
Included in this package is a sample test file for Cadence 
Verilog (xxx_test.v), a module file (xxx.v), and parameter 
files (xxx.spc) for the various speeds of this particular 
device.  If you are running on a platform other than Cadence 
Verilog, the test and module files can be generated by opening
one of the parameter files in MemMaker and performing a
Generate command fom the File Menu.
 

To run a specific parameter file, change the memory spec  
parameter in the sample test file (xxx_test.v) and the 
module file (xxx.v)  to the corresponding parameter file 
(xxx.spc) desired. 
 

To run this model with the sample test file included, your  
command line may be: 
 
% verilog  xxx_test.v  xxx.v 

 
To run this model with your own test file, your command 
line may be:

% verilog  <your test file>  xxx.v

 

