Project Name: S32K116EVB_OOBE_FreeMASTER_Firmware

Date Created: Jun 20, 2018, 3:59:02 PM

PIN Assignments for S32K116_48 48 LQFP48 package

24
23
22
21
20
19
18
17
16
15
14
13
PTB2
PTB3
PTC14
PTC15
PTC16
PTC1
PTD5
PTC2
PTC3
PTB4
PTB5
PTE8
25
LPUART0_TX
PTE9
12
26
LPUART0_RX
PTD15
11
27
PTC9
PTD16
10
28
PTC8
PTB6
9
29
PTA7
PTB7
8
30
VSS
VSS
7
31
VDD
VDDA
6
32
PTB13
VDD
5
33
PTD3
PTE4
4
34
PTD2
PTE5
3
35
PTA3
PTD0
2
36
PTA2
PTD1
1
PTA1
PTA0
LPUART1_TX
LPUART1_RX
PTA13
PTA12
PTA11
JTAG_TDO
JTAG_TDI
JTAG_TCLK/SWD_CLK
RESET_b
JTAG_TMS/SWD_DIO
37
38
39
40
41
42
43
44
45
46
47
48


Pin Allocation Report

PeripheralCustom peripheral namePeripheral description
ADC0ADC0Analog-to-Digital Converter
CAN0CAN0Flex Controller Area Network module
CMP0CMP0Analog comparator
FLEXIOFLEXIOFlexible IO
FTM0FTM0FlexTimer Module
FTM1FTM1FlexTimer Module
JTAGJTAGJoint Test Action Group (JTAG)
LPI2C0LPI2C0The LPI2C Memory Map/Register Definition can be found here.
LPSPI0LPSPI0The LPSPI Memory Map/Register Definition can be found here.
LPTMR0LPTMR0Low Power Timer
LPUART0LPUART0Universal Asynchronous Receiver/Transmitter
LPUART1LPUART1Universal Asynchronous Receiver/Transmitter
PTAPTAGeneral Purpose Input/Output
PTBPTBGeneral Purpose Input/Output
PTCPTCGeneral Purpose Input/Output
PTDPTDGeneral Purpose Input/Output
PTEPTEGeneral Purpose Input/Output
PlatformPlatformPlatform (Platform)
PowerAndGroundPowerAndGroundPower And Ground (PowerAndGround)
RTCRTCSecure Real Time Clock
SWDSWDSerial Wire Debug (SWD)
TRGMUXTRGMUXTRGMUX


Routed Pins

Assigned Pin Function(s)
Package Pin #Pin NameUser Assigned Signal NameAssigned PeripheralAssigned FunctionPackage FunctionDir
1PTD1same PTDport1alt1Output
2PTD0same PTDport0alt1Output
3PTE5same PTEport5alt1Input
4PTE4same PTEport4alt1Input
5VDD5same PowerAndGroundVDD5alt0Input
6VDDAsame PowerAndGroundVDDA6alt0Input
7VSS7same PowerAndGroundVSS7alt0Output
8PTB7same PTBport7alt1Input
9PTB6same PTBport6alt1Input
10PTD16same PTDport16alt1Input
11PTD15same PTDport15alt1Input
12PTE9same PTEport9alt1Output
13PTE8same PTEport8alt1Input
14PTB5same PTBport5alt1Output
15PTB4same PTBport4alt1Output
16PTC3same PTCport3alt1Output
17PTC2same PTCport2alt1Output
18PTD5same PTDport5alt1Input
19PTC1same PTCport1alt1Input
20PTC16same PTCport16alt1Input
21PTC15same PTCport15alt1Input
22PTC14same PTCport14alt1Input
23PTB3same PTBport3alt1Output
24PTB2same PTBport2alt1Output
25PTB1same LPUART0lpuart_txalt2Output
26PTB0same LPUART0lpuart_rxalt2Input
27PTC9same PTCport9alt1Input
28PTC8same PTCport8alt1Input
29PTA7same PTAport7alt1Input
30VSS30same PowerAndGroundVSS30alt0Output
31VDD31same PowerAndGroundVDD31alt0Input
32PTB13same PTBport13alt1Input
33PTD3same PTDport3alt1Input
34PTD2same PTDport2alt1Output
35PTA3same PTAport3alt1Output
36PTA2same PTAport2alt1Output
37PTA1same PTAport1alt1Input
38PTA0same PTAport0alt1Input
39PTC7same LPUART1lpuart_txalt2Output
40PTC6same LPUART1lpuart_rxalt2Input
41PTA13same PTAport13alt1Output
42PTA12same PTAport12alt1Output
43PTA11same PTAport11alt1Input
44PTA10same JTAGjtag_tdoalt7Output
45PTC5same JTAGjtag_tdialt7Input
46PTC4same JTAGjtag_tclkalt7Input
SWDswd_clkalt7Input
47PTA5same Platformreset_b47alt7Output
48PTA4same JTAGjtag_tmsalt7Input/Output
SWDswd_dioalt7Input/Output

Routable Pins

alt0alt1alt2alt3alt4alt5alt6alt7
Package Pin #Pin NameUser Assigned Signal Name PeripheralFunctionDir PeripheralFunctionDir PeripheralFunctionDir PeripheralFunctionDir PeripheralFunctionDir PeripheralFunctionDir PeripheralFunctionDir PeripheralFunctionDir
1PTD1same PTDport1Input, Output FTM0ftm_ch3Input, Output FLEXIOfxio_d1Input/Output TRGMUXtrg_out2Output
2PTD0same PTDport0Input, Output FTM0ftm_ch2Input, Output FLEXIOfxio_d0Input/Output TRGMUXtrg_out1Output
3PTE5same PTEport5Input, Output FTM0ftm_tclk2Input CAN0can_txtxdOutput FLEXIOfxio_d7Input/Output
4PTE4same PTEport4Input, Output CAN0can_rxrxdInput FLEXIOfxio_d6Input/Output
5VDD5same PowerAndGroundVDD5Input
6VDDAsame PowerAndGroundVDDA6Input
7VSS7same PowerAndGroundVSS7Output
8PTB7same PTBport7Input, Output LPI2C0lpi2c_sclsclInput/Output
9PTB6same PTBport6Input, Output LPI2C0lpi2c_sdasdaInput/Output
10PTD16same PTDport16Input, Output FTM0ftm_ch1Input, Output LPSPI0lpspi_sinInput, Output, Input/Output CMP0cmp_rrtOutput
11PTD15same PTDport15Input, Output FTM0ftm_ch0Input, Output LPSPI0lpspi_scksckInput, Output, Input/Output
12PTE9same PTEport9Input, Output FTM0ftm_ch7Input, Output
13PTE8same CMP0cmp_in3Input PTEport8Input, Output FTM0ftm_ch6Input, Output
14PTB5same PTBport5Input, Output FTM0ftm_ch5Input, Output LPSPI0lpspi_pcs1Input, Output, Input/Output LPSPI0lpspi_pcs0Input, Output, Input/Output Platformclkout14Output TRGMUXtrg_in0Input
15PTB4same PTBport4Input, Output FTM0ftm_ch4Input, Output LPSPI0lpspi_soutInput, Output, Input/Output TRGMUXtrg_in1Input
16PTC3same ADC0
CMP0		adc_se11
cmp_in4		Input PTCport3Input, Output FTM0ftm_ch3Input, Output CAN0can_txtxdOutput LPUART0lpuart_txInput, Output, Input/Output
17PTC2same ADC0
CMP0		adc_se10
cmp_in5		Input PTCport2Input, Output FTM0ftm_ch2Input, Output CAN0can_rxrxdInput LPUART0lpuart_rxInput
18PTD5same PTDport5Input, Output LPTMR0lptmr_alt2Input TRGMUXtrg_in7Input
19PTC1same ADC0adc_se9Input PTCport1Input, Output FTM0ftm_ch1Input, Output FTM1ftm_ch7Input, Output
20PTC16same ADC0adc_se14Input PTCport16Input, Output FTM1ftm_flt2Input
21PTC15same ADC0adc_se13Input PTCport15Input, Output FTM1ftm_ch3Input, Output TRGMUXtrg_in8Input
22PTC14same ADC0adc_se12Input PTCport14Input, Output FTM1ftm_ch2Input, Output TRGMUXtrg_in9Input
23PTB3same ADC0adc_se7Input PTBport3Input, Output FTM1ftm_ch1Input, Output LPSPI0lpspi_sinInput, Output, Input/Output FTM1ftm_qd_phaInput TRGMUXtrg_in2Input
24PTB2same ADC0adc_se6Input PTBport2Input, Output FTM1ftm_ch0Input, Output LPSPI0lpspi_scksckInput, Output, Input/Output FTM1ftm_qd_phbInput TRGMUXtrg_in3Input
25PTB1same ADC0adc_se5Input PTBport1Input, Output LPUART0lpuart_txInput, Output, Input/Output LPSPI0lpspi_soutInput, Output, Input/Output FTM0ftm_tclk0Input CAN0can_txtxdOutput
26PTB0same ADC0adc_se4Input PTBport0Input, Output LPUART0lpuart_rxInput LPSPI0lpspi_pcs0Input, Output, Input/Output LPTMR0lptmr_alt3Input CAN0can_rxrxdInput
27PTC9same PTCport9Input, Output LPUART1lpuart_txInput, Output, Input/Output FTM1ftm_flt1Input LPUART0lpuart_rtsOutput
28PTC8same PTCport8Input, Output LPUART1lpuart_rxInput FTM1ftm_flt0Input LPUART0lpuart_ctsInput
29PTA7same ADC0adc_se3Input PTAport7Input, Output FTM0ftm_flt2Input RTCrtc_clkinInput LPUART1lpuart_rtsOutput
30VSS30same PowerAndGroundVSS30Output
31VDD31same PowerAndGroundVDD31Input
32PTB13same PTBport13Input, Output FTM0ftm_ch1Input, Output
33PTD3same PTDport3Input, Output FLEXIOfxio_d5Input/Output FLEXIOfxio_d7Input/Output TRGMUXtrg_in4Input Platformnmi_b33Input
34PTD2same PTDport2Input, Output FLEXIOfxio_d4Input/Output FLEXIOfxio_d6Input/Output TRGMUXtrg_in5Input
35PTA3same PTAport3Input, Output LPI2C0lpi2c_sclsclInput/Output FLEXIOfxio_d5Input/Output LPUART0lpuart_txInput, Output, Input/Output
36PTA2same PTAport2Input, Output LPI2C0lpi2c_sdasdaInput/Output FLEXIOfxio_d4Input/Output LPUART0lpuart_rxInput
37PTA1same ADC0
CMP0		adc_se1
cmp_in1		Input PTAport1Input, Output FTM1ftm_ch1Input, Output LPI2C0lpi2c_sdassdasInput/Output FLEXIOfxio_d3Input/Output FTM1ftm_qd_phaInput LPUART0lpuart_rtsOutput TRGMUXtrg_out0Output
38PTA0same ADC0
CMP0		adc_se0
cmp_in0		Input PTAport0Input, Output LPI2C0lpi2c_sclssclsInput/Output FLEXIOfxio_d2Input/Output LPUART0lpuart_ctsInput TRGMUXtrg_out3Output
39PTC7same PTCport7Input, Output LPUART1lpuart_txInput, Output, Input/Output FTM1ftm_qd_phaInput
40PTC6same PTCport6Input, Output LPUART1lpuart_rxInput FTM1ftm_qd_phbInput
41PTA13same PTAport13Input, Output FTM1ftm_ch7Input, Output
42PTA12same PTAport12Input, Output FTM1ftm_ch6Input, Output
43PTA11same PTAport11Input, Output FTM1ftm_ch5Input, Output FLEXIOfxio_d1Input/Output CMP0cmp_rrtOutput
44PTA10same PTAport10Input, Output FTM1ftm_ch4Input, Output FLEXIOfxio_d0Input/Output JTAGjtag_tdoOutput
45PTC5same PTCport5Input, Output RTCrtc_clkoutOutput JTAGjtag_tdiInput
46PTC4same CMP0cmp_in2Input PTCport4Input, Output FTM1ftm_ch0Input, Output RTCrtc_clkoutOutput FTM1ftm_qd_phbInput JTAG
SWD		jtag_tclk
swd_clk		Input
47PTA5same PTAport5Input, Output FTM0ftm_tclk1Input Platformreset_b47Output
48PTA4same PTAport4Input, Output CMP0cmp_outOutput JTAG
SWD		jtag_tms
swd_dio		Input/Output