//FS26-C1 - OTP Editor
//file generated on lun. fvr. 5 11:42:51 2024
//Device Type:FS26-D
//OTP ID:AL
//Customer:NXP
//Part Number:MFS2633AMDALAD

//Write main registers

//Test mode entry
SET_REG:FS26-C1:M_TestMode:M_TM_ENTRY:0x0000
SET_REG:FS26-C1:M_TestMode:M_TM_ENTRY:0xD5A7
SET_REG:FS26-C1:M_TestMode:M_TM_ENTRY:0xB8EE
SET_REG:FS26-C1:M_TestMode:M_TM_ENTRY:0x0F37
//Verify test mode entry _expect 0x0100


//MAIN_VOTP
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x011B
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0010
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x011C
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0020
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x011D
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x011E
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x011F
//MAIN_OTP
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0038
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0120
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0054
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0121
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0080
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0122
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x00d4
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0123
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0030
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0124
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x008d
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0125
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x000a
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0126
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x00e1
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0127
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0001
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0128
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x006b
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0129
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x004a
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x012A
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0038
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x012B
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x006b
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x012C
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x002b
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x012D
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x002b
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x012E
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x001d
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x012F
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0020
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0130
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0047
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0131
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0042
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0132
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0021
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0133
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0038
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0134
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0007
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0135
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0007
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0136
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x000b
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0137
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x005f
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0138
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0057
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x0139
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x001c
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x013A
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x013B
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0014
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x013C
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x013D
SET_REG:FS26-C1:M_TestMode:M_MIRRORDATA:0x0000
SET_REG:FS26-C1:M_TestMode:M_MIRRORCMD:0x013E

//OTP Command CRC_Fill + GO
SET_REG:FS26-C1:M_TestMode:M_OTPCMD:0x0125

//OTP Command CRC_Check + GO
SET_REG:FS26-C1:M_TestMode:M_OTPCMD:0x0124

//Verify tet mode entry _expect 0x0000
GET_REG:FS26-C1:M_TestMode:M_TM_STATUS1
//----------------------------- END MAIN ----------------------------


//Write Fail safe registers

//Fail Safe Test mode entry
SET_REG:FS26-C1:FS_TestMode:FS_TM_ENTRY:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_TM_ENTRY:0xD5A7
SET_REG:FS26-C1:FS_TestMode:FS_TM_ENTRY:0xB8EE
SET_REG:FS26-C1:FS_TestMode:FS_TM_ENTRY:0x0F37
//Verify tet mode entry _expect 0x0000
GET_REG:FS26-C1:FS_TestMode:FS_TM_STATUS1


//FAILSAFE_VOTP
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x010A
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0044
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x010B
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x010C
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x010D
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x010E
//FAILSAFE_OTP
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0038
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x010F
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0047
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0110
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x007b
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0111
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x00bb
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0112
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0003
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0113
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0033
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0114
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0033
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0115
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0011
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0116
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0011
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0117
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0118
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x00bb
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0119
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x00ff
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x011A
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x00ff
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x011B
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x00ff
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x011C
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x004f
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x011D
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x011E
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x011F
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0120
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0121
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORDATA:0x0000
SET_REG:FS26-C1:FS_TestMode:FS_MIRRORCMD:0x0122

//OTP Command CRC_Fill + GO
SET_REG:FS26-C1:FS_TestMode:FS_OTPCMD:0x0125

//OTP Command CRC_Check + GO
SET_REG:FS26-C1:FS_TestMode:FS_OTPCMD:0x0124

//Verify tet mode entry _expect 0x0000
GET_REG:FS26-C1:FS_TestMode:FS_TM_STATUS1
//---------------------------- END FAILSAFE ------------------------------


//Rev,A
