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fsl_pit_features.h
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/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if !defined(__FSL_PIT_FEATURES_H__)
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#define __FSL_PIT_FEATURES_H__
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// NOTE: Cpu type is defined as part of the project configuration.
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#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
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defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
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defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
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defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
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defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
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defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
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defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
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defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
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defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
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defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
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/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
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#define FSL_FEATURE_PIT_TIMER_COUNT (4)
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/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
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#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
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/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
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#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (0)
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#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
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defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
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defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
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defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
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defined(CPU_MK64FX512VMD12) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
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defined(CPU_MKV31F512VLL12)
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/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
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#define FSL_FEATURE_PIT_TIMER_COUNT (4)
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/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
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#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
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/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
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#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
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#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
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defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
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/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
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#define FSL_FEATURE_PIT_TIMER_COUNT (4)
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/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
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#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
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/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
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#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
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#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
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defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
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defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
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defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
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defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
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defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || \
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defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || \
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defined(CPU_MKL46Z256VMC4)
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/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn).*/
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#define FSL_FEATURE_PIT_TIMER_COUNT (2)
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/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H).*/
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#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
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/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]).*/
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#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
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#else
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#error "No valid CPU defined!"
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#endif
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#endif
/* __FSL_PIT_FEATURES_H__*/
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/*******************************************************************************
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* EOF
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******************************************************************************/
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© Freescale Semiconductor, Inc. 2015. All Rights Reserved.