NXP® SemiconductorsMSE9S12XS128_1M04M
Mask Set ErrataRev. April 16, 2012



MC9S12XS128, Mask 1M04M


Introduction
This errata sheet applies to the following devices:

MC9S12XS128, MC9S12XS64



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts03867 s12_cpu_xs CPU: Breakpoint missed at simultaneous taghits YES
MUCts03977 pwm_8b8c PWM: Emergency shutdown input can be overruled YES
MUCts04135 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode YES
MUCts04136 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode YES
MUCts04157 tim_16b8c TIM_16B8C: Output compare pulse is inaccurate YES
MUCts04177 s12xe_crg s12xe_crg: Possible PLL premature LOCK followed by an UN-LOCK in conjunction with STOP instruction YES
MUCts04243 sci SCI: RXEDGIF occurs more times than expected in IR mode YES



CPU: Breakpoint missed at simultaneous taghitsMUCts03867

Description

The CPU execution priority encoder evaluates taghits and then 

generates a breakpoint if a taghit must lead to an immediate
breakpoint as determined by the DBG module.

If the DBG module indicates that this taghit leads to an immediate
breakpoint then the CPU loads the execution stage with SWI or BGND thus
generating the breakpoint.

At simultaneous taghits the lowest channel has priority.
If taghits on 2 channels simultaneously, whereby the lower channel tag
must be ignored, but the higher channel tag must cause a breakpoint,
then the breakpoint request is erroneously missed.
Thus if channel[1:0] taghits occur simultaneously whereby channel[0]
must be ignored but channel[1] must cause a breakpoint, then the
breakpoint request on channel[1] is erroneously missed and no
breakpoint generated.

The DBG module recognises the taghit and the state sequencer
transitions accordingly. Furthermore the taghit causes the DBG module
to request a forced breakpoint, which means that a late CPU breakpoint
occurs. If the tagged instruction is a single cycle instruction, the
breakpoint occurs at the second instruction following the tagged
instruction.
Otherwise the breakpoint occurs at the instruction immediately
following the tagged instruction.

This bug requires that separate tags are placed on the same
instruction. This is not a typical case when using exact tag addresses.
It is more relevant in debugging environments using range modes, where
tags may cover a whole range. In this case a tagged range may cover a
tag or another tagged range, making simultaneous taghits possible.

This is a debugging issue only.

Workaround


Do not attach multiple tags to the same exact address. 

When attaching multiple tags to the same address by overlapping tag
ranges in range modes, or covering a tag with a tag range in range
modes, then the missed tag can be avoided by mapping the final state
change to the lower channel number.

For example the case
Channel[0] tags a range; channel[3] tags an instruction within that
range.
From DBG State1 Taghit[0] leads to State2. (DBGSCR1=$6)
From DBG State2 Taghit[3] leads to FinalState.(DBGSCR2=$5)
In State2 a simultaneous Taghit[3,0] scenario would miss the breakpoint.

This can be avoided by using the alternative DBG configuration
Channel[2] tags a range; channel[0] tags an instruction within that
range.
From DBG State1 Taghit[2] leads to State2. (DBGSCR1=$3)
From DBG State2 Taghit[0] leads to FinalState.(DBGSCR2=$7)



PWM: Emergency shutdown input can be overruledMUCts03977

Description

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 7 by setting the PWME7 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.




PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04135

Description

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels do
not show the state which is set by PWMLVL bit when the 16-bit counter is
non-zero.




Workaround


If emergency shutdown mode is required:


In 16-bit concatenation mode, user can disable the related PWM
channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.





PWM: Wrong output value after restart from stop or wait modeMUCts04136

Description

In low power modes (P-STOP/STOP/WAIT mode) and during PWM7

de-assert and when PWM counter reaching 0, the PWM channel outputs
cannot keep the state which is set by PWMLVL bit.






Workaround


Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.








TIM_16B8C: Output compare pulse is inaccurateMUCts04157

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision V02.07 (04

May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.







s12xe_crg: Possible PLL premature LOCK followed by an UN-LOCK in conjunction with STOP instructionMUCts04177

Description

If the PLL is manually turned off (PLLCTL_ PLLON = 0) before a STOP

instruction and the PLL is manually turned on (PLLCTL_PLLON=1) after
execution of the STOP instruction, the PLL might have a premature lock
condition in the case of a STOP instruction being executed with a
pending interrupt and the corresponding interrupt is enabled. In this
case the STOP is executed similar to NOP instruction.

Due to the manual control of the PLL, the VCO clock is switched on and
off. The PLL lock detection logic uses the VCO clock as well as the
reference clock (based on the external oscillator). The external
oscillator is not stopped because the STOP instruction is executed like
a NOP instruction, which keeps the reference clock running.

This causes the logic in the PLL lock detection being uncorrelated and
thus resulting in a possible premature LOCK condition (CRGFLG_LOCK=1).

After the next lock detection cycle the lock is lost (CRGFLG_LOCK=0)
because the VCO clock frequency has not reached the correct value. Some
lock detection cycles later the correct lock condition is reached (VCO
clock frequency reached the correct value) and the LOCK bit is set again
(CRGFLG_LOCK=1). Each transition of the LOCK bit is indicated by the
lock interrupt flag (CRGFLG_LOCKIF).

Workaround


Do not modify the PLLON bit around the STOP instruction. 


The clock control and power down/up sequencing is automatically done by
the device CRG module. Only the system clock source selection after exit
from STOP must be controlled by software (CLKSEL_PLLSEL bit) as
described in the Reference Manual.

Depending on the application if the fast wake-up feature is used the
software also needs to control the bit FSTWKP and bit SCME (both located
in the PLLCTL register) as described in the device Reference Manual when
STOP Mode is entered or exited.






SCI: RXEDGIF occurs more times than expected in IR modeMUCts04243

Description

Configured for Infrared Receive mode, the SCI may incorrectly set the 

RXEDGIF bit if there are consecutive '00' data bits. There are two
cases:

Case 1: due to re-sync of the RXD input, the received edge may be
delayed by one bus cycle. If an edge (bit = '0') is detected near
an SCI clock edge, the next edge (bit = '0') may be detected one
SCI clock later than expected due to re-sync logic.

Case 2: if external baud is slower than SCI receiver, the next edge
may be detected later than expected.

This glitch can be detected by the RXEDGIF circuit, but it does not
impact the final data result because the SCI receive and data recovery
logic takes samples at RT8, RT9, and RT10.




Workaround


Case 1 and case 2 may occurs at same time. To avoid those unexpected 

RXEDGIF at IR mode, the external baud should be kept a little bit
faster than receiver baud by:
P > (1/16)/(SBR)
or
(P)(SBR)(16)> 1

Where SBR is baud of receiver, P is external baud faster ratio.
For example:
1.- When SBR = 16, P = 0.4%, this means the external baud should be at
least 0.4% faster than receiver.
2.- When SBR = 4, P = 1.6%, this means the external baud should be at
least 1.6% faster than receiver.

Case 1 will cover case 2, i.e. case 1 is the worst case. If case1 is
solved, case 2 is also solved.


© NXP Semiconductors, Inc., 2012. All rights reserved.