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MKMxxZxxACxx5 Bare Metal Software Drivers
R4.1.6
Reference Manual
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List of timer primary count sources.
Any BUS_CLK_DIV1 .. BUS_CLK_DIV128 sources represents primary clock source configured by the SIM_SelTmrPcs macro.
Macros | |
| #define | PRM_CNTR0_INP |
| Counter 0 input pin. | |
| #define | PRM_CNTR1_INP |
| Counter 1 input pin. | |
| #define | PRM_CNTR2_INP |
| Counter 2 input pin. | |
| #define | PRM_CNTR3_INP |
| Counter 3 input pin. | |
| #define | PRM_CNTR0_OUT |
| Counter 0 output. | |
| #define | PRM_CNTR1_OUT |
| Counter 1 output. | |
| #define | PRM_CNTR2_OUT |
| Counter 2 output. | |
| #define | PRM_CNTR3_OUT |
| Counter 3 output. | |
| #define | BUS_CLK_DIV1 |
| IP bus clock divide by 1 prescaler. | |
| #define | BUS_CLK_DIV2 |
| IP bus clock divide by 2 prescaler. | |
| #define | BUS_CLK_DIV4 |
| IP bus clock divide by 4 prescaler. | |
| #define | BUS_CLK_DIV8 |
| IP bus clock divide by 8 prescaler. | |
| #define | BUS_CLK_DIV16 |
| IP bus clock divide by 16 prescaler. | |
| #define | BUS_CLK_DIV32 |
| IP bus clock divide by 32 prescaler. | |
| #define | BUS_CLK_DIV64 |
| IP bus clock divide by 64 prescaler. | |
| #define | BUS_CLK_DIV128 |
| IP bus clock divide by 128 prescaler. | |