DMA Configuration Structures

Overview

This section describes default configuration structures for DMA channel configuration. Create a new configuration structure if default ones don't initialize on-chip peripheral in required operating mode (see Creating Configuration Structure).

Macros
#define	DMA_CH_SWTRG_M2M_CN_CONFIG(srcaddr, dstaddr, nbytes)
	Selects and starts software triggered continuous memory to memory data transfer. More...
#define	DMA_CH_SWTRG_M2P_CN_CONFIG(srcaddr, regsize, regaddr, nbytes)
	Selects software initiated continuous memory to peripheral data transfer. More...
#define	DMA_CH_HWTRG_M2M_CN_CONFIG(reqsrc, regsize, srcaddr, dstaddr, nbytes)
	Selects and starts hardware triggered continuous memory to memory data transfer. More...
#define	DMA_CH_HWTRG_M2M_CS_CONFIG(reqsrc, regsize, srcaddr, dstaddr, nbytes)
	Selects and starts hardware triggered cycle steal memory to memory data transfer. More...
#define	DMA_CH_HWTRG_P2M_CS_CONFIG(reqsrc, regsize, regaddr, dstaddr, nbytes)
	Selects hardware initiated cycle steal peripheral to memory data transfer. More...
#define	DMA_CH_HWTRG_M2P_CS_CONFIG(reqsrc, srcaddr, regsize, regaddr, nbytes)
	Selects hardware initiated cycle steal memory to peripheral data transfer. More...
#define	DMA_CH_HWTRG_P2P_CS_LOOP_CONFIG(reqsrc, regsize, reg1addr, reg2addr, nbytes)
	Selects hardware initiated cycle steal peripheral to peripheral data transfer executed in a loop. More...

Macro Definition Documentation

#define DMA_CH_SWTRG_M2M_CN_CONFIG	(		srcaddr,
			dstaddr,
			nbytes
	)

Value:

(tDMA_CH){                                                                    \
/* CHCFG */  CLR(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|         \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(0)), /* DMA_REQ_DISABLED */              \
/* SAR   */  (uint32)srcaddr,                                                 \
/* DAR   */  (uint32)dstaddr,                                                 \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),            \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|CLR(DMA_DCR_ERQ_MASK)|                    \
/* ...   */  CLR(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))| \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|CLR(DMA_DCR_EADREQ_MASK)|                  \
/* ...   */  SET(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(DMA_SIZE8BIT))|         \
/* ...   */  SET(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(DMA_SIZE8BIT))|         \
/* ...   */  SET(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                    \
/* ...   */  SET(DMA_DCR_DMOD(0))|CLR(DMA_DCR_D_REQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0)) \
}

Configures and starts DMA channel to operate in software trigger continuous memory to memory data transfer.

Parameters

srcaddr	Source memory buffer address (uint32).
dstaddr	Destination memory buffer address (uint32).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.

#define DMA_CH_SWTRG_M2P_CN_CONFIG	(		srcaddr,
			regsize,
			regaddr,
			nbytes
	)

Value:

(tDMA_CH){                                                                    \
/* CHCFG */  CLR(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|         \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(0)), /* DMA_REQ_DISABLED */              \
/* SAR   */  (uint32)srcaddr,                                                 \
/* DAR   */  (uint32)regaddr,                                                 \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),            \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|CLR(DMA_DCR_ERQ_MASK)|                    \
/* ...   */  CLR(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))| \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|CLR(DMA_DCR_EADREQ_MASK)|                  \
/* ...   */  SET(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(regsize))|              \
/* ...   */  CLR(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(regsize))|              \
/* ...   */  SET(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                    \
/* ...   */  SET(DMA_DCR_DMOD(0))|CLR(DMA_DCR_D_REQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0)) \
}

Configures software initiated continuous memory to peripheral data transfer.

Parameters

srcaddr	Source memory buffer address (uint32-regsize aligned)
regsize	Select DMA Transfer Sizes.
regaddr	Destination peripheral register address (uint32).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.

#define DMA_CH_HWTRG_M2M_CN_CONFIG	(		reqsrc,
			regsize,
			srcaddr,
			dstaddr,
			nbytes
	)

Value:

(tDMA_CH){                                                                    \
/* CHCFG */  SET(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|         \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(reqsrc)),                                \
/* SAR   */  (uint32)srcaddr,                                                 \
/* DAR   */  (uint32)dstaddr,                                                 \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),            \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|SET(DMA_DCR_ERQ_MASK)|                    \
/* ...   */  CLR(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))| \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|SET(DMA_DCR_EADREQ_MASK)|                  \
/* ...   */  SET(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(regsize))|              \
/* ...   */  SET(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(regsize))|              \
/* ...   */  CLR(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                    \
/* ...   */  SET(DMA_DCR_DMOD(0))|SET(DMA_DCR_D_REQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0)) \
}

Configures and starts DMA channel to operate in hardware trigger continuous memory to memory data transfer.

Parameters

reqsrc	Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources.
regsize	Select DMA Transfer Sizes.
srcaddr	Source memory buffer address (uint32).
dstaddr	Destination memory buffer address (uint32).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.

#define DMA_CH_HWTRG_M2M_CS_CONFIG	(		reqsrc,
			regsize,
			srcaddr,
			dstaddr,
			nbytes
	)

Value:

(tDMA_CH){                                                                    \
/* CHCFG */  SET(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|         \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(reqsrc)),                                \
/* SAR   */  (uint32)srcaddr,                                                 \
/* DAR   */  (uint32)dstaddr,                                                 \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),            \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|SET(DMA_DCR_ERQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))| \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|SET(DMA_DCR_EADREQ_MASK)|                  \
/* ...   */  SET(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(regsize))|              \
/* ...   */  SET(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(regsize))|              \
/* ...   */  CLR(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                    \
/* ...   */  SET(DMA_DCR_DMOD(0))|SET(DMA_DCR_D_REQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0)) \
}

Configures and starts DMA channel to operate in hardware trigger cycle steal memory to memory data transfer.

Parameters

reqsrc	Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources.
regsize	Select DMA Transfer Sizes.
srcaddr	Source memory buffer address (uint32).
dstaddr	Destination memory buffer address (uint32).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.

#define DMA_CH_HWTRG_P2M_CS_CONFIG	(		reqsrc,
			regsize,
			regaddr,
			dstaddr,
			nbytes
	)

Value:

(tDMA_CH){                                                                    \
/* CHCFG */  SET(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|         \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(reqsrc)),                                \
/* SAR   */  (uint32)regaddr,                                                 \
/* DAR   */  (uint32)dstaddr,                                                 \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),            \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|SET(DMA_DCR_ERQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))| \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|SET(DMA_DCR_EADREQ_MASK)|                  \
/* ...   */  CLR(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(regsize))|              \
/* ...   */  SET(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(regsize))|              \
/* ...   */  CLR(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                    \
/* ...   */  SET(DMA_DCR_DMOD(0))|SET(DMA_DCR_D_REQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0)) \
}

Configures hardware initiated cycle steal peripheral to memory data transfer.

Parameters

reqsrc	Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources.
regsize	Select DMA Transfer Sizes.
regaddr	Peripheral register address (uint32).
dstaddr	Destination memory buffer address (uint32-regsize aligned).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.

#define DMA_CH_HWTRG_M2P_CS_CONFIG	(		reqsrc,
			srcaddr,
			regsize,
			regaddr,
			nbytes
	)

Value:

(tDMA_CH){                                                                    \
/* CHCFG */  SET(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|         \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(reqsrc)),                                \
/* SAR   */  (uint32)srcaddr,                                                 \
/* DAR   */  (uint32)regaddr,                                                 \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),            \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|SET(DMA_DCR_ERQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))| \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|SET(DMA_DCR_EADREQ_MASK)|                  \
/* ...   */  SET(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(regsize))|              \
/* ...   */  CLR(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(regsize))|              \
/* ...   */  CLR(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                    \
/* ...   */  SET(DMA_DCR_DMOD(0))|SET(DMA_DCR_D_REQ_MASK)|                    \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0)) \
}

Configures hardware initiated cycle steal memory to peripheral data transfer.

Parameters

reqsrc	Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources.
srcaddr	Source memory buffer address (uint32-regsize aligned)
regsize	Select DMA Transfer Sizes.
regaddr	Destination peripheral register address (uint32).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.

#define DMA_CH_HWTRG_P2P_CS_LOOP_CONFIG	(		reqsrc,
			regsize,
			reg1addr,
			reg2addr,
			nbytes
	)

Value:

(tDMA_CH){                                                                       \
/* CHCFG */  SET(DMAMUX_CHCFG_ENBL_MASK)|CLR(DMAMUX_CHCFG_TRIG_MASK)|            \
/* ..... */  SET(DMAMUX_CHCFG_SOURCE(reqsrc)),                                   \
/* SAR   */  (uint32)reg1addr,                                                   \
/* DAR   */  (uint32)reg2addr,                                                   \
/* DSR   */  CLR(DMA_DSR_BCR_DONE_MASK)|((uint32)nbytes&0x0FFFFF),               \
/* DCR   */  CLR(DMA_DCR_EINT_MASK)|SET(DMA_DCR_ERQ_MASK)|                       \
/* ...   */  SET(DMA_DCR_CS_MASK)|CLR(DMA_DCR_AA_MASK)|CLR(DMA_DCR_CHACR(0))|    \
/* ...   */  CLR(DMA_DCR_UMNSM(0))|SET(DMA_DCR_EADREQ_MASK)|                     \
/* ...   */  CLR(DMA_DCR_SINC_MASK)|SET(DMA_DCR_SSIZE(regsize))|                 \
/* ...   */  CLR(DMA_DCR_DINC_MASK)|SET(DMA_DCR_DSIZE(regsize))|                 \
/* ...   */  CLR(DMA_DCR_START_MASK)|SET(DMA_DCR_SMOD(0))|                       \
/* ...   */  SET(DMA_DCR_DMOD(0))|SET(DMA_DCR_D_REQ_MASK)|                       \
/* ...   */  SET(DMA_DCR_LINKCC(0))|SET(DMA_DCR_LCH1(0))|SET(DMA_DCR_LCH2(0))    \
}

Configures hardware initiated cycle steal peripheral to peripheral data transfer executed in a loop.

Parameters

reqsrc	Request source chosen for DMA channel being configured: DMA0=DMA Channel 0 Request Sources DMA1=DMA Channel 1 Request Sources DMA2=DMA Channel 2 Request Sources DMA3=DMA Channel 3 Request Sources.
regsize	Select DMA Transfer Sizes.
reg1addr	Source peripheral register address (uint32).
reg2addr	Destination peripheral register address (uint32).
nbytes	Bytes count to be transferred in range 0x000001 to 0x0FFFFF.

Note

Implemented as an inline macro.