!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.8	//
A1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t A1;                                     \/**< I2C Address Register 1, offset: 0x0 *\/$/;"	m	struct:I2C_MemMap
A2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t A2;                                     \/**< I2C Address Register 2, offset: 0x9 *\/$/;"	m	struct:I2C_MemMap
ADC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	725;"	d
ADC_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	727;"	d
ADC_CAL	.\Static_Code\IO_Map\MC56F82748.h	820;"	d
ADC_CAL_REG	.\Static_Code\IO_Map\MC56F82748.h	292;"	d
ADC_CAL_SEL_VREFH_A_MASK	.\Static_Code\IO_Map\MC56F82748.h	547;"	d
ADC_CAL_SEL_VREFH_A_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	548;"	d
ADC_CAL_SEL_VREFH_B_MASK	.\Static_Code\IO_Map\MC56F82748.h	551;"	d
ADC_CAL_SEL_VREFH_B_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	552;"	d
ADC_CAL_SEL_VREFL_A_MASK	.\Static_Code\IO_Map\MC56F82748.h	545;"	d
ADC_CAL_SEL_VREFL_A_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	546;"	d
ADC_CAL_SEL_VREFL_B_MASK	.\Static_Code\IO_Map\MC56F82748.h	549;"	d
ADC_CAL_SEL_VREFL_B_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	550;"	d
ADC_CLIST1	.\Static_Code\IO_Map\MC56F82748.h	745;"	d
ADC_CLIST1_REG	.\Static_Code\IO_Map\MC56F82748.h	277;"	d
ADC_CLIST1_SAMPLE0	.\Static_Code\IO_Map\MC56F82748.h	423;"	d
ADC_CLIST1_SAMPLE0_MASK	.\Static_Code\IO_Map\MC56F82748.h	421;"	d
ADC_CLIST1_SAMPLE0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	422;"	d
ADC_CLIST1_SAMPLE1	.\Static_Code\IO_Map\MC56F82748.h	426;"	d
ADC_CLIST1_SAMPLE1_MASK	.\Static_Code\IO_Map\MC56F82748.h	424;"	d
ADC_CLIST1_SAMPLE1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	425;"	d
ADC_CLIST1_SAMPLE2	.\Static_Code\IO_Map\MC56F82748.h	429;"	d
ADC_CLIST1_SAMPLE2_MASK	.\Static_Code\IO_Map\MC56F82748.h	427;"	d
ADC_CLIST1_SAMPLE2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	428;"	d
ADC_CLIST1_SAMPLE3	.\Static_Code\IO_Map\MC56F82748.h	432;"	d
ADC_CLIST1_SAMPLE3_MASK	.\Static_Code\IO_Map\MC56F82748.h	430;"	d
ADC_CLIST1_SAMPLE3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	431;"	d
ADC_CLIST2	.\Static_Code\IO_Map\MC56F82748.h	746;"	d
ADC_CLIST2_REG	.\Static_Code\IO_Map\MC56F82748.h	278;"	d
ADC_CLIST2_SAMPLE4	.\Static_Code\IO_Map\MC56F82748.h	436;"	d
ADC_CLIST2_SAMPLE4_MASK	.\Static_Code\IO_Map\MC56F82748.h	434;"	d
ADC_CLIST2_SAMPLE4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	435;"	d
ADC_CLIST2_SAMPLE5	.\Static_Code\IO_Map\MC56F82748.h	439;"	d
ADC_CLIST2_SAMPLE5_MASK	.\Static_Code\IO_Map\MC56F82748.h	437;"	d
ADC_CLIST2_SAMPLE5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	438;"	d
ADC_CLIST2_SAMPLE6	.\Static_Code\IO_Map\MC56F82748.h	442;"	d
ADC_CLIST2_SAMPLE6_MASK	.\Static_Code\IO_Map\MC56F82748.h	440;"	d
ADC_CLIST2_SAMPLE6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	441;"	d
ADC_CLIST2_SAMPLE7	.\Static_Code\IO_Map\MC56F82748.h	445;"	d
ADC_CLIST2_SAMPLE7_MASK	.\Static_Code\IO_Map\MC56F82748.h	443;"	d
ADC_CLIST2_SAMPLE7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	444;"	d
ADC_CLIST3	.\Static_Code\IO_Map\MC56F82748.h	747;"	d
ADC_CLIST3_REG	.\Static_Code\IO_Map\MC56F82748.h	279;"	d
ADC_CLIST3_SAMPLE10	.\Static_Code\IO_Map\MC56F82748.h	455;"	d
ADC_CLIST3_SAMPLE10_MASK	.\Static_Code\IO_Map\MC56F82748.h	453;"	d
ADC_CLIST3_SAMPLE10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	454;"	d
ADC_CLIST3_SAMPLE11	.\Static_Code\IO_Map\MC56F82748.h	458;"	d
ADC_CLIST3_SAMPLE11_MASK	.\Static_Code\IO_Map\MC56F82748.h	456;"	d
ADC_CLIST3_SAMPLE11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	457;"	d
ADC_CLIST3_SAMPLE8	.\Static_Code\IO_Map\MC56F82748.h	449;"	d
ADC_CLIST3_SAMPLE8_MASK	.\Static_Code\IO_Map\MC56F82748.h	447;"	d
ADC_CLIST3_SAMPLE8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	448;"	d
ADC_CLIST3_SAMPLE9	.\Static_Code\IO_Map\MC56F82748.h	452;"	d
ADC_CLIST3_SAMPLE9_MASK	.\Static_Code\IO_Map\MC56F82748.h	450;"	d
ADC_CLIST3_SAMPLE9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	451;"	d
ADC_CLIST4	.\Static_Code\IO_Map\MC56F82748.h	748;"	d
ADC_CLIST4_REG	.\Static_Code\IO_Map\MC56F82748.h	280;"	d
ADC_CLIST4_SAMPLE12	.\Static_Code\IO_Map\MC56F82748.h	462;"	d
ADC_CLIST4_SAMPLE12_MASK	.\Static_Code\IO_Map\MC56F82748.h	460;"	d
ADC_CLIST4_SAMPLE12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	461;"	d
ADC_CLIST4_SAMPLE13	.\Static_Code\IO_Map\MC56F82748.h	465;"	d
ADC_CLIST4_SAMPLE13_MASK	.\Static_Code\IO_Map\MC56F82748.h	463;"	d
ADC_CLIST4_SAMPLE13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	464;"	d
ADC_CLIST4_SAMPLE14	.\Static_Code\IO_Map\MC56F82748.h	468;"	d
ADC_CLIST4_SAMPLE14_MASK	.\Static_Code\IO_Map\MC56F82748.h	466;"	d
ADC_CLIST4_SAMPLE14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	467;"	d
ADC_CLIST4_SAMPLE15	.\Static_Code\IO_Map\MC56F82748.h	471;"	d
ADC_CLIST4_SAMPLE15_MASK	.\Static_Code\IO_Map\MC56F82748.h	469;"	d
ADC_CLIST4_SAMPLE15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	470;"	d
ADC_CLIST5	.\Static_Code\IO_Map\MC56F82748.h	828;"	d
ADC_CLIST5_REG	.\Static_Code\IO_Map\MC56F82748.h	300;"	d
ADC_CLIST5_SAMPLE16	.\Static_Code\IO_Map\MC56F82748.h	640;"	d
ADC_CLIST5_SAMPLE16_MASK	.\Static_Code\IO_Map\MC56F82748.h	638;"	d
ADC_CLIST5_SAMPLE16_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	639;"	d
ADC_CLIST5_SAMPLE17	.\Static_Code\IO_Map\MC56F82748.h	643;"	d
ADC_CLIST5_SAMPLE17_MASK	.\Static_Code\IO_Map\MC56F82748.h	641;"	d
ADC_CLIST5_SAMPLE17_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	642;"	d
ADC_CLIST5_SAMPLE18	.\Static_Code\IO_Map\MC56F82748.h	646;"	d
ADC_CLIST5_SAMPLE18_MASK	.\Static_Code\IO_Map\MC56F82748.h	644;"	d
ADC_CLIST5_SAMPLE18_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	645;"	d
ADC_CLIST5_SAMPLE19	.\Static_Code\IO_Map\MC56F82748.h	649;"	d
ADC_CLIST5_SAMPLE19_MASK	.\Static_Code\IO_Map\MC56F82748.h	647;"	d
ADC_CLIST5_SAMPLE19_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	648;"	d
ADC_CLIST5_SEL_INTERNAL_0_MASK	.\Static_Code\IO_Map\MC56F82748.h	652;"	d
ADC_CLIST5_SEL_INTERNAL_0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	653;"	d
ADC_CLIST5_SEL_INTERNAL_1_MASK	.\Static_Code\IO_Map\MC56F82748.h	656;"	d
ADC_CLIST5_SEL_INTERNAL_1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	657;"	d
ADC_CLIST5_SEL_TEMP_0_MASK	.\Static_Code\IO_Map\MC56F82748.h	650;"	d
ADC_CLIST5_SEL_TEMP_0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	651;"	d
ADC_CLIST5_SEL_TEMP_1_MASK	.\Static_Code\IO_Map\MC56F82748.h	654;"	d
ADC_CLIST5_SEL_TEMP_1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	655;"	d
ADC_CTRL1	.\Static_Code\IO_Map\MC56F82748.h	741;"	d
ADC_CTRL1_CHNCFG_L	.\Static_Code\IO_Map\MC56F82748.h	334;"	d
ADC_CTRL1_CHNCFG_L_MASK	.\Static_Code\IO_Map\MC56F82748.h	332;"	d
ADC_CTRL1_CHNCFG_L_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	333;"	d
ADC_CTRL1_DMAEN0_MASK	.\Static_Code\IO_Map\MC56F82748.h	349;"	d
ADC_CTRL1_DMAEN0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	350;"	d
ADC_CTRL1_EOSIE0_MASK	.\Static_Code\IO_Map\MC56F82748.h	341;"	d
ADC_CTRL1_EOSIE0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	342;"	d
ADC_CTRL1_HLMTIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	335;"	d
ADC_CTRL1_HLMTIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	336;"	d
ADC_CTRL1_LLMTIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	337;"	d
ADC_CTRL1_LLMTIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	338;"	d
ADC_CTRL1_REG	.\Static_Code\IO_Map\MC56F82748.h	273;"	d
ADC_CTRL1_SMODE	.\Static_Code\IO_Map\MC56F82748.h	331;"	d
ADC_CTRL1_SMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	329;"	d
ADC_CTRL1_SMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	330;"	d
ADC_CTRL1_START0_MASK	.\Static_Code\IO_Map\MC56F82748.h	345;"	d
ADC_CTRL1_START0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	346;"	d
ADC_CTRL1_STOP0_MASK	.\Static_Code\IO_Map\MC56F82748.h	347;"	d
ADC_CTRL1_STOP0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	348;"	d
ADC_CTRL1_SYNC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	343;"	d
ADC_CTRL1_SYNC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	344;"	d
ADC_CTRL1_ZCIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	339;"	d
ADC_CTRL1_ZCIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	340;"	d
ADC_CTRL2	.\Static_Code\IO_Map\MC56F82748.h	742;"	d
ADC_CTRL2_CHNCFG_H	.\Static_Code\IO_Map\MC56F82748.h	359;"	d
ADC_CTRL2_CHNCFG_H_MASK	.\Static_Code\IO_Map\MC56F82748.h	357;"	d
ADC_CTRL2_CHNCFG_H_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	358;"	d
ADC_CTRL2_DIV0	.\Static_Code\IO_Map\MC56F82748.h	354;"	d
ADC_CTRL2_DIV0_MASK	.\Static_Code\IO_Map\MC56F82748.h	352;"	d
ADC_CTRL2_DIV0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	353;"	d
ADC_CTRL2_DMAEN1_MASK	.\Static_Code\IO_Map\MC56F82748.h	368;"	d
ADC_CTRL2_DMAEN1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	369;"	d
ADC_CTRL2_EOSIE1_MASK	.\Static_Code\IO_Map\MC56F82748.h	360;"	d
ADC_CTRL2_EOSIE1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	361;"	d
ADC_CTRL2_REG	.\Static_Code\IO_Map\MC56F82748.h	274;"	d
ADC_CTRL2_SIMULT_MASK	.\Static_Code\IO_Map\MC56F82748.h	355;"	d
ADC_CTRL2_SIMULT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	356;"	d
ADC_CTRL2_START1_MASK	.\Static_Code\IO_Map\MC56F82748.h	364;"	d
ADC_CTRL2_START1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	365;"	d
ADC_CTRL2_STOP1_MASK	.\Static_Code\IO_Map\MC56F82748.h	366;"	d
ADC_CTRL2_STOP1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	367;"	d
ADC_CTRL2_SYNC1_MASK	.\Static_Code\IO_Map\MC56F82748.h	362;"	d
ADC_CTRL2_SYNC1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	363;"	d
ADC_CTRL3	.\Static_Code\IO_Map\MC56F82748.h	825;"	d
ADC_CTRL3_DMASRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	612;"	d
ADC_CTRL3_DMASRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	613;"	d
ADC_CTRL3_REG	.\Static_Code\IO_Map\MC56F82748.h	297;"	d
ADC_CTRL3_UPDEN_H	.\Static_Code\IO_Map\MC56F82748.h	619;"	d
ADC_CTRL3_UPDEN_H_MASK	.\Static_Code\IO_Map\MC56F82748.h	617;"	d
ADC_CTRL3_UPDEN_H_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	618;"	d
ADC_CTRL3_UPDEN_L	.\Static_Code\IO_Map\MC56F82748.h	616;"	d
ADC_CTRL3_UPDEN_L_MASK	.\Static_Code\IO_Map\MC56F82748.h	614;"	d
ADC_CTRL3_UPDEN_L_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	615;"	d
ADC_CYCLIC_PDD_ALL_END_OF_SCAN_FLAGS	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	71;"	d
ADC_CYCLIC_PDD_ALTERNATIVE_INPUT_0	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	127;"	d
ADC_CYCLIC_PDD_ALTERNATIVE_INPUT_1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	128;"	d
ADC_CYCLIC_PDD_ALTERNATIVE_INPUT_2	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	129;"	d
ADC_CYCLIC_PDD_ALTERNATIVE_INPUT_3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	130;"	d
ADC_CYCLIC_PDD_AMPLIFICATION_X1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	157;"	d
ADC_CYCLIC_PDD_AMPLIFICATION_X2	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	158;"	d
ADC_CYCLIC_PDD_AMPLIFICATION_X4	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	159;"	d
ADC_CYCLIC_PDD_ANA0	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	109;"	d
ADC_CYCLIC_PDD_ANA1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	110;"	d
ADC_CYCLIC_PDD_ANA2	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	111;"	d
ADC_CYCLIC_PDD_ANA3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	112;"	d
ADC_CYCLIC_PDD_ANA4	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	113;"	d
ADC_CYCLIC_PDD_ANA5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	114;"	d
ADC_CYCLIC_PDD_ANA6	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	115;"	d
ADC_CYCLIC_PDD_ANA7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	116;"	d
ADC_CYCLIC_PDD_ANB0	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	117;"	d
ADC_CYCLIC_PDD_ANB1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	118;"	d
ADC_CYCLIC_PDD_ANB2	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	119;"	d
ADC_CYCLIC_PDD_ANB3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	120;"	d
ADC_CYCLIC_PDD_ANB4	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	121;"	d
ADC_CYCLIC_PDD_ANB5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	122;"	d
ADC_CYCLIC_PDD_ANB6	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	123;"	d
ADC_CYCLIC_PDD_ANB7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	124;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANA0_1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	87;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANA2_3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	88;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANA4_5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	93;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANA6_7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	94;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANB0_1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	89;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANB2_3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	90;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANB4_5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	95;"	d
ADC_CYCLIC_PDD_CHANNEL_CONFIG_ANB6_7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	96;"	d
ADC_CYCLIC_PDD_CONTINUE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	162;"	d
ADC_CYCLIC_PDD_CONVERSION_IN_PROGRESS_0_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	79;"	d
ADC_CYCLIC_PDD_CONVERSION_IN_PROGRESS_1_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	80;"	d
ADC_CYCLIC_PDD_CONVERTER_A_POWER_DOWN_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	83;"	d
ADC_CYCLIC_PDD_CONVERTER_B_POWER_DOWN_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	84;"	d
ADC_CYCLIC_PDD_ClearEndOfScanInterruptFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1569;"	d
ADC_CYCLIC_PDD_ClearHighLimitInterruptFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1929;"	d
ADC_CYCLIC_PDD_ClearLowLimitInterruptFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1777;"	d
ADC_CYCLIC_PDD_ClearZeroCrossingInterruptFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2081;"	d
ADC_CYCLIC_PDD_DMA_SOURCE_EOSI	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	166;"	d
ADC_CYCLIC_PDD_DMA_SOURCE_RDY	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	167;"	d
ADC_CYCLIC_PDD_DisableEndOfScanInterrupt	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	317;"	d
ADC_CYCLIC_PDD_DisableEndOfScanInterrupt1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	650;"	d
ADC_CYCLIC_PDD_DisableInterrupts	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	367;"	d
ADC_CYCLIC_PDD_END_OF_SCAN_0_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	69;"	d
ADC_CYCLIC_PDD_END_OF_SCAN_0_INT	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	63;"	d
ADC_CYCLIC_PDD_END_OF_SCAN_1_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	70;"	d
ADC_CYCLIC_PDD_EnableAutoPowerdown	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2441;"	d
ADC_CYCLIC_PDD_EnableAutoStandby	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2407;"	d
ADC_CYCLIC_PDD_EnableDmaRequest	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	192;"	d
ADC_CYCLIC_PDD_EnableDmaRequest1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	525;"	d
ADC_CYCLIC_PDD_EnableEndOfScanInterrupt	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	295;"	d
ADC_CYCLIC_PDD_EnableEndOfScanInterrupt1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	628;"	d
ADC_CYCLIC_PDD_EnableInterrupts	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	342;"	d
ADC_CYCLIC_PDD_EnablePower	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2502;"	d
ADC_CYCLIC_PDD_EnableSample	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1394;"	d
ADC_CYCLIC_PDD_EnableScanHaltedInterrupt	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3095;"	d
ADC_CYCLIC_PDD_EnableSimultaneousMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	711;"	d
ADC_CYCLIC_PDD_EnableSyncMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	249;"	d
ADC_CYCLIC_PDD_EnableSyncMode1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	582;"	d
ADC_CYCLIC_PDD_EnableUnipolarDifferentialMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	817;"	d
ADC_CYCLIC_PDD_GetHighLimitStatusFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1901;"	d
ADC_CYCLIC_PDD_GetInterruptFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1535;"	d
ADC_CYCLIC_PDD_GetLowLimitStatusFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1749;"	d
ADC_CYCLIC_PDD_GetPowerDownStatus	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2530;"	d
ADC_CYCLIC_PDD_GetSampleReady	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1675;"	d
ADC_CYCLIC_PDD_GetScanMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	453;"	d
ADC_CYCLIC_PDD_GetStatusFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1593;"	d
ADC_CYCLIC_PDD_GetZeroCrossingStatusFlags	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2053;"	d
ADC_CYCLIC_PDD_HIGH_LIMIT_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	74;"	d
ADC_CYCLIC_PDD_HIGH_LIMIT_INT	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	66;"	d
ADC_CYCLIC_PDD_H_	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	9;"	d
ADC_CYCLIC_PDD_LOOP_PARALLEL_MODE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	146;"	d
ADC_CYCLIC_PDD_LOOP_SEQUENTIAL_MODE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	145;"	d
ADC_CYCLIC_PDD_LOW_LIMIT_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	75;"	d
ADC_CYCLIC_PDD_LOW_LIMIT_INT	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	65;"	d
ADC_CYCLIC_PDD_ONCE_PARALLEL_MODE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	144;"	d
ADC_CYCLIC_PDD_ONCE_SEQUENTIAL_MODE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	143;"	d
ADC_CYCLIC_PDD_PAUSE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	163;"	d
ADC_CYCLIC_PDD_POWER_CONVERTER_A	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	133;"	d
ADC_CYCLIC_PDD_POWER_CONVERTER_B	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	134;"	d
ADC_CYCLIC_PDD_ReadCalibrationReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2737;"	d
ADC_CYCLIC_PDD_ReadChannelList1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1177;"	d
ADC_CYCLIC_PDD_ReadChannelList2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1224;"	d
ADC_CYCLIC_PDD_ReadChannelList3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1271;"	d
ADC_CYCLIC_PDD_ReadChannelList4Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1318;"	d
ADC_CYCLIC_PDD_ReadChannelList5Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1365;"	d
ADC_CYCLIC_PDD_ReadControl1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	499;"	d
ADC_CYCLIC_PDD_ReadControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	787;"	d
ADC_CYCLIC_PDD_ReadControl3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	894;"	d
ADC_CYCLIC_PDD_ReadGainControl1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2829;"	d
ADC_CYCLIC_PDD_ReadGainControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2876;"	d
ADC_CYCLIC_PDD_ReadGainControl3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2923;"	d
ADC_CYCLIC_PDD_ReadHighLimitReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2326;"	d
ADC_CYCLIC_PDD_ReadHighLimitStatus2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2027;"	d
ADC_CYCLIC_PDD_ReadHighLimitStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1980;"	d
ADC_CYCLIC_PDD_ReadLowLimitReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2277;"	d
ADC_CYCLIC_PDD_ReadLowLimitStatus2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1875;"	d
ADC_CYCLIC_PDD_ReadLowLimitStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1828;"	d
ADC_CYCLIC_PDD_ReadOffsetReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2375;"	d
ADC_CYCLIC_PDD_ReadPowerControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2656;"	d
ADC_CYCLIC_PDD_ReadPowerControlReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2580;"	d
ADC_CYCLIC_PDD_ReadReady2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1723;"	d
ADC_CYCLIC_PDD_ReadReadyReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1701;"	d
ADC_CYCLIC_PDD_ReadResultReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2228;"	d
ADC_CYCLIC_PDD_ReadSampleDisable2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1510;"	d
ADC_CYCLIC_PDD_ReadSampleDisableReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1463;"	d
ADC_CYCLIC_PDD_ReadScanControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3066;"	d
ADC_CYCLIC_PDD_ReadScanControlReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3019;"	d
ADC_CYCLIC_PDD_ReadScanHaltedInterruptEnable2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3213;"	d
ADC_CYCLIC_PDD_ReadScanHaltedInterruptEnableReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3165;"	d
ADC_CYCLIC_PDD_ReadStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1649;"	d
ADC_CYCLIC_PDD_ReadZeroCrossingControl1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	981;"	d
ADC_CYCLIC_PDD_ReadZeroCrossingControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1028;"	d
ADC_CYCLIC_PDD_ReadZeroCrossingControl3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1075;"	d
ADC_CYCLIC_PDD_ReadZeroCrossingStatus2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2179;"	d
ADC_CYCLIC_PDD_ReadZeroCrossingStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2132;"	d
ADC_CYCLIC_PDD_SAMPLE0	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	41;"	d
ADC_CYCLIC_PDD_SAMPLE1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	42;"	d
ADC_CYCLIC_PDD_SAMPLE10	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	51;"	d
ADC_CYCLIC_PDD_SAMPLE11	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	52;"	d
ADC_CYCLIC_PDD_SAMPLE12	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	53;"	d
ADC_CYCLIC_PDD_SAMPLE13	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	54;"	d
ADC_CYCLIC_PDD_SAMPLE14	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	55;"	d
ADC_CYCLIC_PDD_SAMPLE15	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	56;"	d
ADC_CYCLIC_PDD_SAMPLE16	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	57;"	d
ADC_CYCLIC_PDD_SAMPLE17	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	58;"	d
ADC_CYCLIC_PDD_SAMPLE18	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	59;"	d
ADC_CYCLIC_PDD_SAMPLE19	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	60;"	d
ADC_CYCLIC_PDD_SAMPLE2	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	43;"	d
ADC_CYCLIC_PDD_SAMPLE3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	44;"	d
ADC_CYCLIC_PDD_SAMPLE4	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	45;"	d
ADC_CYCLIC_PDD_SAMPLE5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	46;"	d
ADC_CYCLIC_PDD_SAMPLE6	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	47;"	d
ADC_CYCLIC_PDD_SAMPLE7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	48;"	d
ADC_CYCLIC_PDD_SAMPLE8	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	49;"	d
ADC_CYCLIC_PDD_SAMPLE9	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	50;"	d
ADC_CYCLIC_PDD_SelectDMASource	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	846;"	d
ADC_CYCLIC_PDD_SelectGainControl	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2766;"	d
ADC_CYCLIC_PDD_SelectSampleInput	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1102;"	d
ADC_CYCLIC_PDD_SelectScanControl	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2950;"	d
ADC_CYCLIC_PDD_SelectScanMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	426;"	d
ADC_CYCLIC_PDD_SelectVoltageReferenceSources	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2686;"	d
ADC_CYCLIC_PDD_SelectZeroCrossingMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	921;"	d
ADC_CYCLIC_PDD_SetChannelConfigureHigh	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	680;"	d
ADC_CYCLIC_PDD_SetChannelConfigureLow	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	397;"	d
ADC_CYCLIC_PDD_SetClockDivisor	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	737;"	d
ADC_CYCLIC_PDD_SetClockDivisor1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2605;"	d
ADC_CYCLIC_PDD_SetPowerUpDelay	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2469;"	d
ADC_CYCLIC_PDD_SetStopMode	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	220;"	d
ADC_CYCLIC_PDD_SetStopMode1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	553;"	d
ADC_CYCLIC_PDD_StartConversion	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	273;"	d
ADC_CYCLIC_PDD_StartConversion1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	606;"	d
ADC_CYCLIC_PDD_TRIGGERED_PARALLEL_MODE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	148;"	d
ADC_CYCLIC_PDD_TRIGGERED_SEQUENTIAL_MODE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	147;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANA0_1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	99;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANA2_3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	100;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANA4_5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	103;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANA6_7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	104;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANB0_1	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	101;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANB2_3	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	102;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANB4_5	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	105;"	d
ADC_CYCLIC_PDD_UNIPOLAR_ANB6_7	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	106;"	d
ADC_CYCLIC_PDD_VOLTAGE_REFERENCE_HIGH_A	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	138;"	d
ADC_CYCLIC_PDD_VOLTAGE_REFERENCE_HIGH_B	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	140;"	d
ADC_CYCLIC_PDD_VOLTAGE_REFERENCE_LOW_A	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	137;"	d
ADC_CYCLIC_PDD_VOLTAGE_REFERENCE_LOW_B	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	139;"	d
ADC_CYCLIC_PDD_WriteCalibrationReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2714;"	d
ADC_CYCLIC_PDD_WriteChannelList1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1154;"	d
ADC_CYCLIC_PDD_WriteChannelList2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1201;"	d
ADC_CYCLIC_PDD_WriteChannelList3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1248;"	d
ADC_CYCLIC_PDD_WriteChannelList4Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1295;"	d
ADC_CYCLIC_PDD_WriteChannelList5Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1342;"	d
ADC_CYCLIC_PDD_WriteControl1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	477;"	d
ADC_CYCLIC_PDD_WriteControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	765;"	d
ADC_CYCLIC_PDD_WriteControl3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	872;"	d
ADC_CYCLIC_PDD_WriteGainControl1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2806;"	d
ADC_CYCLIC_PDD_WriteGainControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2853;"	d
ADC_CYCLIC_PDD_WriteGainControl3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2900;"	d
ADC_CYCLIC_PDD_WriteHighLimitReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2302;"	d
ADC_CYCLIC_PDD_WriteHighLimitStatus2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2004;"	d
ADC_CYCLIC_PDD_WriteHighLimitStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1957;"	d
ADC_CYCLIC_PDD_WriteLowLimitReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2253;"	d
ADC_CYCLIC_PDD_WriteLowLimitStatus2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1852;"	d
ADC_CYCLIC_PDD_WriteLowLimitStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1805;"	d
ADC_CYCLIC_PDD_WriteOffsetReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2351;"	d
ADC_CYCLIC_PDD_WritePowerControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2633;"	d
ADC_CYCLIC_PDD_WritePowerControlReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2557;"	d
ADC_CYCLIC_PDD_WriteResultReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2204;"	d
ADC_CYCLIC_PDD_WriteSampleDisable2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1487;"	d
ADC_CYCLIC_PDD_WriteSampleDisableReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1440;"	d
ADC_CYCLIC_PDD_WriteScanControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3043;"	d
ADC_CYCLIC_PDD_WriteScanControlReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2996;"	d
ADC_CYCLIC_PDD_WriteScanHaltedInterruptEnable2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3190;"	d
ADC_CYCLIC_PDD_WriteScanHaltedInterruptEnableReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	3142;"	d
ADC_CYCLIC_PDD_WriteStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1627;"	d
ADC_CYCLIC_PDD_WriteZeroCrossingControl1Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	958;"	d
ADC_CYCLIC_PDD_WriteZeroCrossingControl2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1005;"	d
ADC_CYCLIC_PDD_WriteZeroCrossingControl3Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	1052;"	d
ADC_CYCLIC_PDD_WriteZeroCrossingStatus2Reg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2156;"	d
ADC_CYCLIC_PDD_WriteZeroCrossingStatusReg	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	2109;"	d
ADC_CYCLIC_PDD_ZERO_CROSSING_ANY_CHANGE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	154;"	d
ADC_CYCLIC_PDD_ZERO_CROSSING_DISABLED	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	151;"	d
ADC_CYCLIC_PDD_ZERO_CROSSING_FLAG	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	76;"	d
ADC_CYCLIC_PDD_ZERO_CROSSING_INT	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	64;"	d
ADC_CYCLIC_PDD_ZERO_CROSSING_NEGATIVE_TO_POSITIVE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	153;"	d
ADC_CYCLIC_PDD_ZERO_CROSSING_POSITIVE_TO_NEGATIVE	.\Static_Code\PDD\ADC_CYCLIC_PDD.h	152;"	d
ADC_GC1	.\Static_Code\IO_Map\MC56F82748.h	821;"	d
ADC_GC1_GAIN0	.\Static_Code\IO_Map\MC56F82748.h	556;"	d
ADC_GC1_GAIN0_MASK	.\Static_Code\IO_Map\MC56F82748.h	554;"	d
ADC_GC1_GAIN0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	555;"	d
ADC_GC1_GAIN1	.\Static_Code\IO_Map\MC56F82748.h	559;"	d
ADC_GC1_GAIN1_MASK	.\Static_Code\IO_Map\MC56F82748.h	557;"	d
ADC_GC1_GAIN1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	558;"	d
ADC_GC1_GAIN2	.\Static_Code\IO_Map\MC56F82748.h	562;"	d
ADC_GC1_GAIN2_MASK	.\Static_Code\IO_Map\MC56F82748.h	560;"	d
ADC_GC1_GAIN2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	561;"	d
ADC_GC1_GAIN3	.\Static_Code\IO_Map\MC56F82748.h	565;"	d
ADC_GC1_GAIN3_MASK	.\Static_Code\IO_Map\MC56F82748.h	563;"	d
ADC_GC1_GAIN3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	564;"	d
ADC_GC1_GAIN4	.\Static_Code\IO_Map\MC56F82748.h	568;"	d
ADC_GC1_GAIN4_MASK	.\Static_Code\IO_Map\MC56F82748.h	566;"	d
ADC_GC1_GAIN4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	567;"	d
ADC_GC1_GAIN5	.\Static_Code\IO_Map\MC56F82748.h	571;"	d
ADC_GC1_GAIN5_MASK	.\Static_Code\IO_Map\MC56F82748.h	569;"	d
ADC_GC1_GAIN5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	570;"	d
ADC_GC1_GAIN6	.\Static_Code\IO_Map\MC56F82748.h	574;"	d
ADC_GC1_GAIN6_MASK	.\Static_Code\IO_Map\MC56F82748.h	572;"	d
ADC_GC1_GAIN6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	573;"	d
ADC_GC1_GAIN7	.\Static_Code\IO_Map\MC56F82748.h	577;"	d
ADC_GC1_GAIN7_MASK	.\Static_Code\IO_Map\MC56F82748.h	575;"	d
ADC_GC1_GAIN7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	576;"	d
ADC_GC1_REG	.\Static_Code\IO_Map\MC56F82748.h	293;"	d
ADC_GC2	.\Static_Code\IO_Map\MC56F82748.h	822;"	d
ADC_GC2_GAIN10	.\Static_Code\IO_Map\MC56F82748.h	587;"	d
ADC_GC2_GAIN10_MASK	.\Static_Code\IO_Map\MC56F82748.h	585;"	d
ADC_GC2_GAIN10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	586;"	d
ADC_GC2_GAIN11	.\Static_Code\IO_Map\MC56F82748.h	590;"	d
ADC_GC2_GAIN11_MASK	.\Static_Code\IO_Map\MC56F82748.h	588;"	d
ADC_GC2_GAIN11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	589;"	d
ADC_GC2_GAIN12	.\Static_Code\IO_Map\MC56F82748.h	593;"	d
ADC_GC2_GAIN12_MASK	.\Static_Code\IO_Map\MC56F82748.h	591;"	d
ADC_GC2_GAIN12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	592;"	d
ADC_GC2_GAIN13	.\Static_Code\IO_Map\MC56F82748.h	596;"	d
ADC_GC2_GAIN13_MASK	.\Static_Code\IO_Map\MC56F82748.h	594;"	d
ADC_GC2_GAIN13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	595;"	d
ADC_GC2_GAIN14	.\Static_Code\IO_Map\MC56F82748.h	599;"	d
ADC_GC2_GAIN14_MASK	.\Static_Code\IO_Map\MC56F82748.h	597;"	d
ADC_GC2_GAIN14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	598;"	d
ADC_GC2_GAIN15	.\Static_Code\IO_Map\MC56F82748.h	602;"	d
ADC_GC2_GAIN15_MASK	.\Static_Code\IO_Map\MC56F82748.h	600;"	d
ADC_GC2_GAIN15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	601;"	d
ADC_GC2_GAIN8	.\Static_Code\IO_Map\MC56F82748.h	581;"	d
ADC_GC2_GAIN8_MASK	.\Static_Code\IO_Map\MC56F82748.h	579;"	d
ADC_GC2_GAIN8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	580;"	d
ADC_GC2_GAIN9	.\Static_Code\IO_Map\MC56F82748.h	584;"	d
ADC_GC2_GAIN9_MASK	.\Static_Code\IO_Map\MC56F82748.h	582;"	d
ADC_GC2_GAIN9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	583;"	d
ADC_GC2_REG	.\Static_Code\IO_Map\MC56F82748.h	294;"	d
ADC_GC3	.\Static_Code\IO_Map\MC56F82748.h	850;"	d
ADC_GC3_GAIN16	.\Static_Code\IO_Map\MC56F82748.h	699;"	d
ADC_GC3_GAIN16_MASK	.\Static_Code\IO_Map\MC56F82748.h	697;"	d
ADC_GC3_GAIN16_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	698;"	d
ADC_GC3_GAIN17	.\Static_Code\IO_Map\MC56F82748.h	702;"	d
ADC_GC3_GAIN17_MASK	.\Static_Code\IO_Map\MC56F82748.h	700;"	d
ADC_GC3_GAIN17_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	701;"	d
ADC_GC3_GAIN18	.\Static_Code\IO_Map\MC56F82748.h	705;"	d
ADC_GC3_GAIN18_MASK	.\Static_Code\IO_Map\MC56F82748.h	703;"	d
ADC_GC3_GAIN18_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	704;"	d
ADC_GC3_GAIN19	.\Static_Code\IO_Map\MC56F82748.h	708;"	d
ADC_GC3_GAIN19_MASK	.\Static_Code\IO_Map\MC56F82748.h	706;"	d
ADC_GC3_GAIN19_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	707;"	d
ADC_GC3_REG	.\Static_Code\IO_Map\MC56F82748.h	310;"	d
ADC_HILIM	.\Static_Code\IO_Map\MC56F82748.h	857;"	d
ADC_HILIM0	.\Static_Code\IO_Map\MC56F82748.h	787;"	d
ADC_HILIM1	.\Static_Code\IO_Map\MC56F82748.h	788;"	d
ADC_HILIM10	.\Static_Code\IO_Map\MC56F82748.h	797;"	d
ADC_HILIM11	.\Static_Code\IO_Map\MC56F82748.h	798;"	d
ADC_HILIM12	.\Static_Code\IO_Map\MC56F82748.h	799;"	d
ADC_HILIM13	.\Static_Code\IO_Map\MC56F82748.h	800;"	d
ADC_HILIM14	.\Static_Code\IO_Map\MC56F82748.h	801;"	d
ADC_HILIM15	.\Static_Code\IO_Map\MC56F82748.h	802;"	d
ADC_HILIM2	.\Static_Code\IO_Map\MC56F82748.h	789;"	d
ADC_HILIM216	.\Static_Code\IO_Map\MC56F82748.h	842;"	d
ADC_HILIM217	.\Static_Code\IO_Map\MC56F82748.h	843;"	d
ADC_HILIM218	.\Static_Code\IO_Map\MC56F82748.h	844;"	d
ADC_HILIM219	.\Static_Code\IO_Map\MC56F82748.h	845;"	d
ADC_HILIM3	.\Static_Code\IO_Map\MC56F82748.h	790;"	d
ADC_HILIM4	.\Static_Code\IO_Map\MC56F82748.h	791;"	d
ADC_HILIM5	.\Static_Code\IO_Map\MC56F82748.h	792;"	d
ADC_HILIM6	.\Static_Code\IO_Map\MC56F82748.h	793;"	d
ADC_HILIM7	.\Static_Code\IO_Map\MC56F82748.h	794;"	d
ADC_HILIM8	.\Static_Code\IO_Map\MC56F82748.h	795;"	d
ADC_HILIM9	.\Static_Code\IO_Map\MC56F82748.h	796;"	d
ADC_HILIMSTAT	.\Static_Code\IO_Map\MC56F82748.h	753;"	d
ADC_HILIMSTAT2	.\Static_Code\IO_Map\MC56F82748.h	832;"	d
ADC_HILIMSTAT2_HLS	.\Static_Code\IO_Map\MC56F82748.h	673;"	d
ADC_HILIMSTAT2_HLS_MASK	.\Static_Code\IO_Map\MC56F82748.h	671;"	d
ADC_HILIMSTAT2_HLS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	672;"	d
ADC_HILIMSTAT2_REG	.\Static_Code\IO_Map\MC56F82748.h	304;"	d
ADC_HILIMSTAT_HLS	.\Static_Code\IO_Map\MC56F82748.h	505;"	d
ADC_HILIMSTAT_HLS_MASK	.\Static_Code\IO_Map\MC56F82748.h	503;"	d
ADC_HILIMSTAT_HLS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	504;"	d
ADC_HILIMSTAT_REG	.\Static_Code\IO_Map\MC56F82748.h	285;"	d
ADC_HILIM_2	.\Static_Code\IO_Map\MC56F82748.h	861;"	d
ADC_HILIM_2_HLMT	.\Static_Code\IO_Map\MC56F82748.h	691;"	d
ADC_HILIM_2_HLMT_MASK	.\Static_Code\IO_Map\MC56F82748.h	689;"	d
ADC_HILIM_2_HLMT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	690;"	d
ADC_HILIM_2_REG	.\Static_Code\IO_Map\MC56F82748.h	308;"	d
ADC_HILIM_HLMT	.\Static_Code\IO_Map\MC56F82748.h	523;"	d
ADC_HILIM_HLMT_MASK	.\Static_Code\IO_Map\MC56F82748.h	521;"	d
ADC_HILIM_HLMT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	522;"	d
ADC_HILIM_REG	.\Static_Code\IO_Map\MC56F82748.h	289;"	d
ADC_Init	.\Static_Code\Peripherals\ADC_Init.c	/^void ADC_Init(void) {$/;"	f
ADC_LOLIM	.\Static_Code\IO_Map\MC56F82748.h	856;"	d
ADC_LOLIM0	.\Static_Code\IO_Map\MC56F82748.h	771;"	d
ADC_LOLIM1	.\Static_Code\IO_Map\MC56F82748.h	772;"	d
ADC_LOLIM10	.\Static_Code\IO_Map\MC56F82748.h	781;"	d
ADC_LOLIM11	.\Static_Code\IO_Map\MC56F82748.h	782;"	d
ADC_LOLIM12	.\Static_Code\IO_Map\MC56F82748.h	783;"	d
ADC_LOLIM13	.\Static_Code\IO_Map\MC56F82748.h	784;"	d
ADC_LOLIM14	.\Static_Code\IO_Map\MC56F82748.h	785;"	d
ADC_LOLIM15	.\Static_Code\IO_Map\MC56F82748.h	786;"	d
ADC_LOLIM2	.\Static_Code\IO_Map\MC56F82748.h	773;"	d
ADC_LOLIM216	.\Static_Code\IO_Map\MC56F82748.h	838;"	d
ADC_LOLIM217	.\Static_Code\IO_Map\MC56F82748.h	839;"	d
ADC_LOLIM218	.\Static_Code\IO_Map\MC56F82748.h	840;"	d
ADC_LOLIM219	.\Static_Code\IO_Map\MC56F82748.h	841;"	d
ADC_LOLIM3	.\Static_Code\IO_Map\MC56F82748.h	774;"	d
ADC_LOLIM4	.\Static_Code\IO_Map\MC56F82748.h	775;"	d
ADC_LOLIM5	.\Static_Code\IO_Map\MC56F82748.h	776;"	d
ADC_LOLIM6	.\Static_Code\IO_Map\MC56F82748.h	777;"	d
ADC_LOLIM7	.\Static_Code\IO_Map\MC56F82748.h	778;"	d
ADC_LOLIM8	.\Static_Code\IO_Map\MC56F82748.h	779;"	d
ADC_LOLIM9	.\Static_Code\IO_Map\MC56F82748.h	780;"	d
ADC_LOLIMSTAT	.\Static_Code\IO_Map\MC56F82748.h	752;"	d
ADC_LOLIMSTAT2	.\Static_Code\IO_Map\MC56F82748.h	831;"	d
ADC_LOLIMSTAT2_LLS	.\Static_Code\IO_Map\MC56F82748.h	669;"	d
ADC_LOLIMSTAT2_LLS_MASK	.\Static_Code\IO_Map\MC56F82748.h	667;"	d
ADC_LOLIMSTAT2_LLS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	668;"	d
ADC_LOLIMSTAT2_REG	.\Static_Code\IO_Map\MC56F82748.h	303;"	d
ADC_LOLIMSTAT_LLS	.\Static_Code\IO_Map\MC56F82748.h	501;"	d
ADC_LOLIMSTAT_LLS_MASK	.\Static_Code\IO_Map\MC56F82748.h	499;"	d
ADC_LOLIMSTAT_LLS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	500;"	d
ADC_LOLIMSTAT_REG	.\Static_Code\IO_Map\MC56F82748.h	284;"	d
ADC_LOLIM_2	.\Static_Code\IO_Map\MC56F82748.h	860;"	d
ADC_LOLIM_2_LLMT	.\Static_Code\IO_Map\MC56F82748.h	687;"	d
ADC_LOLIM_2_LLMT_MASK	.\Static_Code\IO_Map\MC56F82748.h	685;"	d
ADC_LOLIM_2_LLMT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	686;"	d
ADC_LOLIM_2_REG	.\Static_Code\IO_Map\MC56F82748.h	307;"	d
ADC_LOLIM_LLMT	.\Static_Code\IO_Map\MC56F82748.h	519;"	d
ADC_LOLIM_LLMT_MASK	.\Static_Code\IO_Map\MC56F82748.h	517;"	d
ADC_LOLIM_LLMT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	518;"	d
ADC_LOLIM_REG	.\Static_Code\IO_Map\MC56F82748.h	288;"	d
ADC_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct ADC_MemMap {$/;"	s
ADC_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *ADC_MemMapPtr;$/;"	t
ADC_OFFST	.\Static_Code\IO_Map\MC56F82748.h	858;"	d
ADC_OFFST0	.\Static_Code\IO_Map\MC56F82748.h	803;"	d
ADC_OFFST1	.\Static_Code\IO_Map\MC56F82748.h	804;"	d
ADC_OFFST10	.\Static_Code\IO_Map\MC56F82748.h	813;"	d
ADC_OFFST11	.\Static_Code\IO_Map\MC56F82748.h	814;"	d
ADC_OFFST12	.\Static_Code\IO_Map\MC56F82748.h	815;"	d
ADC_OFFST13	.\Static_Code\IO_Map\MC56F82748.h	816;"	d
ADC_OFFST14	.\Static_Code\IO_Map\MC56F82748.h	817;"	d
ADC_OFFST15	.\Static_Code\IO_Map\MC56F82748.h	818;"	d
ADC_OFFST2	.\Static_Code\IO_Map\MC56F82748.h	805;"	d
ADC_OFFST216	.\Static_Code\IO_Map\MC56F82748.h	846;"	d
ADC_OFFST217	.\Static_Code\IO_Map\MC56F82748.h	847;"	d
ADC_OFFST218	.\Static_Code\IO_Map\MC56F82748.h	848;"	d
ADC_OFFST219	.\Static_Code\IO_Map\MC56F82748.h	849;"	d
ADC_OFFST3	.\Static_Code\IO_Map\MC56F82748.h	806;"	d
ADC_OFFST4	.\Static_Code\IO_Map\MC56F82748.h	807;"	d
ADC_OFFST5	.\Static_Code\IO_Map\MC56F82748.h	808;"	d
ADC_OFFST6	.\Static_Code\IO_Map\MC56F82748.h	809;"	d
ADC_OFFST7	.\Static_Code\IO_Map\MC56F82748.h	810;"	d
ADC_OFFST8	.\Static_Code\IO_Map\MC56F82748.h	811;"	d
ADC_OFFST9	.\Static_Code\IO_Map\MC56F82748.h	812;"	d
ADC_OFFST_2	.\Static_Code\IO_Map\MC56F82748.h	862;"	d
ADC_OFFST_2_OFFSET	.\Static_Code\IO_Map\MC56F82748.h	695;"	d
ADC_OFFST_2_OFFSET_MASK	.\Static_Code\IO_Map\MC56F82748.h	693;"	d
ADC_OFFST_2_OFFSET_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	694;"	d
ADC_OFFST_2_REG	.\Static_Code\IO_Map\MC56F82748.h	309;"	d
ADC_OFFST_OFFSET	.\Static_Code\IO_Map\MC56F82748.h	527;"	d
ADC_OFFST_OFFSET_MASK	.\Static_Code\IO_Map\MC56F82748.h	525;"	d
ADC_OFFST_OFFSET_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	526;"	d
ADC_OFFST_REG	.\Static_Code\IO_Map\MC56F82748.h	290;"	d
ADC_PWR	.\Static_Code\IO_Map\MC56F82748.h	819;"	d
ADC_PWR2	.\Static_Code\IO_Map\MC56F82748.h	824;"	d
ADC_PWR2_DIV1	.\Static_Code\IO_Map\MC56F82748.h	610;"	d
ADC_PWR2_DIV1_MASK	.\Static_Code\IO_Map\MC56F82748.h	608;"	d
ADC_PWR2_DIV1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	609;"	d
ADC_PWR2_REG	.\Static_Code\IO_Map\MC56F82748.h	296;"	d
ADC_PWR_APD_MASK	.\Static_Code\IO_Map\MC56F82748.h	533;"	d
ADC_PWR_APD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	534;"	d
ADC_PWR_ASB_MASK	.\Static_Code\IO_Map\MC56F82748.h	542;"	d
ADC_PWR_ASB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	543;"	d
ADC_PWR_PD0_MASK	.\Static_Code\IO_Map\MC56F82748.h	529;"	d
ADC_PWR_PD0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	530;"	d
ADC_PWR_PD1_MASK	.\Static_Code\IO_Map\MC56F82748.h	531;"	d
ADC_PWR_PD1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	532;"	d
ADC_PWR_PSTS0_MASK	.\Static_Code\IO_Map\MC56F82748.h	538;"	d
ADC_PWR_PSTS0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	539;"	d
ADC_PWR_PSTS1_MASK	.\Static_Code\IO_Map\MC56F82748.h	540;"	d
ADC_PWR_PSTS1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	541;"	d
ADC_PWR_PUDELAY	.\Static_Code\IO_Map\MC56F82748.h	537;"	d
ADC_PWR_PUDELAY_MASK	.\Static_Code\IO_Map\MC56F82748.h	535;"	d
ADC_PWR_PUDELAY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	536;"	d
ADC_PWR_REG	.\Static_Code\IO_Map\MC56F82748.h	291;"	d
ADC_RDY	.\Static_Code\IO_Map\MC56F82748.h	751;"	d
ADC_RDY2	.\Static_Code\IO_Map\MC56F82748.h	830;"	d
ADC_RDY2_RDY	.\Static_Code\IO_Map\MC56F82748.h	665;"	d
ADC_RDY2_RDY_MASK	.\Static_Code\IO_Map\MC56F82748.h	663;"	d
ADC_RDY2_RDY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	664;"	d
ADC_RDY2_REG	.\Static_Code\IO_Map\MC56F82748.h	302;"	d
ADC_RDY_RDY	.\Static_Code\IO_Map\MC56F82748.h	497;"	d
ADC_RDY_RDY_MASK	.\Static_Code\IO_Map\MC56F82748.h	495;"	d
ADC_RDY_RDY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	496;"	d
ADC_RDY_REG	.\Static_Code\IO_Map\MC56F82748.h	283;"	d
ADC_RSLT	.\Static_Code\IO_Map\MC56F82748.h	855;"	d
ADC_RSLT0	.\Static_Code\IO_Map\MC56F82748.h	755;"	d
ADC_RSLT1	.\Static_Code\IO_Map\MC56F82748.h	756;"	d
ADC_RSLT10	.\Static_Code\IO_Map\MC56F82748.h	765;"	d
ADC_RSLT11	.\Static_Code\IO_Map\MC56F82748.h	766;"	d
ADC_RSLT12	.\Static_Code\IO_Map\MC56F82748.h	767;"	d
ADC_RSLT13	.\Static_Code\IO_Map\MC56F82748.h	768;"	d
ADC_RSLT14	.\Static_Code\IO_Map\MC56F82748.h	769;"	d
ADC_RSLT15	.\Static_Code\IO_Map\MC56F82748.h	770;"	d
ADC_RSLT2	.\Static_Code\IO_Map\MC56F82748.h	757;"	d
ADC_RSLT216	.\Static_Code\IO_Map\MC56F82748.h	834;"	d
ADC_RSLT217	.\Static_Code\IO_Map\MC56F82748.h	835;"	d
ADC_RSLT218	.\Static_Code\IO_Map\MC56F82748.h	836;"	d
ADC_RSLT219	.\Static_Code\IO_Map\MC56F82748.h	837;"	d
ADC_RSLT3	.\Static_Code\IO_Map\MC56F82748.h	758;"	d
ADC_RSLT4	.\Static_Code\IO_Map\MC56F82748.h	759;"	d
ADC_RSLT5	.\Static_Code\IO_Map\MC56F82748.h	760;"	d
ADC_RSLT6	.\Static_Code\IO_Map\MC56F82748.h	761;"	d
ADC_RSLT7	.\Static_Code\IO_Map\MC56F82748.h	762;"	d
ADC_RSLT8	.\Static_Code\IO_Map\MC56F82748.h	763;"	d
ADC_RSLT9	.\Static_Code\IO_Map\MC56F82748.h	764;"	d
ADC_RSLT_2	.\Static_Code\IO_Map\MC56F82748.h	859;"	d
ADC_RSLT_2_REG	.\Static_Code\IO_Map\MC56F82748.h	306;"	d
ADC_RSLT_2_RSLT	.\Static_Code\IO_Map\MC56F82748.h	681;"	d
ADC_RSLT_2_RSLT_MASK	.\Static_Code\IO_Map\MC56F82748.h	679;"	d
ADC_RSLT_2_RSLT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	680;"	d
ADC_RSLT_2_SEXT_MASK	.\Static_Code\IO_Map\MC56F82748.h	682;"	d
ADC_RSLT_2_SEXT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	683;"	d
ADC_RSLT_REG	.\Static_Code\IO_Map\MC56F82748.h	287;"	d
ADC_RSLT_RSLT	.\Static_Code\IO_Map\MC56F82748.h	513;"	d
ADC_RSLT_RSLT_MASK	.\Static_Code\IO_Map\MC56F82748.h	511;"	d
ADC_RSLT_RSLT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	512;"	d
ADC_RSLT_SEXT_MASK	.\Static_Code\IO_Map\MC56F82748.h	514;"	d
ADC_RSLT_SEXT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	515;"	d
ADC_SCHLTEN	.\Static_Code\IO_Map\MC56F82748.h	826;"	d
ADC_SCHLTEN2	.\Static_Code\IO_Map\MC56F82748.h	852;"	d
ADC_SCHLTEN2_REG	.\Static_Code\IO_Map\MC56F82748.h	312;"	d
ADC_SCHLTEN2_SCHLTEN	.\Static_Code\IO_Map\MC56F82748.h	716;"	d
ADC_SCHLTEN2_SCHLTEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	714;"	d
ADC_SCHLTEN2_SCHLTEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	715;"	d
ADC_SCHLTEN_REG	.\Static_Code\IO_Map\MC56F82748.h	298;"	d
ADC_SCHLTEN_SCHLTEN	.\Static_Code\IO_Map\MC56F82748.h	623;"	d
ADC_SCHLTEN_SCHLTEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	621;"	d
ADC_SCHLTEN_SCHLTEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	622;"	d
ADC_SCTRL	.\Static_Code\IO_Map\MC56F82748.h	823;"	d
ADC_SCTRL2	.\Static_Code\IO_Map\MC56F82748.h	851;"	d
ADC_SCTRL2_REG	.\Static_Code\IO_Map\MC56F82748.h	311;"	d
ADC_SCTRL2_SC	.\Static_Code\IO_Map\MC56F82748.h	712;"	d
ADC_SCTRL2_SC_MASK	.\Static_Code\IO_Map\MC56F82748.h	710;"	d
ADC_SCTRL2_SC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	711;"	d
ADC_SCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	295;"	d
ADC_SCTRL_SC	.\Static_Code\IO_Map\MC56F82748.h	606;"	d
ADC_SCTRL_SC_MASK	.\Static_Code\IO_Map\MC56F82748.h	604;"	d
ADC_SCTRL_SC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	605;"	d
ADC_SDIS	.\Static_Code\IO_Map\MC56F82748.h	749;"	d
ADC_SDIS2	.\Static_Code\IO_Map\MC56F82748.h	829;"	d
ADC_SDIS2_DS	.\Static_Code\IO_Map\MC56F82748.h	661;"	d
ADC_SDIS2_DS_MASK	.\Static_Code\IO_Map\MC56F82748.h	659;"	d
ADC_SDIS2_DS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	660;"	d
ADC_SDIS2_REG	.\Static_Code\IO_Map\MC56F82748.h	301;"	d
ADC_SDIS_DS	.\Static_Code\IO_Map\MC56F82748.h	475;"	d
ADC_SDIS_DS_MASK	.\Static_Code\IO_Map\MC56F82748.h	473;"	d
ADC_SDIS_DS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	474;"	d
ADC_SDIS_REG	.\Static_Code\IO_Map\MC56F82748.h	281;"	d
ADC_STAT	.\Static_Code\IO_Map\MC56F82748.h	750;"	d
ADC_STAT_CIP0_MASK	.\Static_Code\IO_Map\MC56F82748.h	492;"	d
ADC_STAT_CIP0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	493;"	d
ADC_STAT_CIP1_MASK	.\Static_Code\IO_Map\MC56F82748.h	490;"	d
ADC_STAT_CIP1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	491;"	d
ADC_STAT_EOSI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	486;"	d
ADC_STAT_EOSI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	487;"	d
ADC_STAT_EOSI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	488;"	d
ADC_STAT_EOSI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	489;"	d
ADC_STAT_HLMTI_MASK	.\Static_Code\IO_Map\MC56F82748.h	480;"	d
ADC_STAT_HLMTI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	481;"	d
ADC_STAT_LLMTI_MASK	.\Static_Code\IO_Map\MC56F82748.h	482;"	d
ADC_STAT_LLMTI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	483;"	d
ADC_STAT_REG	.\Static_Code\IO_Map\MC56F82748.h	282;"	d
ADC_STAT_UNDEFINED	.\Static_Code\IO_Map\MC56F82748.h	479;"	d
ADC_STAT_UNDEFINED_MASK	.\Static_Code\IO_Map\MC56F82748.h	477;"	d
ADC_STAT_UNDEFINED_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	478;"	d
ADC_STAT_ZCI_MASK	.\Static_Code\IO_Map\MC56F82748.h	484;"	d
ADC_STAT_ZCI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	485;"	d
ADC_ZXCTRL1	.\Static_Code\IO_Map\MC56F82748.h	743;"	d
ADC_ZXCTRL1_REG	.\Static_Code\IO_Map\MC56F82748.h	275;"	d
ADC_ZXCTRL1_ZCE0	.\Static_Code\IO_Map\MC56F82748.h	373;"	d
ADC_ZXCTRL1_ZCE0_MASK	.\Static_Code\IO_Map\MC56F82748.h	371;"	d
ADC_ZXCTRL1_ZCE0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	372;"	d
ADC_ZXCTRL1_ZCE1	.\Static_Code\IO_Map\MC56F82748.h	376;"	d
ADC_ZXCTRL1_ZCE1_MASK	.\Static_Code\IO_Map\MC56F82748.h	374;"	d
ADC_ZXCTRL1_ZCE1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	375;"	d
ADC_ZXCTRL1_ZCE2	.\Static_Code\IO_Map\MC56F82748.h	379;"	d
ADC_ZXCTRL1_ZCE2_MASK	.\Static_Code\IO_Map\MC56F82748.h	377;"	d
ADC_ZXCTRL1_ZCE2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	378;"	d
ADC_ZXCTRL1_ZCE3	.\Static_Code\IO_Map\MC56F82748.h	382;"	d
ADC_ZXCTRL1_ZCE3_MASK	.\Static_Code\IO_Map\MC56F82748.h	380;"	d
ADC_ZXCTRL1_ZCE3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	381;"	d
ADC_ZXCTRL1_ZCE4	.\Static_Code\IO_Map\MC56F82748.h	385;"	d
ADC_ZXCTRL1_ZCE4_MASK	.\Static_Code\IO_Map\MC56F82748.h	383;"	d
ADC_ZXCTRL1_ZCE4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	384;"	d
ADC_ZXCTRL1_ZCE5	.\Static_Code\IO_Map\MC56F82748.h	388;"	d
ADC_ZXCTRL1_ZCE5_MASK	.\Static_Code\IO_Map\MC56F82748.h	386;"	d
ADC_ZXCTRL1_ZCE5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	387;"	d
ADC_ZXCTRL1_ZCE6	.\Static_Code\IO_Map\MC56F82748.h	391;"	d
ADC_ZXCTRL1_ZCE6_MASK	.\Static_Code\IO_Map\MC56F82748.h	389;"	d
ADC_ZXCTRL1_ZCE6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	390;"	d
ADC_ZXCTRL1_ZCE7	.\Static_Code\IO_Map\MC56F82748.h	394;"	d
ADC_ZXCTRL1_ZCE7_MASK	.\Static_Code\IO_Map\MC56F82748.h	392;"	d
ADC_ZXCTRL1_ZCE7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	393;"	d
ADC_ZXCTRL2	.\Static_Code\IO_Map\MC56F82748.h	744;"	d
ADC_ZXCTRL2_REG	.\Static_Code\IO_Map\MC56F82748.h	276;"	d
ADC_ZXCTRL2_ZCE10	.\Static_Code\IO_Map\MC56F82748.h	404;"	d
ADC_ZXCTRL2_ZCE10_MASK	.\Static_Code\IO_Map\MC56F82748.h	402;"	d
ADC_ZXCTRL2_ZCE10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	403;"	d
ADC_ZXCTRL2_ZCE11	.\Static_Code\IO_Map\MC56F82748.h	407;"	d
ADC_ZXCTRL2_ZCE11_MASK	.\Static_Code\IO_Map\MC56F82748.h	405;"	d
ADC_ZXCTRL2_ZCE11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	406;"	d
ADC_ZXCTRL2_ZCE12	.\Static_Code\IO_Map\MC56F82748.h	410;"	d
ADC_ZXCTRL2_ZCE12_MASK	.\Static_Code\IO_Map\MC56F82748.h	408;"	d
ADC_ZXCTRL2_ZCE12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	409;"	d
ADC_ZXCTRL2_ZCE13	.\Static_Code\IO_Map\MC56F82748.h	413;"	d
ADC_ZXCTRL2_ZCE13_MASK	.\Static_Code\IO_Map\MC56F82748.h	411;"	d
ADC_ZXCTRL2_ZCE13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	412;"	d
ADC_ZXCTRL2_ZCE14	.\Static_Code\IO_Map\MC56F82748.h	416;"	d
ADC_ZXCTRL2_ZCE14_MASK	.\Static_Code\IO_Map\MC56F82748.h	414;"	d
ADC_ZXCTRL2_ZCE14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	415;"	d
ADC_ZXCTRL2_ZCE15	.\Static_Code\IO_Map\MC56F82748.h	419;"	d
ADC_ZXCTRL2_ZCE15_MASK	.\Static_Code\IO_Map\MC56F82748.h	417;"	d
ADC_ZXCTRL2_ZCE15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	418;"	d
ADC_ZXCTRL2_ZCE8	.\Static_Code\IO_Map\MC56F82748.h	398;"	d
ADC_ZXCTRL2_ZCE8_MASK	.\Static_Code\IO_Map\MC56F82748.h	396;"	d
ADC_ZXCTRL2_ZCE8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	397;"	d
ADC_ZXCTRL2_ZCE9	.\Static_Code\IO_Map\MC56F82748.h	401;"	d
ADC_ZXCTRL2_ZCE9_MASK	.\Static_Code\IO_Map\MC56F82748.h	399;"	d
ADC_ZXCTRL2_ZCE9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	400;"	d
ADC_ZXCTRL3	.\Static_Code\IO_Map\MC56F82748.h	827;"	d
ADC_ZXCTRL3_REG	.\Static_Code\IO_Map\MC56F82748.h	299;"	d
ADC_ZXCTRL3_ZCE16	.\Static_Code\IO_Map\MC56F82748.h	627;"	d
ADC_ZXCTRL3_ZCE16_MASK	.\Static_Code\IO_Map\MC56F82748.h	625;"	d
ADC_ZXCTRL3_ZCE16_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	626;"	d
ADC_ZXCTRL3_ZCE17	.\Static_Code\IO_Map\MC56F82748.h	630;"	d
ADC_ZXCTRL3_ZCE17_MASK	.\Static_Code\IO_Map\MC56F82748.h	628;"	d
ADC_ZXCTRL3_ZCE17_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	629;"	d
ADC_ZXCTRL3_ZCE18	.\Static_Code\IO_Map\MC56F82748.h	633;"	d
ADC_ZXCTRL3_ZCE18_MASK	.\Static_Code\IO_Map\MC56F82748.h	631;"	d
ADC_ZXCTRL3_ZCE18_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	632;"	d
ADC_ZXCTRL3_ZCE19	.\Static_Code\IO_Map\MC56F82748.h	636;"	d
ADC_ZXCTRL3_ZCE19_MASK	.\Static_Code\IO_Map\MC56F82748.h	634;"	d
ADC_ZXCTRL3_ZCE19_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	635;"	d
ADC_ZXSTAT	.\Static_Code\IO_Map\MC56F82748.h	754;"	d
ADC_ZXSTAT2	.\Static_Code\IO_Map\MC56F82748.h	833;"	d
ADC_ZXSTAT2_REG	.\Static_Code\IO_Map\MC56F82748.h	305;"	d
ADC_ZXSTAT2_ZCS	.\Static_Code\IO_Map\MC56F82748.h	677;"	d
ADC_ZXSTAT2_ZCS_MASK	.\Static_Code\IO_Map\MC56F82748.h	675;"	d
ADC_ZXSTAT2_ZCS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	676;"	d
ADC_ZXSTAT_REG	.\Static_Code\IO_Map\MC56F82748.h	286;"	d
ADC_ZXSTAT_ZCS	.\Static_Code\IO_Map\MC56F82748.h	509;"	d
ADC_ZXSTAT_ZCS_MASK	.\Static_Code\IO_Map\MC56F82748.h	507;"	d
ADC_ZXSTAT_ZCS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	508;"	d
AOI_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	977;"	d
AOI_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	979;"	d
AOI_BFCRT01	.\Static_Code\IO_Map\MC56F82748.h	1003;"	d
AOI_BFCRT010	.\Static_Code\IO_Map\MC56F82748.h	993;"	d
AOI_BFCRT011	.\Static_Code\IO_Map\MC56F82748.h	995;"	d
AOI_BFCRT012	.\Static_Code\IO_Map\MC56F82748.h	997;"	d
AOI_BFCRT013	.\Static_Code\IO_Map\MC56F82748.h	999;"	d
AOI_BFCRT01_PT0_AC	.\Static_Code\IO_Map\MC56F82748.h	943;"	d
AOI_BFCRT01_PT0_AC_MASK	.\Static_Code\IO_Map\MC56F82748.h	941;"	d
AOI_BFCRT01_PT0_AC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	942;"	d
AOI_BFCRT01_PT0_BC	.\Static_Code\IO_Map\MC56F82748.h	940;"	d
AOI_BFCRT01_PT0_BC_MASK	.\Static_Code\IO_Map\MC56F82748.h	938;"	d
AOI_BFCRT01_PT0_BC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	939;"	d
AOI_BFCRT01_PT0_CC	.\Static_Code\IO_Map\MC56F82748.h	937;"	d
AOI_BFCRT01_PT0_CC_MASK	.\Static_Code\IO_Map\MC56F82748.h	935;"	d
AOI_BFCRT01_PT0_CC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	936;"	d
AOI_BFCRT01_PT0_DC	.\Static_Code\IO_Map\MC56F82748.h	934;"	d
AOI_BFCRT01_PT0_DC_MASK	.\Static_Code\IO_Map\MC56F82748.h	932;"	d
AOI_BFCRT01_PT0_DC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	933;"	d
AOI_BFCRT01_PT1_AC	.\Static_Code\IO_Map\MC56F82748.h	931;"	d
AOI_BFCRT01_PT1_AC_MASK	.\Static_Code\IO_Map\MC56F82748.h	929;"	d
AOI_BFCRT01_PT1_AC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	930;"	d
AOI_BFCRT01_PT1_BC	.\Static_Code\IO_Map\MC56F82748.h	928;"	d
AOI_BFCRT01_PT1_BC_MASK	.\Static_Code\IO_Map\MC56F82748.h	926;"	d
AOI_BFCRT01_PT1_BC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	927;"	d
AOI_BFCRT01_PT1_CC	.\Static_Code\IO_Map\MC56F82748.h	925;"	d
AOI_BFCRT01_PT1_CC_MASK	.\Static_Code\IO_Map\MC56F82748.h	923;"	d
AOI_BFCRT01_PT1_CC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	924;"	d
AOI_BFCRT01_PT1_DC	.\Static_Code\IO_Map\MC56F82748.h	922;"	d
AOI_BFCRT01_PT1_DC_MASK	.\Static_Code\IO_Map\MC56F82748.h	920;"	d
AOI_BFCRT01_PT1_DC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	921;"	d
AOI_BFCRT01_REG	.\Static_Code\IO_Map\MC56F82748.h	902;"	d
AOI_BFCRT23	.\Static_Code\IO_Map\MC56F82748.h	1004;"	d
AOI_BFCRT230	.\Static_Code\IO_Map\MC56F82748.h	994;"	d
AOI_BFCRT231	.\Static_Code\IO_Map\MC56F82748.h	996;"	d
AOI_BFCRT232	.\Static_Code\IO_Map\MC56F82748.h	998;"	d
AOI_BFCRT233	.\Static_Code\IO_Map\MC56F82748.h	1000;"	d
AOI_BFCRT23_PT2_AC	.\Static_Code\IO_Map\MC56F82748.h	968;"	d
AOI_BFCRT23_PT2_AC_MASK	.\Static_Code\IO_Map\MC56F82748.h	966;"	d
AOI_BFCRT23_PT2_AC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	967;"	d
AOI_BFCRT23_PT2_BC	.\Static_Code\IO_Map\MC56F82748.h	965;"	d
AOI_BFCRT23_PT2_BC_MASK	.\Static_Code\IO_Map\MC56F82748.h	963;"	d
AOI_BFCRT23_PT2_BC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	964;"	d
AOI_BFCRT23_PT2_CC	.\Static_Code\IO_Map\MC56F82748.h	962;"	d
AOI_BFCRT23_PT2_CC_MASK	.\Static_Code\IO_Map\MC56F82748.h	960;"	d
AOI_BFCRT23_PT2_CC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	961;"	d
AOI_BFCRT23_PT2_DC	.\Static_Code\IO_Map\MC56F82748.h	959;"	d
AOI_BFCRT23_PT2_DC_MASK	.\Static_Code\IO_Map\MC56F82748.h	957;"	d
AOI_BFCRT23_PT2_DC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	958;"	d
AOI_BFCRT23_PT3_AC	.\Static_Code\IO_Map\MC56F82748.h	956;"	d
AOI_BFCRT23_PT3_AC_MASK	.\Static_Code\IO_Map\MC56F82748.h	954;"	d
AOI_BFCRT23_PT3_AC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	955;"	d
AOI_BFCRT23_PT3_BC	.\Static_Code\IO_Map\MC56F82748.h	953;"	d
AOI_BFCRT23_PT3_BC_MASK	.\Static_Code\IO_Map\MC56F82748.h	951;"	d
AOI_BFCRT23_PT3_BC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	952;"	d
AOI_BFCRT23_PT3_CC	.\Static_Code\IO_Map\MC56F82748.h	950;"	d
AOI_BFCRT23_PT3_CC_MASK	.\Static_Code\IO_Map\MC56F82748.h	948;"	d
AOI_BFCRT23_PT3_CC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	949;"	d
AOI_BFCRT23_PT3_DC	.\Static_Code\IO_Map\MC56F82748.h	947;"	d
AOI_BFCRT23_PT3_DC_MASK	.\Static_Code\IO_Map\MC56F82748.h	945;"	d
AOI_BFCRT23_PT3_DC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	946;"	d
AOI_BFCRT23_REG	.\Static_Code\IO_Map\MC56F82748.h	903;"	d
AOI_Init	.\Static_Code\Peripherals\AOI_Init.c	/^void AOI_Init(void) {$/;"	f
AOI_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct AOI_MemMap {$/;"	s
AOI_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *AOI_MemMapPtr;$/;"	t
AOI_PDD_Complement	.\Static_Code\PDD\AOI_PDD.h	43;"	d
AOI_PDD_GetBooleanFunctionTerm0And1ForEvent	.\Static_Code\PDD\AOI_PDD.h	652;"	d
AOI_PDD_GetBooleanFunctionTerm2And3ForEvent	.\Static_Code\PDD\AOI_PDD.h	673;"	d
AOI_PDD_GetFunctionTerm0A	.\Static_Code\PDD\AOI_PDD.h	222;"	d
AOI_PDD_GetFunctionTerm0B	.\Static_Code\PDD\AOI_PDD.h	246;"	d
AOI_PDD_GetFunctionTerm0C	.\Static_Code\PDD\AOI_PDD.h	270;"	d
AOI_PDD_GetFunctionTerm0D	.\Static_Code\PDD\AOI_PDD.h	294;"	d
AOI_PDD_GetFunctionTerm1A	.\Static_Code\PDD\AOI_PDD.h	318;"	d
AOI_PDD_GetFunctionTerm1B	.\Static_Code\PDD\AOI_PDD.h	342;"	d
AOI_PDD_GetFunctionTerm1C	.\Static_Code\PDD\AOI_PDD.h	366;"	d
AOI_PDD_GetFunctionTerm1D	.\Static_Code\PDD\AOI_PDD.h	390;"	d
AOI_PDD_GetFunctionTerm2A	.\Static_Code\PDD\AOI_PDD.h	412;"	d
AOI_PDD_GetFunctionTerm2B	.\Static_Code\PDD\AOI_PDD.h	436;"	d
AOI_PDD_GetFunctionTerm2C	.\Static_Code\PDD\AOI_PDD.h	460;"	d
AOI_PDD_GetFunctionTerm2D	.\Static_Code\PDD\AOI_PDD.h	484;"	d
AOI_PDD_GetFunctionTerm3A	.\Static_Code\PDD\AOI_PDD.h	508;"	d
AOI_PDD_GetFunctionTerm3B	.\Static_Code\PDD\AOI_PDD.h	532;"	d
AOI_PDD_GetFunctionTerm3C	.\Static_Code\PDD\AOI_PDD.h	556;"	d
AOI_PDD_GetFunctionTerm3D	.\Static_Code\PDD\AOI_PDD.h	580;"	d
AOI_PDD_H_	.\Static_Code\PDD\AOI_PDD.h	9;"	d
AOI_PDD_One	.\Static_Code\PDD\AOI_PDD.h	44;"	d
AOI_PDD_Pass	.\Static_Code\PDD\AOI_PDD.h	42;"	d
AOI_PDD_ReadFunction0Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	853;"	d
AOI_PDD_ReadFunction0Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	933;"	d
AOI_PDD_ReadFunction1Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	873;"	d
AOI_PDD_ReadFunction1Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	953;"	d
AOI_PDD_ReadFunction2Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	893;"	d
AOI_PDD_ReadFunction2Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	973;"	d
AOI_PDD_ReadFunction3Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	913;"	d
AOI_PDD_ReadFunction3Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	993;"	d
AOI_PDD_SetBooleanFunctionTerm0And1ForEvent	.\Static_Code\PDD\AOI_PDD.h	604;"	d
AOI_PDD_SetBooleanFunctionTerm2And3ForEvent	.\Static_Code\PDD\AOI_PDD.h	628;"	d
AOI_PDD_SetFunctionTerm0	.\Static_Code\PDD\AOI_PDD.h	71;"	d
AOI_PDD_SetFunctionTerm1	.\Static_Code\PDD\AOI_PDD.h	111;"	d
AOI_PDD_SetFunctionTerm2	.\Static_Code\PDD\AOI_PDD.h	151;"	d
AOI_PDD_SetFunctionTerm3	.\Static_Code\PDD\AOI_PDD.h	191;"	d
AOI_PDD_WriteFunction0Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	693;"	d
AOI_PDD_WriteFunction0Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	773;"	d
AOI_PDD_WriteFunction1Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	713;"	d
AOI_PDD_WriteFunction1Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	793;"	d
AOI_PDD_WriteFunction2Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	733;"	d
AOI_PDD_WriteFunction2Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	813;"	d
AOI_PDD_WriteFunction3Term0And1ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	753;"	d
AOI_PDD_WriteFunction3Term2And3ConfigurationReg	.\Static_Code\PDD\AOI_PDD.h	833;"	d
AOI_PDD_Zero	.\Static_Code\PDD\AOI_PDD.h	41;"	d
ASM_DEPS	.\FLASH_SDM\sources.mk	/^ASM_DEPS := $/;"	m
ASM_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^ASM_DEPS_OS_FORMAT := $/;"	m
ASM_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^ASM_DEPS_QUOTED := $/;"	m
ASM_SRCS	.\FLASH_SDM\sources.mk	/^ASM_SRCS := $/;"	m
ASM_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^ASM_SRCS_OS_FORMAT := $/;"	m
ASM_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^ASM_SRCS_QUOTED := $/;"	m
ASM_UPPER_DEPS	.\FLASH_SDM\sources.mk	/^ASM_UPPER_DEPS := $/;"	m
ASM_UPPER_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^ASM_UPPER_DEPS_OS_FORMAT := $/;"	m
ASM_UPPER_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^ASM_UPPER_DEPS_QUOTED := $/;"	m
ASM_UPPER_SRCS	.\FLASH_SDM\sources.mk	/^ASM_UPPER_SRCS := $/;"	m
ASM_UPPER_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^ASM_UPPER_SRCS_OS_FORMAT := $/;"	m
ASM_UPPER_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^ASM_UPPER_SRCS_QUOTED := $/;"	m
AckErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t AckErrors;                  \/* ACK error counter *\/$/;"	m	struct:__anon40
ArbitLost	.\Generated_Code\PE_LDD.h	/^  uint32_t ArbitLost;                  \/* Number of lost the bus arbitration. *\/$/;"	m	struct:__anon25
AutomaticWaveform	.\Generated_Code\PE_LDD.h	/^  unsigned int AutomaticWaveform : 1;  \/* Enables automatic waveform generation *\/$/;"	m	struct:__anon30
BFCRT	.\Static_Code\IO_Map\MC56F82748.h	/^  } BFCRT[4];$/;"	m	struct:AOI_MemMap	typeref:struct:AOI_MemMap::__anon47
BFCRT01	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t BFCRT01;                                \/**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x2 *\/$/;"	m	struct:AOI_MemMap::__anon47
BFCRT23	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t BFCRT23;                                \/**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x1, array step: 0x2 *\/$/;"	m	struct:AOI_MemMap::__anon47
BTR0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t BTR0;                                   \/**< MSCAN Bus Timing Register 0, offset: 0x2 *\/$/;"	m	struct:CAN_MemMap
BTR1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t BTR1;                                   \/**< MSCAN Bus Timing Register 1, offset: 0x3 *\/$/;"	m	struct:CAN_MemMap
Bit0Errors	.\Generated_Code\PE_LDD.h	/^  uint32_t Bit0Errors;                 \/* Bit0 error counter *\/$/;"	m	struct:__anon40
Bit1Errors	.\Generated_Code\PE_LDD.h	/^  uint32_t Bit1Errors;                 \/* Bit1 error counter *\/$/;"	m	struct:__anon40
BitIoLdd1_ClrVal	.\Generated_Code\BitIoLdd1.h	211;"	d
BitIoLdd1_ClrVal_METHOD_ENABLED	.\Generated_Code\BitIoLdd1.h	114;"	d
BitIoLdd1_DeviceData	.\Generated_Code\BitIoLdd1.h	108;"	d
BitIoLdd1_GetVal	.\Generated_Code\BitIoLdd1.h	167;"	d
BitIoLdd1_GetVal_METHOD_ENABLED	.\Generated_Code\BitIoLdd1.h	112;"	d
BitIoLdd1_Init	.\Generated_Code\BitIoLdd1.c	/^LDD_TDeviceData* BitIoLdd1_Init(LDD_TUserData *UserDataPtr)$/;"	f
BitIoLdd1_Init_METHOD_ENABLED	.\Generated_Code\BitIoLdd1.h	111;"	d
BitIoLdd1_MODULE_BASE_ADDRESS	.\Generated_Code\BitIoLdd1.h	118;"	d
BitIoLdd1_PORT_MASK	.\Generated_Code\BitIoLdd1.h	119;"	d
BitIoLdd1_PRPH_BASE_ADDRESS	.\Generated_Code\BitIoLdd1.h	105;"	d
BitIoLdd1_PutVal	.\Generated_Code\BitIoLdd1.h	194;"	d
BitIoLdd1_PutVal_METHOD_ENABLED	.\Generated_Code\BitIoLdd1.h	113;"	d
BitIoLdd1_SetVal	.\Generated_Code\BitIoLdd1.h	228;"	d
BitIoLdd1_SetVal_METHOD_ENABLED	.\Generated_Code\BitIoLdd1.h	115;"	d
BitIoLdd1_TDeviceData	.\Generated_Code\BitIoLdd1.c	/^} BitIoLdd1_TDeviceData;               \/* Device data structure type *\/$/;"	t	typeref:struct:__anon1	file:
BitIoLdd1_TDeviceDataPtr	.\Generated_Code\BitIoLdd1.c	/^typedef BitIoLdd1_TDeviceData *BitIoLdd1_TDeviceDataPtr ; \/* Pointer to the device data structure. *\/$/;"	t	file:
BitStuffErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t BitStuffErrors;             \/* Bit stuff error counter *\/$/;"	m	struct:__anon40
BusOffs	.\Generated_Code\PE_LDD.h	/^  uint32_t BusOffs;                    \/* Bus off counter *\/$/;"	m	struct:__anon40
C1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t C1;                                     \/**< I2C Control Register 1, offset: 0x2 *\/$/;"	m	struct:I2C_MemMap
C2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t C2;                                     \/**< I2C Control Register 2, offset: 0x5 *\/$/;"	m	struct:I2C_MemMap
CAL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CAL;                                    \/**< ADC Calibration Register, offset: 0x4F *\/$/;"	m	struct:ADC_MemMap
CALLMAIN	.\Project_Settings\Startup_Code\56F83x_init.asm	/^CALLMAIN:                               ; initialize compiler environment$/;"	l
CAN_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1409;"	d
CAN_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	1411;"	d
CAN_BTR0	.\Static_Code\IO_Map\MC56F82748.h	1427;"	d
CAN_BTR0_BRP	.\Static_Code\IO_Map\MC56F82748.h	1182;"	d
CAN_BTR0_BRP_MASK	.\Static_Code\IO_Map\MC56F82748.h	1180;"	d
CAN_BTR0_BRP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1181;"	d
CAN_BTR0_REG	.\Static_Code\IO_Map\MC56F82748.h	1092;"	d
CAN_BTR0_SJW	.\Static_Code\IO_Map\MC56F82748.h	1185;"	d
CAN_BTR0_SJW_MASK	.\Static_Code\IO_Map\MC56F82748.h	1183;"	d
CAN_BTR0_SJW_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1184;"	d
CAN_BTR1	.\Static_Code\IO_Map\MC56F82748.h	1428;"	d
CAN_BTR1_REG	.\Static_Code\IO_Map\MC56F82748.h	1093;"	d
CAN_BTR1_SAMP_MASK	.\Static_Code\IO_Map\MC56F82748.h	1193;"	d
CAN_BTR1_SAMP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1194;"	d
CAN_BTR1_TSEG1	.\Static_Code\IO_Map\MC56F82748.h	1189;"	d
CAN_BTR1_TSEG1_MASK	.\Static_Code\IO_Map\MC56F82748.h	1187;"	d
CAN_BTR1_TSEG1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1188;"	d
CAN_BTR1_TSEG2	.\Static_Code\IO_Map\MC56F82748.h	1192;"	d
CAN_BTR1_TSEG2_MASK	.\Static_Code\IO_Map\MC56F82748.h	1190;"	d
CAN_BTR1_TSEG2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1191;"	d
CAN_CTL0	.\Static_Code\IO_Map\MC56F82748.h	1425;"	d
CAN_CTL0_CSWAI_MASK	.\Static_Code\IO_Map\MC56F82748.h	1156;"	d
CAN_CTL0_CSWAI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1157;"	d
CAN_CTL0_INITRQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	1146;"	d
CAN_CTL0_INITRQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1147;"	d
CAN_CTL0_REG	.\Static_Code\IO_Map\MC56F82748.h	1090;"	d
CAN_CTL0_RXACT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1158;"	d
CAN_CTL0_RXACT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1159;"	d
CAN_CTL0_RXFRM_MASK	.\Static_Code\IO_Map\MC56F82748.h	1160;"	d
CAN_CTL0_RXFRM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1161;"	d
CAN_CTL0_SLPRQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	1148;"	d
CAN_CTL0_SLPRQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1149;"	d
CAN_CTL0_SYNCH_MASK	.\Static_Code\IO_Map\MC56F82748.h	1154;"	d
CAN_CTL0_SYNCH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1155;"	d
CAN_CTL0_TIME_MASK	.\Static_Code\IO_Map\MC56F82748.h	1152;"	d
CAN_CTL0_TIME_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1153;"	d
CAN_CTL0_WUPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1150;"	d
CAN_CTL0_WUPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1151;"	d
CAN_CTL1	.\Static_Code\IO_Map\MC56F82748.h	1426;"	d
CAN_CTL1_BORM_MASK	.\Static_Code\IO_Map\MC56F82748.h	1169;"	d
CAN_CTL1_BORM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1170;"	d
CAN_CTL1_CANE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1177;"	d
CAN_CTL1_CANE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1178;"	d
CAN_CTL1_CLKSRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	1175;"	d
CAN_CTL1_CLKSRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1176;"	d
CAN_CTL1_INITAK_MASK	.\Static_Code\IO_Map\MC56F82748.h	1163;"	d
CAN_CTL1_INITAK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1164;"	d
CAN_CTL1_LISTEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1171;"	d
CAN_CTL1_LISTEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1172;"	d
CAN_CTL1_LOOPB_MASK	.\Static_Code\IO_Map\MC56F82748.h	1173;"	d
CAN_CTL1_LOOPB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1174;"	d
CAN_CTL1_REG	.\Static_Code\IO_Map\MC56F82748.h	1091;"	d
CAN_CTL1_SLPAK_MASK	.\Static_Code\IO_Map\MC56F82748.h	1165;"	d
CAN_CTL1_SLPAK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1166;"	d
CAN_CTL1_WUPM_MASK	.\Static_Code\IO_Map\MC56F82748.h	1167;"	d
CAN_CTL1_WUPM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1168;"	d
CAN_IDAC	.\Static_Code\IO_Map\MC56F82748.h	1436;"	d
CAN_IDAC_IDAM	.\Static_Code\IO_Map\MC56F82748.h	1251;"	d
CAN_IDAC_IDAM_MASK	.\Static_Code\IO_Map\MC56F82748.h	1249;"	d
CAN_IDAC_IDAM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1250;"	d
CAN_IDAC_IDHIT	.\Static_Code\IO_Map\MC56F82748.h	1248;"	d
CAN_IDAC_IDHIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1246;"	d
CAN_IDAC_IDHIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1247;"	d
CAN_IDAC_REG	.\Static_Code\IO_Map\MC56F82748.h	1101;"	d
CAN_IDAR0	.\Static_Code\IO_Map\MC56F82748.h	1440;"	d
CAN_IDAR1	.\Static_Code\IO_Map\MC56F82748.h	1441;"	d
CAN_IDAR2	.\Static_Code\IO_Map\MC56F82748.h	1442;"	d
CAN_IDAR3	.\Static_Code\IO_Map\MC56F82748.h	1443;"	d
CAN_IDAR4	.\Static_Code\IO_Map\MC56F82748.h	1448;"	d
CAN_IDAR5	.\Static_Code\IO_Map\MC56F82748.h	1449;"	d
CAN_IDAR6	.\Static_Code\IO_Map\MC56F82748.h	1450;"	d
CAN_IDAR7	.\Static_Code\IO_Map\MC56F82748.h	1451;"	d
CAN_IDAR_BANK_1	.\Static_Code\IO_Map\MC56F82748.h	1493;"	d
CAN_IDAR_BANK_1_AC	.\Static_Code\IO_Map\MC56F82748.h	1266;"	d
CAN_IDAR_BANK_1_AC_MASK	.\Static_Code\IO_Map\MC56F82748.h	1264;"	d
CAN_IDAR_BANK_1_AC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1265;"	d
CAN_IDAR_BANK_1_REG	.\Static_Code\IO_Map\MC56F82748.h	1105;"	d
CAN_IDAR_BANK_2	.\Static_Code\IO_Map\MC56F82748.h	1495;"	d
CAN_IDAR_BANK_2_AC	.\Static_Code\IO_Map\MC56F82748.h	1274;"	d
CAN_IDAR_BANK_2_AC_MASK	.\Static_Code\IO_Map\MC56F82748.h	1272;"	d
CAN_IDAR_BANK_2_AC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1273;"	d
CAN_IDAR_BANK_2_REG	.\Static_Code\IO_Map\MC56F82748.h	1107;"	d
CAN_IDMR0	.\Static_Code\IO_Map\MC56F82748.h	1444;"	d
CAN_IDMR1	.\Static_Code\IO_Map\MC56F82748.h	1445;"	d
CAN_IDMR2	.\Static_Code\IO_Map\MC56F82748.h	1446;"	d
CAN_IDMR3	.\Static_Code\IO_Map\MC56F82748.h	1447;"	d
CAN_IDMR4	.\Static_Code\IO_Map\MC56F82748.h	1452;"	d
CAN_IDMR5	.\Static_Code\IO_Map\MC56F82748.h	1453;"	d
CAN_IDMR6	.\Static_Code\IO_Map\MC56F82748.h	1454;"	d
CAN_IDMR7	.\Static_Code\IO_Map\MC56F82748.h	1455;"	d
CAN_IDMR_BANK_1	.\Static_Code\IO_Map\MC56F82748.h	1494;"	d
CAN_IDMR_BANK_1_AM	.\Static_Code\IO_Map\MC56F82748.h	1270;"	d
CAN_IDMR_BANK_1_AM_MASK	.\Static_Code\IO_Map\MC56F82748.h	1268;"	d
CAN_IDMR_BANK_1_AM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1269;"	d
CAN_IDMR_BANK_1_REG	.\Static_Code\IO_Map\MC56F82748.h	1106;"	d
CAN_IDMR_BANK_2	.\Static_Code\IO_Map\MC56F82748.h	1496;"	d
CAN_IDMR_BANK_2_AM	.\Static_Code\IO_Map\MC56F82748.h	1278;"	d
CAN_IDMR_BANK_2_AM_MASK	.\Static_Code\IO_Map\MC56F82748.h	1276;"	d
CAN_IDMR_BANK_2_AM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1277;"	d
CAN_IDMR_BANK_2_REG	.\Static_Code\IO_Map\MC56F82748.h	1108;"	d
CAN_Init	.\Static_Code\Peripherals\CAN_Init.c	/^void CAN_Init(void) {$/;"	f
CAN_MISC	.\Static_Code\IO_Map\MC56F82748.h	1437;"	d
CAN_MISC_BOHOLD_MASK	.\Static_Code\IO_Map\MC56F82748.h	1253;"	d
CAN_MISC_BOHOLD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1254;"	d
CAN_MISC_REG	.\Static_Code\IO_Map\MC56F82748.h	1102;"	d
CAN_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct CAN_MemMap {$/;"	s
CAN_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *CAN_MemMapPtr;$/;"	t
CAN_PDD_BUFFER_ID_EXT	.\Static_Code\PDD\MSCAN_PDD.h	168;"	d
CAN_PDD_BUFFER_ID_STD	.\Static_Code\PDD\MSCAN_PDD.h	169;"	d
CAN_PDD_BUS_CLOCK	.\Static_Code\PDD\MSCAN_PDD.h	57;"	d
CAN_PDD_BusOffRecoveryRequest	.\Static_Code\PDD\MSCAN_PDD.h	1776;"	d
CAN_PDD_ClearReceivedFrameFlag	.\Static_Code\PDD\MSCAN_PDD.h	212;"	d
CAN_PDD_ClearRxStatusInterruptFlags	.\Static_Code\PDD\MSCAN_PDD.h	1005;"	d
CAN_PDD_ClearTxMessageBufferFlagMask	.\Static_Code\PDD\MSCAN_PDD.h	1276;"	d
CAN_PDD_DisableRxInterruptsMask	.\Static_Code\PDD\MSCAN_PDD.h	1146;"	d
CAN_PDD_DisableTxMessageBufferInterruptMask	.\Static_Code\PDD\MSCAN_PDD.h	1394;"	d
CAN_PDD_EIGHT_8BIT_ACCEPTANCE_FILTER	.\Static_Code\PDD\MSCAN_PDD.h	153;"	d
CAN_PDD_ERROR_COUNTER_CHANGE_FLAG	.\Static_Code\PDD\MSCAN_PDD.h	37;"	d
CAN_PDD_ERROR_COUNTER_CHANGE_INT	.\Static_Code\PDD\MSCAN_PDD.h	43;"	d
CAN_PDD_EnableAutomaticBusOffRecovery	.\Static_Code\PDD\MSCAN_PDD.h	605;"	d
CAN_PDD_EnableBusOffRecovery	.\Static_Code\PDD\MSCAN_PDD.h	1802;"	d
CAN_PDD_EnableDevice	.\Static_Code\PDD\MSCAN_PDD.h	493;"	d
CAN_PDD_EnableInitializationMode	.\Static_Code\PDD\MSCAN_PDD.h	419;"	d
CAN_PDD_EnableListenOnlyMode	.\Static_Code\PDD\MSCAN_PDD.h	576;"	d
CAN_PDD_EnableLoopBack	.\Static_Code\PDD\MSCAN_PDD.h	548;"	d
CAN_PDD_EnableOperateInWaitMode	.\Static_Code\PDD\MSCAN_PDD.h	261;"	d
CAN_PDD_EnableRxInterruptsMask	.\Static_Code\PDD\MSCAN_PDD.h	1122;"	d
CAN_PDD_EnableSleepMode	.\Static_Code\PDD\MSCAN_PDD.h	369;"	d
CAN_PDD_EnableTimerSynchronization	.\Static_Code\PDD\MSCAN_PDD.h	313;"	d
CAN_PDD_EnableTxMessageBufferIDExt	.\Static_Code\PDD\MSCAN_PDD.h	3133;"	d
CAN_PDD_EnableTxMessageBufferInterruptMask	.\Static_Code\PDD\MSCAN_PDD.h	1370;"	d
CAN_PDD_EnableTxMessageBufferRTRExtId	.\Static_Code\PDD\MSCAN_PDD.h	3348;"	d
CAN_PDD_EnableTxMessageBufferRTRStdId	.\Static_Code\PDD\MSCAN_PDD.h	3216;"	d
CAN_PDD_EnableTxMessageBufferSRRExtId	.\Static_Code\PDD\MSCAN_PDD.h	3100;"	d
CAN_PDD_EnableWakeUp	.\Static_Code\PDD\MSCAN_PDD.h	341;"	d
CAN_PDD_EnableWakeUpFilter	.\Static_Code\PDD\MSCAN_PDD.h	633;"	d
CAN_PDD_FILTER_CLOSED	.\Static_Code\PDD\MSCAN_PDD.h	154;"	d
CAN_PDD_FILTER_HIT_0	.\Static_Code\PDD\MSCAN_PDD.h	157;"	d
CAN_PDD_FILTER_HIT_1	.\Static_Code\PDD\MSCAN_PDD.h	158;"	d
CAN_PDD_FILTER_HIT_2	.\Static_Code\PDD\MSCAN_PDD.h	159;"	d
CAN_PDD_FILTER_HIT_3	.\Static_Code\PDD\MSCAN_PDD.h	160;"	d
CAN_PDD_FILTER_HIT_4	.\Static_Code\PDD\MSCAN_PDD.h	161;"	d
CAN_PDD_FILTER_HIT_5	.\Static_Code\PDD\MSCAN_PDD.h	162;"	d
CAN_PDD_FILTER_HIT_6	.\Static_Code\PDD\MSCAN_PDD.h	163;"	d
CAN_PDD_FILTER_HIT_7	.\Static_Code\PDD\MSCAN_PDD.h	164;"	d
CAN_PDD_FOUR_16BIT_ACCEPTAN_FILTER	.\Static_Code\PDD\MSCAN_PDD.h	152;"	d
CAN_PDD_GetIdAcceptanceCode1stBank	.\Static_Code\PDD\MSCAN_PDD.h	1962;"	d
CAN_PDD_GetIdAcceptanceCode2ndBank	.\Static_Code\PDD\MSCAN_PDD.h	2213;"	d
CAN_PDD_GetIdAcceptanceHitIndicator	.\Static_Code\PDD\MSCAN_PDD.h	1706;"	d
CAN_PDD_GetIdAcceptanceMask1stBank	.\Static_Code\PDD\MSCAN_PDD.h	2088;"	d
CAN_PDD_GetIdAcceptanceMask2ndBank	.\Static_Code\PDD\MSCAN_PDD.h	2339;"	d
CAN_PDD_GetInitializationModeAcknowledgeFlag	.\Static_Code\PDD\MSCAN_PDD.h	681;"	d
CAN_PDD_GetReceivedFrameFlag	.\Static_Code\PDD\MSCAN_PDD.h	190;"	d
CAN_PDD_GetReceiverActiveStatusFlag	.\Static_Code\PDD\MSCAN_PDD.h	236;"	d
CAN_PDD_GetRxBufferTimeStampValue	.\Static_Code\PDD\MSCAN_PDD.h	3574;"	d
CAN_PDD_GetRxErrorCounter	.\Static_Code\PDD\MSCAN_PDD.h	1873;"	d
CAN_PDD_GetRxMessageBufferData	.\Static_Code\PDD\MSCAN_PDD.h	3429;"	d
CAN_PDD_GetRxMessageBufferDataLength	.\Static_Code\PDD\MSCAN_PDD.h	3502;"	d
CAN_PDD_GetRxMessageBufferID	.\Static_Code\PDD\MSCAN_PDD.h	2469;"	d
CAN_PDD_GetRxMessageBufferIDExt	.\Static_Code\PDD\MSCAN_PDD.h	2653;"	d
CAN_PDD_GetRxMessageBufferRTRExtId	.\Static_Code\PDD\MSCAN_PDD.h	2860;"	d
CAN_PDD_GetRxMessageBufferRTRStdId	.\Static_Code\PDD\MSCAN_PDD.h	2733;"	d
CAN_PDD_GetRxMessageBufferSRRExtId	.\Static_Code\PDD\MSCAN_PDD.h	2624;"	d
CAN_PDD_GetRxStatusBits	.\Static_Code\PDD\MSCAN_PDD.h	1028;"	d
CAN_PDD_GetRxStatusInterruptFlags	.\Static_Code\PDD\MSCAN_PDD.h	981;"	d
CAN_PDD_GetSleepModeAcknoledgeFlag	.\Static_Code\PDD\MSCAN_PDD.h	658;"	d
CAN_PDD_GetSleepModeState	.\Static_Code\PDD\MSCAN_PDD.h	393;"	d
CAN_PDD_GetSynchronizedStatusFlag	.\Static_Code\PDD\MSCAN_PDD.h	287;"	d
CAN_PDD_GetTxBufferTimeStampValue	.\Static_Code\PDD\MSCAN_PDD.h	3874;"	d
CAN_PDD_GetTxErrorCounter	.\Static_Code\PDD\MSCAN_PDD.h	1917;"	d
CAN_PDD_GetTxMessageAbortAcknowledgeMask	.\Static_Code\PDD\MSCAN_PDD.h	1560;"	d
CAN_PDD_GetTxMessageBufferFlagMask	.\Static_Code\PDD\MSCAN_PDD.h	1299;"	d
CAN_PDD_GetTxMessageBufferInterruptMask	.\Static_Code\PDD\MSCAN_PDD.h	1417;"	d
CAN_PDD_GetTxStatusBits	.\Static_Code\PDD\MSCAN_PDD.h	1051;"	d
CAN_PDD_NOT_SYNCHRONIZED	.\Static_Code\PDD\MSCAN_PDD.h	52;"	d
CAN_PDD_ONE_SAMPLE	.\Static_Code\PDD\MSCAN_PDD.h	66;"	d
CAN_PDD_RECEIVING	.\Static_Code\PDD\MSCAN_PDD.h	49;"	d
CAN_PDD_RX_ALL_STATE_INT	.\Static_Code\PDD\MSCAN_PDD.h	113;"	d
CAN_PDD_RX_BUFFER_FULL_FLAG	.\Static_Code\PDD\MSCAN_PDD.h	39;"	d
CAN_PDD_RX_BUFFER_FULL_INT	.\Static_Code\PDD\MSCAN_PDD.h	45;"	d
CAN_PDD_RX_BUFFER_OVERRUN_FLAG	.\Static_Code\PDD\MSCAN_PDD.h	38;"	d
CAN_PDD_RX_BUFFER_OVERRUN_INT	.\Static_Code\PDD\MSCAN_PDD.h	44;"	d
CAN_PDD_RX_BUS_OFF	.\Static_Code\PDD\MSCAN_PDD.h	101;"	d
CAN_PDD_RX_BUS_OFF_INT	.\Static_Code\PDD\MSCAN_PDD.h	111;"	d
CAN_PDD_RX_ERROR	.\Static_Code\PDD\MSCAN_PDD.h	100;"	d
CAN_PDD_RX_OK	.\Static_Code\PDD\MSCAN_PDD.h	98;"	d
CAN_PDD_RX_STATUS_DISABLE_INT	.\Static_Code\PDD\MSCAN_PDD.h	110;"	d
CAN_PDD_RX_TX_ERROR_OR_BUS_OFF_INT	.\Static_Code\PDD\MSCAN_PDD.h	112;"	d
CAN_PDD_RX_WARNING	.\Static_Code\PDD\MSCAN_PDD.h	99;"	d
CAN_PDD_ReadBusTiming0Reg	.\Static_Code\PDD\MSCAN_PDD.h	805;"	d
CAN_PDD_ReadBusTiming1Reg	.\Static_Code\PDD\MSCAN_PDD.h	933;"	d
CAN_PDD_ReadControl0Reg	.\Static_Code\PDD\MSCAN_PDD.h	443;"	d
CAN_PDD_ReadControl1Reg	.\Static_Code\PDD\MSCAN_PDD.h	703;"	d
CAN_PDD_ReadIdAcceptance1stBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2038;"	d
CAN_PDD_ReadIdAcceptance2ndBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2289;"	d
CAN_PDD_ReadIdAcceptanceControlReg	.\Static_Code\PDD\MSCAN_PDD.h	1729;"	d
CAN_PDD_ReadIdMask1stBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2164;"	d
CAN_PDD_ReadIdMask2ndBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2415;"	d
CAN_PDD_ReadMiscellaneousReg	.\Static_Code\PDD\MSCAN_PDD.h	1826;"	d
CAN_PDD_ReadRxBufferDataLengthReg	.\Static_Code\PDD\MSCAN_PDD.h	3525;"	d
CAN_PDD_ReadRxBufferDataSegmentReg	.\Static_Code\PDD\MSCAN_PDD.h	3453;"	d
CAN_PDD_ReadRxBufferExtIdBits14To7Reg	.\Static_Code\PDD\MSCAN_PDD.h	2811;"	d
CAN_PDD_ReadRxBufferExtIdBits20To15Reg	.\Static_Code\PDD\MSCAN_PDD.h	2684;"	d
CAN_PDD_ReadRxBufferExtIdBits28To21Reg	.\Static_Code\PDD\MSCAN_PDD.h	2527;"	d
CAN_PDD_ReadRxBufferExtIdBits6To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	2887;"	d
CAN_PDD_ReadRxBufferStdIdBits10To3Reg	.\Static_Code\PDD\MSCAN_PDD.h	2576;"	d
CAN_PDD_ReadRxBufferStdIdBits2To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	2762;"	d
CAN_PDD_ReadRxBufferTimeStampHighByteReg	.\Static_Code\PDD\MSCAN_PDD.h	3597;"	d
CAN_PDD_ReadRxBufferTimeStampLowByteReg	.\Static_Code\PDD\MSCAN_PDD.h	3620;"	d
CAN_PDD_ReadRxErrorCounterReg	.\Static_Code\PDD\MSCAN_PDD.h	1895;"	d
CAN_PDD_ReadRxFlagReg	.\Static_Code\PDD\MSCAN_PDD.h	1073;"	d
CAN_PDD_ReadRxInterruptEnableReg	.\Static_Code\PDD\MSCAN_PDD.h	1227;"	d
CAN_PDD_ReadTxBufferDataLengthReg	.\Static_Code\PDD\MSCAN_PDD.h	3748;"	d
CAN_PDD_ReadTxBufferDataSegmentReg	.\Static_Code\PDD\MSCAN_PDD.h	3671;"	d
CAN_PDD_ReadTxBufferExtIdBits14To7Reg	.\Static_Code\PDD\MSCAN_PDD.h	3297;"	d
CAN_PDD_ReadTxBufferExtIdBits20To15Reg	.\Static_Code\PDD\MSCAN_PDD.h	3165;"	d
CAN_PDD_ReadTxBufferExtIdBits28To21Reg	.\Static_Code\PDD\MSCAN_PDD.h	3000;"	d
CAN_PDD_ReadTxBufferExtIdBits6To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	3380;"	d
CAN_PDD_ReadTxBufferPriorityReg	.\Static_Code\PDD\MSCAN_PDD.h	3825;"	d
CAN_PDD_ReadTxBufferSelectionReg	.\Static_Code\PDD\MSCAN_PDD.h	1629;"	d
CAN_PDD_ReadTxBufferStdIdBits10To3Reg	.\Static_Code\PDD\MSCAN_PDD.h	3049;"	d
CAN_PDD_ReadTxBufferStdIdBits2To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	3248;"	d
CAN_PDD_ReadTxBufferTimeStampHighByteReg	.\Static_Code\PDD\MSCAN_PDD.h	3897;"	d
CAN_PDD_ReadTxBufferTimeStampLowByteReg	.\Static_Code\PDD\MSCAN_PDD.h	3920;"	d
CAN_PDD_ReadTxErrorCounterReg	.\Static_Code\PDD\MSCAN_PDD.h	1939;"	d
CAN_PDD_ReadTxFlagReg	.\Static_Code\PDD\MSCAN_PDD.h	1321;"	d
CAN_PDD_ReadTxInterruptEnableReg	.\Static_Code\PDD\MSCAN_PDD.h	1440;"	d
CAN_PDD_ReadTxMessageAbortAcknowledgeReg	.\Static_Code\PDD\MSCAN_PDD.h	1583;"	d
CAN_PDD_ReadTxMessageAbortRequestReg	.\Static_Code\PDD\MSCAN_PDD.h	1512;"	d
CAN_PDD_SYNCHRONIZED	.\Static_Code\PDD\MSCAN_PDD.h	53;"	d
CAN_PDD_SYNC_JUMP_WIDTH_1_TQ	.\Static_Code\PDD\MSCAN_PDD.h	60;"	d
CAN_PDD_SYNC_JUMP_WIDTH_2_TQ	.\Static_Code\PDD\MSCAN_PDD.h	61;"	d
CAN_PDD_SYNC_JUMP_WIDTH_3_TQ	.\Static_Code\PDD\MSCAN_PDD.h	62;"	d
CAN_PDD_SYNC_JUMP_WIDTH_4_TQ	.\Static_Code\PDD\MSCAN_PDD.h	63;"	d
CAN_PDD_SelectTxMessageBufferMask	.\Static_Code\PDD\MSCAN_PDD.h	1606;"	d
CAN_PDD_SetBitSampling	.\Static_Code\PDD\MSCAN_PDD.h	855;"	d
CAN_PDD_SetClockSource	.\Static_Code\PDD\MSCAN_PDD.h	520;"	d
CAN_PDD_SetIdAcceptanceCode1stBank	.\Static_Code\PDD\MSCAN_PDD.h	1998;"	d
CAN_PDD_SetIdAcceptanceCode2ndBank	.\Static_Code\PDD\MSCAN_PDD.h	2249;"	d
CAN_PDD_SetIdAcceptanceFilterMode	.\Static_Code\PDD\MSCAN_PDD.h	1678;"	d
CAN_PDD_SetIdAcceptanceMask1stBank	.\Static_Code\PDD\MSCAN_PDD.h	2124;"	d
CAN_PDD_SetIdAcceptanceMask2ndBank	.\Static_Code\PDD\MSCAN_PDD.h	2375;"	d
CAN_PDD_SetPhaseSegment1Value	.\Static_Code\PDD\MSCAN_PDD.h	907;"	d
CAN_PDD_SetPhaseSegment2Value	.\Static_Code\PDD\MSCAN_PDD.h	880;"	d
CAN_PDD_SetPrescalerValue	.\Static_Code\PDD\MSCAN_PDD.h	779;"	d
CAN_PDD_SetRxInterruptFlagStatusChange	.\Static_Code\PDD\MSCAN_PDD.h	1171;"	d
CAN_PDD_SetSyncJumpWidthValue	.\Static_Code\PDD\MSCAN_PDD.h	751;"	d
CAN_PDD_SetTxBufferPriority	.\Static_Code\PDD\MSCAN_PDD.h	3798;"	d
CAN_PDD_SetTxInterruptFlagStatusChange	.\Static_Code\PDD\MSCAN_PDD.h	1200;"	d
CAN_PDD_SetTxMessageBufferData	.\Static_Code\PDD\MSCAN_PDD.h	3644;"	d
CAN_PDD_SetTxMessageBufferDataLength	.\Static_Code\PDD\MSCAN_PDD.h	3721;"	d
CAN_PDD_SetTxMessageBufferID	.\Static_Code\PDD\MSCAN_PDD.h	2941;"	d
CAN_PDD_THREE_SAMPLES	.\Static_Code\PDD\MSCAN_PDD.h	67;"	d
CAN_PDD_TIME_SEGMENT1_10_TQ	.\Static_Code\PDD\MSCAN_PDD.h	89;"	d
CAN_PDD_TIME_SEGMENT1_11_TQ	.\Static_Code\PDD\MSCAN_PDD.h	90;"	d
CAN_PDD_TIME_SEGMENT1_12_TQ	.\Static_Code\PDD\MSCAN_PDD.h	91;"	d
CAN_PDD_TIME_SEGMENT1_13_TQ	.\Static_Code\PDD\MSCAN_PDD.h	92;"	d
CAN_PDD_TIME_SEGMENT1_14_TQ	.\Static_Code\PDD\MSCAN_PDD.h	93;"	d
CAN_PDD_TIME_SEGMENT1_15_TQ	.\Static_Code\PDD\MSCAN_PDD.h	94;"	d
CAN_PDD_TIME_SEGMENT1_16_TQ	.\Static_Code\PDD\MSCAN_PDD.h	95;"	d
CAN_PDD_TIME_SEGMENT1_1_TQ	.\Static_Code\PDD\MSCAN_PDD.h	80;"	d
CAN_PDD_TIME_SEGMENT1_2_TQ	.\Static_Code\PDD\MSCAN_PDD.h	81;"	d
CAN_PDD_TIME_SEGMENT1_3_TQ	.\Static_Code\PDD\MSCAN_PDD.h	82;"	d
CAN_PDD_TIME_SEGMENT1_4_TQ	.\Static_Code\PDD\MSCAN_PDD.h	83;"	d
CAN_PDD_TIME_SEGMENT1_5_TQ	.\Static_Code\PDD\MSCAN_PDD.h	84;"	d
CAN_PDD_TIME_SEGMENT1_6_TQ	.\Static_Code\PDD\MSCAN_PDD.h	85;"	d
CAN_PDD_TIME_SEGMENT1_7_TQ	.\Static_Code\PDD\MSCAN_PDD.h	86;"	d
CAN_PDD_TIME_SEGMENT1_8_TQ	.\Static_Code\PDD\MSCAN_PDD.h	87;"	d
CAN_PDD_TIME_SEGMENT1_9_TQ	.\Static_Code\PDD\MSCAN_PDD.h	88;"	d
CAN_PDD_TIME_SEGMENT2_1_TQ	.\Static_Code\PDD\MSCAN_PDD.h	70;"	d
CAN_PDD_TIME_SEGMENT2_2_TQ	.\Static_Code\PDD\MSCAN_PDD.h	71;"	d
CAN_PDD_TIME_SEGMENT2_3_TQ	.\Static_Code\PDD\MSCAN_PDD.h	72;"	d
CAN_PDD_TIME_SEGMENT2_4_TQ	.\Static_Code\PDD\MSCAN_PDD.h	73;"	d
CAN_PDD_TIME_SEGMENT2_5_TQ	.\Static_Code\PDD\MSCAN_PDD.h	74;"	d
CAN_PDD_TIME_SEGMENT2_6_TQ	.\Static_Code\PDD\MSCAN_PDD.h	75;"	d
CAN_PDD_TIME_SEGMENT2_7_TQ	.\Static_Code\PDD\MSCAN_PDD.h	76;"	d
CAN_PDD_TIME_SEGMENT2_8_TQ	.\Static_Code\PDD\MSCAN_PDD.h	77;"	d
CAN_PDD_TRANSMITTING_OR_IDLE	.\Static_Code\PDD\MSCAN_PDD.h	48;"	d
CAN_PDD_TWO_32BIT_ACCEPTANCE_FILTER	.\Static_Code\PDD\MSCAN_PDD.h	151;"	d
CAN_PDD_TX_ALL_STATE_INT	.\Static_Code\PDD\MSCAN_PDD.h	119;"	d
CAN_PDD_TX_BUS_OFF	.\Static_Code\PDD\MSCAN_PDD.h	107;"	d
CAN_PDD_TX_BUS_OFF_INT	.\Static_Code\PDD\MSCAN_PDD.h	117;"	d
CAN_PDD_TX_ERROR	.\Static_Code\PDD\MSCAN_PDD.h	106;"	d
CAN_PDD_TX_MESSAGE_BUFFER_0	.\Static_Code\PDD\MSCAN_PDD.h	122;"	d
CAN_PDD_TX_MESSAGE_BUFFER_0_ABORT	.\Static_Code\PDD\MSCAN_PDD.h	134;"	d
CAN_PDD_TX_MESSAGE_BUFFER_0_ABORT_ACK	.\Static_Code\PDD\MSCAN_PDD.h	140;"	d
CAN_PDD_TX_MESSAGE_BUFFER_0_INT	.\Static_Code\PDD\MSCAN_PDD.h	128;"	d
CAN_PDD_TX_MESSAGE_BUFFER_0_SELECT	.\Static_Code\PDD\MSCAN_PDD.h	146;"	d
CAN_PDD_TX_MESSAGE_BUFFER_1	.\Static_Code\PDD\MSCAN_PDD.h	123;"	d
CAN_PDD_TX_MESSAGE_BUFFER_1_ABORT	.\Static_Code\PDD\MSCAN_PDD.h	135;"	d
CAN_PDD_TX_MESSAGE_BUFFER_1_ABORT_ACK	.\Static_Code\PDD\MSCAN_PDD.h	141;"	d
CAN_PDD_TX_MESSAGE_BUFFER_1_INT	.\Static_Code\PDD\MSCAN_PDD.h	129;"	d
CAN_PDD_TX_MESSAGE_BUFFER_1_SELECT	.\Static_Code\PDD\MSCAN_PDD.h	147;"	d
CAN_PDD_TX_MESSAGE_BUFFER_2	.\Static_Code\PDD\MSCAN_PDD.h	124;"	d
CAN_PDD_TX_MESSAGE_BUFFER_2_ABORT	.\Static_Code\PDD\MSCAN_PDD.h	136;"	d
CAN_PDD_TX_MESSAGE_BUFFER_2_ABORT_ACK	.\Static_Code\PDD\MSCAN_PDD.h	142;"	d
CAN_PDD_TX_MESSAGE_BUFFER_2_INT	.\Static_Code\PDD\MSCAN_PDD.h	130;"	d
CAN_PDD_TX_MESSAGE_BUFFER_2_SELECT	.\Static_Code\PDD\MSCAN_PDD.h	148;"	d
CAN_PDD_TX_MESSAGE_BUFFER_ALL	.\Static_Code\PDD\MSCAN_PDD.h	125;"	d
CAN_PDD_TX_MESSAGE_BUFFER_ALL_ABORT	.\Static_Code\PDD\MSCAN_PDD.h	137;"	d
CAN_PDD_TX_MESSAGE_BUFFER_ALL_ABORT_ACK	.\Static_Code\PDD\MSCAN_PDD.h	143;"	d
CAN_PDD_TX_MESSAGE_BUFFER_ALL_INT	.\Static_Code\PDD\MSCAN_PDD.h	131;"	d
CAN_PDD_TX_OK	.\Static_Code\PDD\MSCAN_PDD.h	104;"	d
CAN_PDD_TX_STATUS_DISABLE_INT	.\Static_Code\PDD\MSCAN_PDD.h	116;"	d
CAN_PDD_TX_TX_ERROR_OR_BUS_OFF_INT	.\Static_Code\PDD\MSCAN_PDD.h	118;"	d
CAN_PDD_TX_WARNING	.\Static_Code\PDD\MSCAN_PDD.h	105;"	d
CAN_PDD_TxMessageAbortRequestMask	.\Static_Code\PDD\MSCAN_PDD.h	1489;"	d
CAN_PDD_WAKEUP_REQUESTED_FLAG	.\Static_Code\PDD\MSCAN_PDD.h	36;"	d
CAN_PDD_WAKEUP_REQUESTED_INT	.\Static_Code\PDD\MSCAN_PDD.h	42;"	d
CAN_PDD_WriteBusTiming0Reg	.\Static_Code\PDD\MSCAN_PDD.h	830;"	d
CAN_PDD_WriteBusTiming1Reg	.\Static_Code\PDD\MSCAN_PDD.h	958;"	d
CAN_PDD_WriteControl0Reg	.\Static_Code\PDD\MSCAN_PDD.h	468;"	d
CAN_PDD_WriteControl1Reg	.\Static_Code\PDD\MSCAN_PDD.h	728;"	d
CAN_PDD_WriteIdAcceptance1stBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2065;"	d
CAN_PDD_WriteIdAcceptance2ndBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2316;"	d
CAN_PDD_WriteIdAcceptanceControlReg	.\Static_Code\PDD\MSCAN_PDD.h	1754;"	d
CAN_PDD_WriteIdMask1StBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2190;"	d
CAN_PDD_WriteIdMask2ndBankReg	.\Static_Code\PDD\MSCAN_PDD.h	2441;"	d
CAN_PDD_WriteMiscellaneousReg	.\Static_Code\PDD\MSCAN_PDD.h	1851;"	d
CAN_PDD_WriteRxBufferDataLengthReg	.\Static_Code\PDD\MSCAN_PDD.h	3550;"	d
CAN_PDD_WriteRxBufferDataSegmentReg	.\Static_Code\PDD\MSCAN_PDD.h	3479;"	d
CAN_PDD_WriteRxBufferExtIdBits14To7Reg	.\Static_Code\PDD\MSCAN_PDD.h	2836;"	d
CAN_PDD_WriteRxBufferExtIdBits20To15Reg	.\Static_Code\PDD\MSCAN_PDD.h	2709;"	d
CAN_PDD_WriteRxBufferExtIdBits6To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	2912;"	d
CAN_PDD_WriteRxBufferIdExtBits28To21Reg	.\Static_Code\PDD\MSCAN_PDD.h	2552;"	d
CAN_PDD_WriteRxBufferStdIdBits10To3Reg	.\Static_Code\PDD\MSCAN_PDD.h	2601;"	d
CAN_PDD_WriteRxBufferStdIdBits2To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	2787;"	d
CAN_PDD_WriteRxFlagReg	.\Static_Code\PDD\MSCAN_PDD.h	1098;"	d
CAN_PDD_WriteRxInterruptEnableReg	.\Static_Code\PDD\MSCAN_PDD.h	1252;"	d
CAN_PDD_WriteTxBufferDataLengthReg	.\Static_Code\PDD\MSCAN_PDD.h	3773;"	d
CAN_PDD_WriteTxBufferDataSegmentReg	.\Static_Code\PDD\MSCAN_PDD.h	3697;"	d
CAN_PDD_WriteTxBufferExtIdBits14To7Reg	.\Static_Code\PDD\MSCAN_PDD.h	3322;"	d
CAN_PDD_WriteTxBufferExtIdBits20To15Reg	.\Static_Code\PDD\MSCAN_PDD.h	3190;"	d
CAN_PDD_WriteTxBufferExtIdBits6To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	3405;"	d
CAN_PDD_WriteTxBufferIdExtBits28To21Reg	.\Static_Code\PDD\MSCAN_PDD.h	3025;"	d
CAN_PDD_WriteTxBufferPriorityReg	.\Static_Code\PDD\MSCAN_PDD.h	3850;"	d
CAN_PDD_WriteTxBufferSelectionReg	.\Static_Code\PDD\MSCAN_PDD.h	1654;"	d
CAN_PDD_WriteTxBufferStdIdBits10To3Reg	.\Static_Code\PDD\MSCAN_PDD.h	3074;"	d
CAN_PDD_WriteTxBufferStdIdBits2To0Reg	.\Static_Code\PDD\MSCAN_PDD.h	3273;"	d
CAN_PDD_WriteTxFlagReg	.\Static_Code\PDD\MSCAN_PDD.h	1346;"	d
CAN_PDD_WriteTxInterruptEnableReg	.\Static_Code\PDD\MSCAN_PDD.h	1465;"	d
CAN_PDD_WriteTxMessageAbortRequestReg	.\Static_Code\PDD\MSCAN_PDD.h	1537;"	d
CAN_PDD_XTAL_CLOCK	.\Static_Code\PDD\MSCAN_PDD.h	56;"	d
CAN_RFLG	.\Static_Code\IO_Map\MC56F82748.h	1429;"	d
CAN_RFLG_CSCIF_MASK	.\Static_Code\IO_Map\MC56F82748.h	1206;"	d
CAN_RFLG_CSCIF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1207;"	d
CAN_RFLG_OVRIF_MASK	.\Static_Code\IO_Map\MC56F82748.h	1198;"	d
CAN_RFLG_OVRIF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1199;"	d
CAN_RFLG_REG	.\Static_Code\IO_Map\MC56F82748.h	1094;"	d
CAN_RFLG_RSTAT	.\Static_Code\IO_Map\MC56F82748.h	1205;"	d
CAN_RFLG_RSTAT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1203;"	d
CAN_RFLG_RSTAT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1204;"	d
CAN_RFLG_RXF_MASK	.\Static_Code\IO_Map\MC56F82748.h	1196;"	d
CAN_RFLG_RXF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1197;"	d
CAN_RFLG_TSTAT	.\Static_Code\IO_Map\MC56F82748.h	1202;"	d
CAN_RFLG_TSTAT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1200;"	d
CAN_RFLG_TSTAT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1201;"	d
CAN_RFLG_WUPIF_MASK	.\Static_Code\IO_Map\MC56F82748.h	1208;"	d
CAN_RFLG_WUPIF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1209;"	d
CAN_RIER	.\Static_Code\IO_Map\MC56F82748.h	1430;"	d
CAN_RIER_CSCIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1221;"	d
CAN_RIER_CSCIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1222;"	d
CAN_RIER_OVRIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1213;"	d
CAN_RIER_OVRIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1214;"	d
CAN_RIER_REG	.\Static_Code\IO_Map\MC56F82748.h	1095;"	d
CAN_RIER_RSTATE	.\Static_Code\IO_Map\MC56F82748.h	1220;"	d
CAN_RIER_RSTATE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1218;"	d
CAN_RIER_RSTATE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1219;"	d
CAN_RIER_RXFIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1211;"	d
CAN_RIER_RXFIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1212;"	d
CAN_RIER_TSTATE	.\Static_Code\IO_Map\MC56F82748.h	1217;"	d
CAN_RIER_TSTATE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1215;"	d
CAN_RIER_TSTATE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1216;"	d
CAN_RIER_WUPIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1223;"	d
CAN_RIER_WUPIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1224;"	d
CAN_RXERR	.\Static_Code\IO_Map\MC56F82748.h	1438;"	d
CAN_RXERR_REG	.\Static_Code\IO_Map\MC56F82748.h	1103;"	d
CAN_RXERR_RXERR	.\Static_Code\IO_Map\MC56F82748.h	1258;"	d
CAN_RXERR_RXERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1256;"	d
CAN_RXERR_RXERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1257;"	d
CAN_RXFG_DLR	.\Static_Code\IO_Map\MC56F82748.h	1470;"	d
CAN_RXFG_DLR_DLC	.\Static_Code\IO_Map\MC56F82748.h	1326;"	d
CAN_RXFG_DLR_DLC_MASK	.\Static_Code\IO_Map\MC56F82748.h	1324;"	d
CAN_RXFG_DLR_DLC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1325;"	d
CAN_RXFG_DLR_REG	.\Static_Code\IO_Map\MC56F82748.h	1116;"	d
CAN_RXFG_DLR_Unimplemented	.\Static_Code\IO_Map\MC56F82748.h	1329;"	d
CAN_RXFG_DLR_Unimplemented_MASK	.\Static_Code\IO_Map\MC56F82748.h	1327;"	d
CAN_RXFG_DLR_Unimplemented_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1328;"	d
CAN_RXFG_DSR	.\Static_Code\IO_Map\MC56F82748.h	1497;"	d
CAN_RXFG_DSR0	.\Static_Code\IO_Map\MC56F82748.h	1462;"	d
CAN_RXFG_DSR1	.\Static_Code\IO_Map\MC56F82748.h	1463;"	d
CAN_RXFG_DSR2	.\Static_Code\IO_Map\MC56F82748.h	1464;"	d
CAN_RXFG_DSR3	.\Static_Code\IO_Map\MC56F82748.h	1465;"	d
CAN_RXFG_DSR4	.\Static_Code\IO_Map\MC56F82748.h	1466;"	d
CAN_RXFG_DSR5	.\Static_Code\IO_Map\MC56F82748.h	1467;"	d
CAN_RXFG_DSR6	.\Static_Code\IO_Map\MC56F82748.h	1468;"	d
CAN_RXFG_DSR7	.\Static_Code\IO_Map\MC56F82748.h	1469;"	d
CAN_RXFG_DSR_DB	.\Static_Code\IO_Map\MC56F82748.h	1322;"	d
CAN_RXFG_DSR_DB_MASK	.\Static_Code\IO_Map\MC56F82748.h	1320;"	d
CAN_RXFG_DSR_DB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1321;"	d
CAN_RXFG_DSR_REG	.\Static_Code\IO_Map\MC56F82748.h	1115;"	d
CAN_RXFG_IDR0_EXT	.\Static_Code\IO_Map\MC56F82748.h	1456;"	d
CAN_RXFG_IDR0_EXT_ID	.\Static_Code\IO_Map\MC56F82748.h	1282;"	d
CAN_RXFG_IDR0_EXT_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1280;"	d
CAN_RXFG_IDR0_EXT_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1281;"	d
CAN_RXFG_IDR0_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1109;"	d
CAN_RXFG_IDR0_STD	.\Static_Code\IO_Map\MC56F82748.h	1457;"	d
CAN_RXFG_IDR0_STD_ID	.\Static_Code\IO_Map\MC56F82748.h	1286;"	d
CAN_RXFG_IDR0_STD_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1284;"	d
CAN_RXFG_IDR0_STD_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1285;"	d
CAN_RXFG_IDR0_STD_REG	.\Static_Code\IO_Map\MC56F82748.h	1110;"	d
CAN_RXFG_IDR1_EXT	.\Static_Code\IO_Map\MC56F82748.h	1458;"	d
CAN_RXFG_IDR1_EXT_IDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1291;"	d
CAN_RXFG_IDR1_EXT_IDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1292;"	d
CAN_RXFG_IDR1_EXT_ID_17_15	.\Static_Code\IO_Map\MC56F82748.h	1290;"	d
CAN_RXFG_IDR1_EXT_ID_17_15_MASK	.\Static_Code\IO_Map\MC56F82748.h	1288;"	d
CAN_RXFG_IDR1_EXT_ID_17_15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1289;"	d
CAN_RXFG_IDR1_EXT_ID_20_18	.\Static_Code\IO_Map\MC56F82748.h	1297;"	d
CAN_RXFG_IDR1_EXT_ID_20_18_MASK	.\Static_Code\IO_Map\MC56F82748.h	1295;"	d
CAN_RXFG_IDR1_EXT_ID_20_18_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1296;"	d
CAN_RXFG_IDR1_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1111;"	d
CAN_RXFG_IDR1_EXT_SRR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1293;"	d
CAN_RXFG_IDR1_EXT_SRR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1294;"	d
CAN_RXFG_IDR1_STD	.\Static_Code\IO_Map\MC56F82748.h	1459;"	d
CAN_RXFG_IDR1_STD_ID	.\Static_Code\IO_Map\MC56F82748.h	1308;"	d
CAN_RXFG_IDR1_STD_IDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1302;"	d
CAN_RXFG_IDR1_STD_IDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1303;"	d
CAN_RXFG_IDR1_STD_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1306;"	d
CAN_RXFG_IDR1_STD_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1307;"	d
CAN_RXFG_IDR1_STD_REG	.\Static_Code\IO_Map\MC56F82748.h	1112;"	d
CAN_RXFG_IDR1_STD_RTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1304;"	d
CAN_RXFG_IDR1_STD_RTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1305;"	d
CAN_RXFG_IDR1_STD_Unimplemented	.\Static_Code\IO_Map\MC56F82748.h	1301;"	d
CAN_RXFG_IDR1_STD_Unimplemented_MASK	.\Static_Code\IO_Map\MC56F82748.h	1299;"	d
CAN_RXFG_IDR1_STD_Unimplemented_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1300;"	d
CAN_RXFG_IDR2_EXT	.\Static_Code\IO_Map\MC56F82748.h	1460;"	d
CAN_RXFG_IDR2_EXT_ID	.\Static_Code\IO_Map\MC56F82748.h	1312;"	d
CAN_RXFG_IDR2_EXT_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1310;"	d
CAN_RXFG_IDR2_EXT_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1311;"	d
CAN_RXFG_IDR2_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1113;"	d
CAN_RXFG_IDR3_EXT	.\Static_Code\IO_Map\MC56F82748.h	1461;"	d
CAN_RXFG_IDR3_EXT_ID	.\Static_Code\IO_Map\MC56F82748.h	1318;"	d
CAN_RXFG_IDR3_EXT_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1316;"	d
CAN_RXFG_IDR3_EXT_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1317;"	d
CAN_RXFG_IDR3_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1114;"	d
CAN_RXFG_IDR3_EXT_RTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1314;"	d
CAN_RXFG_IDR3_EXT_RTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1315;"	d
CAN_RXFG_TSRH	.\Static_Code\IO_Map\MC56F82748.h	1471;"	d
CAN_RXFG_TSRH_REG	.\Static_Code\IO_Map\MC56F82748.h	1117;"	d
CAN_RXFG_TSRH_TSR	.\Static_Code\IO_Map\MC56F82748.h	1333;"	d
CAN_RXFG_TSRH_TSR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1331;"	d
CAN_RXFG_TSRH_TSR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1332;"	d
CAN_RXFG_TSRL	.\Static_Code\IO_Map\MC56F82748.h	1472;"	d
CAN_RXFG_TSRL_REG	.\Static_Code\IO_Map\MC56F82748.h	1118;"	d
CAN_RXFG_TSRL_TSR	.\Static_Code\IO_Map\MC56F82748.h	1337;"	d
CAN_RXFG_TSRL_TSR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1335;"	d
CAN_RXFG_TSRL_TSR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1336;"	d
CAN_TAAK	.\Static_Code\IO_Map\MC56F82748.h	1434;"	d
CAN_TAAK_ABTAK	.\Static_Code\IO_Map\MC56F82748.h	1240;"	d
CAN_TAAK_ABTAK_MASK	.\Static_Code\IO_Map\MC56F82748.h	1238;"	d
CAN_TAAK_ABTAK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1239;"	d
CAN_TAAK_REG	.\Static_Code\IO_Map\MC56F82748.h	1099;"	d
CAN_TARQ	.\Static_Code\IO_Map\MC56F82748.h	1433;"	d
CAN_TARQ_ABTRQ	.\Static_Code\IO_Map\MC56F82748.h	1236;"	d
CAN_TARQ_ABTRQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	1234;"	d
CAN_TARQ_ABTRQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1235;"	d
CAN_TARQ_REG	.\Static_Code\IO_Map\MC56F82748.h	1098;"	d
CAN_TBSEL	.\Static_Code\IO_Map\MC56F82748.h	1435;"	d
CAN_TBSEL_REG	.\Static_Code\IO_Map\MC56F82748.h	1100;"	d
CAN_TBSEL_TX	.\Static_Code\IO_Map\MC56F82748.h	1244;"	d
CAN_TBSEL_TX_MASK	.\Static_Code\IO_Map\MC56F82748.h	1242;"	d
CAN_TBSEL_TX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1243;"	d
CAN_TFLG	.\Static_Code\IO_Map\MC56F82748.h	1431;"	d
CAN_TFLG_REG	.\Static_Code\IO_Map\MC56F82748.h	1096;"	d
CAN_TFLG_TXE	.\Static_Code\IO_Map\MC56F82748.h	1228;"	d
CAN_TFLG_TXE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1226;"	d
CAN_TFLG_TXE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1227;"	d
CAN_TIER	.\Static_Code\IO_Map\MC56F82748.h	1432;"	d
CAN_TIER_REG	.\Static_Code\IO_Map\MC56F82748.h	1097;"	d
CAN_TIER_TXEIE	.\Static_Code\IO_Map\MC56F82748.h	1232;"	d
CAN_TIER_TXEIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1230;"	d
CAN_TIER_TXEIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1231;"	d
CAN_TXERR	.\Static_Code\IO_Map\MC56F82748.h	1439;"	d
CAN_TXERR_REG	.\Static_Code\IO_Map\MC56F82748.h	1104;"	d
CAN_TXERR_TXERR	.\Static_Code\IO_Map\MC56F82748.h	1262;"	d
CAN_TXERR_TXERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1260;"	d
CAN_TXERR_TXERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1261;"	d
CAN_TXFG_DLR	.\Static_Code\IO_Map\MC56F82748.h	1487;"	d
CAN_TXFG_DLR_DLC	.\Static_Code\IO_Map\MC56F82748.h	1385;"	d
CAN_TXFG_DLR_DLC_MASK	.\Static_Code\IO_Map\MC56F82748.h	1383;"	d
CAN_TXFG_DLR_DLC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1384;"	d
CAN_TXFG_DLR_REG	.\Static_Code\IO_Map\MC56F82748.h	1126;"	d
CAN_TXFG_DLR_Unimplemented	.\Static_Code\IO_Map\MC56F82748.h	1388;"	d
CAN_TXFG_DLR_Unimplemented_MASK	.\Static_Code\IO_Map\MC56F82748.h	1386;"	d
CAN_TXFG_DLR_Unimplemented_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1387;"	d
CAN_TXFG_DSR	.\Static_Code\IO_Map\MC56F82748.h	1498;"	d
CAN_TXFG_DSR0	.\Static_Code\IO_Map\MC56F82748.h	1479;"	d
CAN_TXFG_DSR1	.\Static_Code\IO_Map\MC56F82748.h	1480;"	d
CAN_TXFG_DSR2	.\Static_Code\IO_Map\MC56F82748.h	1481;"	d
CAN_TXFG_DSR3	.\Static_Code\IO_Map\MC56F82748.h	1482;"	d
CAN_TXFG_DSR4	.\Static_Code\IO_Map\MC56F82748.h	1483;"	d
CAN_TXFG_DSR5	.\Static_Code\IO_Map\MC56F82748.h	1484;"	d
CAN_TXFG_DSR6	.\Static_Code\IO_Map\MC56F82748.h	1485;"	d
CAN_TXFG_DSR7	.\Static_Code\IO_Map\MC56F82748.h	1486;"	d
CAN_TXFG_DSR_DB	.\Static_Code\IO_Map\MC56F82748.h	1381;"	d
CAN_TXFG_DSR_DB_MASK	.\Static_Code\IO_Map\MC56F82748.h	1379;"	d
CAN_TXFG_DSR_DB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1380;"	d
CAN_TXFG_DSR_REG	.\Static_Code\IO_Map\MC56F82748.h	1125;"	d
CAN_TXFG_IDR0_EXT	.\Static_Code\IO_Map\MC56F82748.h	1473;"	d
CAN_TXFG_IDR0_EXT_ID	.\Static_Code\IO_Map\MC56F82748.h	1341;"	d
CAN_TXFG_IDR0_EXT_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1339;"	d
CAN_TXFG_IDR0_EXT_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1340;"	d
CAN_TXFG_IDR0_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1119;"	d
CAN_TXFG_IDR0_STD	.\Static_Code\IO_Map\MC56F82748.h	1474;"	d
CAN_TXFG_IDR0_STD_ID	.\Static_Code\IO_Map\MC56F82748.h	1345;"	d
CAN_TXFG_IDR0_STD_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1343;"	d
CAN_TXFG_IDR0_STD_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1344;"	d
CAN_TXFG_IDR0_STD_REG	.\Static_Code\IO_Map\MC56F82748.h	1120;"	d
CAN_TXFG_IDR1_EXT	.\Static_Code\IO_Map\MC56F82748.h	1475;"	d
CAN_TXFG_IDR1_EXT_IDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1350;"	d
CAN_TXFG_IDR1_EXT_IDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1351;"	d
CAN_TXFG_IDR1_EXT_ID_17_15	.\Static_Code\IO_Map\MC56F82748.h	1349;"	d
CAN_TXFG_IDR1_EXT_ID_17_15_MASK	.\Static_Code\IO_Map\MC56F82748.h	1347;"	d
CAN_TXFG_IDR1_EXT_ID_17_15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1348;"	d
CAN_TXFG_IDR1_EXT_ID_20_18	.\Static_Code\IO_Map\MC56F82748.h	1356;"	d
CAN_TXFG_IDR1_EXT_ID_20_18_MASK	.\Static_Code\IO_Map\MC56F82748.h	1354;"	d
CAN_TXFG_IDR1_EXT_ID_20_18_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1355;"	d
CAN_TXFG_IDR1_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1121;"	d
CAN_TXFG_IDR1_EXT_SRR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1352;"	d
CAN_TXFG_IDR1_EXT_SRR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1353;"	d
CAN_TXFG_IDR1_STD	.\Static_Code\IO_Map\MC56F82748.h	1476;"	d
CAN_TXFG_IDR1_STD_ID	.\Static_Code\IO_Map\MC56F82748.h	1367;"	d
CAN_TXFG_IDR1_STD_IDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1361;"	d
CAN_TXFG_IDR1_STD_IDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1362;"	d
CAN_TXFG_IDR1_STD_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1365;"	d
CAN_TXFG_IDR1_STD_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1366;"	d
CAN_TXFG_IDR1_STD_REG	.\Static_Code\IO_Map\MC56F82748.h	1122;"	d
CAN_TXFG_IDR1_STD_RTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1363;"	d
CAN_TXFG_IDR1_STD_RTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1364;"	d
CAN_TXFG_IDR1_STD_Unimplemented	.\Static_Code\IO_Map\MC56F82748.h	1360;"	d
CAN_TXFG_IDR1_STD_Unimplemented_MASK	.\Static_Code\IO_Map\MC56F82748.h	1358;"	d
CAN_TXFG_IDR1_STD_Unimplemented_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1359;"	d
CAN_TXFG_IDR2_EXT	.\Static_Code\IO_Map\MC56F82748.h	1477;"	d
CAN_TXFG_IDR2_EXT_ID	.\Static_Code\IO_Map\MC56F82748.h	1371;"	d
CAN_TXFG_IDR2_EXT_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1369;"	d
CAN_TXFG_IDR2_EXT_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1370;"	d
CAN_TXFG_IDR2_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1123;"	d
CAN_TXFG_IDR3_EXT	.\Static_Code\IO_Map\MC56F82748.h	1478;"	d
CAN_TXFG_IDR3_EXT_ID	.\Static_Code\IO_Map\MC56F82748.h	1377;"	d
CAN_TXFG_IDR3_EXT_ID_MASK	.\Static_Code\IO_Map\MC56F82748.h	1375;"	d
CAN_TXFG_IDR3_EXT_ID_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1376;"	d
CAN_TXFG_IDR3_EXT_REG	.\Static_Code\IO_Map\MC56F82748.h	1124;"	d
CAN_TXFG_IDR3_EXT_RTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1373;"	d
CAN_TXFG_IDR3_EXT_RTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1374;"	d
CAN_TXFG_TBPR	.\Static_Code\IO_Map\MC56F82748.h	1488;"	d
CAN_TXFG_TBPR_PRIO	.\Static_Code\IO_Map\MC56F82748.h	1392;"	d
CAN_TXFG_TBPR_PRIO_MASK	.\Static_Code\IO_Map\MC56F82748.h	1390;"	d
CAN_TXFG_TBPR_PRIO_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1391;"	d
CAN_TXFG_TBPR_REG	.\Static_Code\IO_Map\MC56F82748.h	1127;"	d
CAN_TXFG_TSRH	.\Static_Code\IO_Map\MC56F82748.h	1489;"	d
CAN_TXFG_TSRH_REG	.\Static_Code\IO_Map\MC56F82748.h	1128;"	d
CAN_TXFG_TSRH_TSR	.\Static_Code\IO_Map\MC56F82748.h	1396;"	d
CAN_TXFG_TSRH_TSR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1394;"	d
CAN_TXFG_TSRH_TSR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1395;"	d
CAN_TXFG_TSRL	.\Static_Code\IO_Map\MC56F82748.h	1490;"	d
CAN_TXFG_TSRL_REG	.\Static_Code\IO_Map\MC56F82748.h	1129;"	d
CAN_TXFG_TSRL_TSR	.\Static_Code\IO_Map\MC56F82748.h	1400;"	d
CAN_TXFG_TSRL_TSR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1398;"	d
CAN_TXFG_TSRL_TSR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1399;"	d
CAPT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPT;                                   \/**< Timer Channel Capture Register, array offset: 0x2, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
CAPTCOMPA	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPTCOMPA;                              \/**< Capture Compare A Register, array offset: 0x1B, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CAPTCOMPB	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPTCOMPB;                              \/**< Capture Compare B Register, array offset: 0x1D, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CAPTCOMPX	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPTCOMPX;                              \/**< Capture Compare X Register, array offset: 0x1F, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CAPTCTRLA	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPTCTRLA;                              \/**< Capture Control A Register, array offset: 0x1A, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CAPTCTRLB	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPTCTRLB;                              \/**< Capture Control B Register, array offset: 0x1C, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CAPTCTRLX	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CAPTCTRLX;                              \/**< Capture Control X Register, array offset: 0x1E, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CC_DEPS	.\FLASH_SDM\sources.mk	/^CC_DEPS := $/;"	m
CC_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^CC_DEPS_OS_FORMAT := $/;"	m
CC_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^CC_DEPS_QUOTED := $/;"	m
CC_SRCS	.\FLASH_SDM\sources.mk	/^CC_SRCS := $/;"	m
CC_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^CC_SRCS_OS_FORMAT := $/;"	m
CC_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^CC_SRCS_QUOTED := $/;"	m
CFADR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t CFADR;                                  \/**< Core fault address register, offset: 0x10 *\/$/;"	m	struct:MCM_MemMap
CFATR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t CFATR;                                   \/**< Core fault attributes register, offset: 0x14 *\/$/;"	m	struct:MCM_MemMap
CFDTR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t CFDTR;                                  \/**< Core fault data register, offset: 0x18 *\/$/;"	m	struct:MCM_MemMap
CFIER	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t CFIER;                                   \/**< Core fault interrupt enable register, offset: 0x16 *\/$/;"	m	struct:MCM_MemMap
CFISR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t CFISR;                                   \/**< MCM interrupt status register, offset: 0x17 *\/$/;"	m	struct:MCM_MemMap
CFLOC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t CFLOC;                                   \/**< Core fault location register, offset: 0x15 *\/$/;"	m	struct:MCM_MemMap
CLIST1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLIST1;                                 \/**< ADC Channel List Register 1, offset: 0x4 *\/$/;"	m	struct:ADC_MemMap
CLIST2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLIST2;                                 \/**< ADC Channel List Register 2, offset: 0x5 *\/$/;"	m	struct:ADC_MemMap
CLIST3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLIST3;                                 \/**< ADC Channel List Register 3, offset: 0x6 *\/$/;"	m	struct:ADC_MemMap
CLIST4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLIST4;                                 \/**< ADC Channel List Register 4, offset: 0x7 *\/$/;"	m	struct:ADC_MemMap
CLIST5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLIST5;                                 \/**< ADC Channel List Register 5, offset: 0x59 *\/$/;"	m	struct:ADC_MemMap
CLKCHKR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLKCHKR;                                \/**< External Clock Check Reference, offset: 0x6 *\/$/;"	m	struct:OCCS_MemMap
CLKCHKT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLKCHKT;                                \/**< External Clock Check Target, offset: 0x7 *\/$/;"	m	struct:OCCS_MemMap
CLKCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLKCTRL;                                \/**< Clock Control Register, offset: 0x4 *\/$/;"	m	struct:EWM_MemMap
CLKOUT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLKOUT;                                 \/**< Clock Output Select Register, offset: 0xA *\/$/;"	m	struct:SIM_MemMap
CLKPRESCALER	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CLKPRESCALER;                           \/**< Clock Prescaler Register, offset: 0x5 *\/$/;"	m	struct:EWM_MemMap
CMPA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1621;"	d
CMPA_CR0	.\Static_Code\IO_Map\MC56F82748.h	1643;"	d
CMPA_CR1	.\Static_Code\IO_Map\MC56F82748.h	1644;"	d
CMPA_DACCR	.\Static_Code\IO_Map\MC56F82748.h	1647;"	d
CMPA_FPR	.\Static_Code\IO_Map\MC56F82748.h	1645;"	d
CMPA_Init	.\Static_Code\Peripherals\CMPA_Init.c	/^void CMPA_Init(void) {$/;"	f
CMPA_MUXCR	.\Static_Code\IO_Map\MC56F82748.h	1648;"	d
CMPA_SCR	.\Static_Code\IO_Map\MC56F82748.h	1646;"	d
CMPB_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1623;"	d
CMPB_CR0	.\Static_Code\IO_Map\MC56F82748.h	1650;"	d
CMPB_CR1	.\Static_Code\IO_Map\MC56F82748.h	1651;"	d
CMPB_DACCR	.\Static_Code\IO_Map\MC56F82748.h	1654;"	d
CMPB_FPR	.\Static_Code\IO_Map\MC56F82748.h	1652;"	d
CMPB_Init	.\Static_Code\Peripherals\CMPB_Init.c	/^void CMPB_Init(void) {$/;"	f
CMPB_MUXCR	.\Static_Code\IO_Map\MC56F82748.h	1655;"	d
CMPB_SCR	.\Static_Code\IO_Map\MC56F82748.h	1653;"	d
CMPC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1625;"	d
CMPC_CR0	.\Static_Code\IO_Map\MC56F82748.h	1657;"	d
CMPC_CR1	.\Static_Code\IO_Map\MC56F82748.h	1658;"	d
CMPC_DACCR	.\Static_Code\IO_Map\MC56F82748.h	1661;"	d
CMPC_FPR	.\Static_Code\IO_Map\MC56F82748.h	1659;"	d
CMPC_Init	.\Static_Code\Peripherals\CMPC_Init.c	/^void CMPC_Init(void) {$/;"	f
CMPC_MUXCR	.\Static_Code\IO_Map\MC56F82748.h	1662;"	d
CMPC_SCR	.\Static_Code\IO_Map\MC56F82748.h	1660;"	d
CMPD_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1627;"	d
CMPD_CR0	.\Static_Code\IO_Map\MC56F82748.h	1664;"	d
CMPD_CR1	.\Static_Code\IO_Map\MC56F82748.h	1665;"	d
CMPD_DACCR	.\Static_Code\IO_Map\MC56F82748.h	1668;"	d
CMPD_FPR	.\Static_Code\IO_Map\MC56F82748.h	1666;"	d
CMPD_Init	.\Static_Code\Peripherals\CMPD_Init.c	/^void CMPD_Init(void) {$/;"	f
CMPD_MUXCR	.\Static_Code\IO_Map\MC56F82748.h	1669;"	d
CMPD_SCR	.\Static_Code\IO_Map\MC56F82748.h	1667;"	d
CMPH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CMPH;                                   \/**< Compare High Register, offset: 0x3 *\/$/;"	m	struct:EWM_MemMap
CMPL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CMPL;                                   \/**< Compare Low Register, offset: 0x2 *\/$/;"	m	struct:EWM_MemMap
CMPLD1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CMPLD1;                                 \/**< Timer Channel Comparator Load Register 1, array offset: 0x8, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
CMPLD2	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CMPLD2;                                 \/**< Timer Channel Comparator Load Register 2, array offset: 0x9, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
CMP_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	1629;"	d
CMP_CR0_FILTER_CNT	.\Static_Code\IO_Map\MC56F82748.h	1567;"	d
CMP_CR0_FILTER_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1565;"	d
CMP_CR0_FILTER_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1566;"	d
CMP_CR0_HYSTCTR	.\Static_Code\IO_Map\MC56F82748.h	1564;"	d
CMP_CR0_HYSTCTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1562;"	d
CMP_CR0_HYSTCTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1563;"	d
CMP_CR0_REG	.\Static_Code\IO_Map\MC56F82748.h	1540;"	d
CMP_CR1_COS_MASK	.\Static_Code\IO_Map\MC56F82748.h	1573;"	d
CMP_CR1_COS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1574;"	d
CMP_CR1_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1569;"	d
CMP_CR1_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1570;"	d
CMP_CR1_INV_MASK	.\Static_Code\IO_Map\MC56F82748.h	1575;"	d
CMP_CR1_INV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1576;"	d
CMP_CR1_OPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1571;"	d
CMP_CR1_OPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1572;"	d
CMP_CR1_PMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1577;"	d
CMP_CR1_PMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1578;"	d
CMP_CR1_REG	.\Static_Code\IO_Map\MC56F82748.h	1541;"	d
CMP_CR1_SE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1581;"	d
CMP_CR1_SE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1582;"	d
CMP_CR1_WE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1579;"	d
CMP_CR1_WE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1580;"	d
CMP_DACCR_DACEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1604;"	d
CMP_DACCR_DACEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1605;"	d
CMP_DACCR_REG	.\Static_Code\IO_Map\MC56F82748.h	1544;"	d
CMP_DACCR_VOSEL	.\Static_Code\IO_Map\MC56F82748.h	1601;"	d
CMP_DACCR_VOSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1599;"	d
CMP_DACCR_VOSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1600;"	d
CMP_DACCR_VRSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1602;"	d
CMP_DACCR_VRSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1603;"	d
CMP_FPR_FILT_PER	.\Static_Code\IO_Map\MC56F82748.h	1586;"	d
CMP_FPR_FILT_PER_MASK	.\Static_Code\IO_Map\MC56F82748.h	1584;"	d
CMP_FPR_FILT_PER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1585;"	d
CMP_FPR_REG	.\Static_Code\IO_Map\MC56F82748.h	1542;"	d
CMP_MUXCR_MSEL	.\Static_Code\IO_Map\MC56F82748.h	1609;"	d
CMP_MUXCR_MSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1607;"	d
CMP_MUXCR_MSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1608;"	d
CMP_MUXCR_PSEL	.\Static_Code\IO_Map\MC56F82748.h	1612;"	d
CMP_MUXCR_PSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1610;"	d
CMP_MUXCR_PSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1611;"	d
CMP_MUXCR_REG	.\Static_Code\IO_Map\MC56F82748.h	1545;"	d
CMP_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct CMP_MemMap {$/;"	s
CMP_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *CMP_MemMapPtr;$/;"	t
CMP_PDD_BOTH_EDGES_MODE	.\Static_Code\PDD\CMP_PDD.h	51;"	d
CMP_PDD_ClearInterruptFlags	.\Static_Code\PDD\CMP_PDD.h	293;"	d
CMP_PDD_DisableInterrupts	.\Static_Code\PDD\CMP_PDD.h	196;"	d
CMP_PDD_EDGE_SENSITIVE_MODE	.\Static_Code\PDD\CMP_PDD.h	84;"	d
CMP_PDD_EnableDac	.\Static_Code\PDD\CMP_PDD.h	858;"	d
CMP_PDD_EnableDevice	.\Static_Code\PDD\CMP_PDD.h	129;"	d
CMP_PDD_EnableInterrupts	.\Static_Code\PDD\CMP_PDD.h	171;"	d
CMP_PDD_EnableOutputPin	.\Static_Code\PDD\CMP_PDD.h	412;"	d
CMP_PDD_EnableSampling	.\Static_Code\PDD\CMP_PDD.h	630;"	d
CMP_PDD_EnableWindowing	.\Static_Code\PDD\CMP_PDD.h	586;"	d
CMP_PDD_FALLING_EDGE_FLAG	.\Static_Code\PDD\CMP_PDD.h	45;"	d
CMP_PDD_FALLING_EDGE_INTERRUPT	.\Static_Code\PDD\CMP_PDD.h	41;"	d
CMP_PDD_FALLING_EDGE_MODE	.\Static_Code\PDD\CMP_PDD.h	49;"	d
CMP_PDD_FILTERED_OUTPUT	.\Static_Code\PDD\CMP_PDD.h	71;"	d
CMP_PDD_FILTER_1_SAMPLE	.\Static_Code\PDD\CMP_PDD.h	62;"	d
CMP_PDD_FILTER_2_SAMPLES	.\Static_Code\PDD\CMP_PDD.h	63;"	d
CMP_PDD_FILTER_3_SAMPLES	.\Static_Code\PDD\CMP_PDD.h	64;"	d
CMP_PDD_FILTER_4_SAMPLES	.\Static_Code\PDD\CMP_PDD.h	65;"	d
CMP_PDD_FILTER_5_SAMPLES	.\Static_Code\PDD\CMP_PDD.h	66;"	d
CMP_PDD_FILTER_6_SAMPLES	.\Static_Code\PDD\CMP_PDD.h	67;"	d
CMP_PDD_FILTER_7_SAMPLES	.\Static_Code\PDD\CMP_PDD.h	68;"	d
CMP_PDD_FILTER_DISABLED	.\Static_Code\PDD\CMP_PDD.h	61;"	d
CMP_PDD_GetComparatorOutput	.\Static_Code\PDD\CMP_PDD.h	713;"	d
CMP_PDD_GetComparatorOutputFilter	.\Static_Code\PDD\CMP_PDD.h	476;"	d
CMP_PDD_GetComparatorOutputInversion	.\Static_Code\PDD\CMP_PDD.h	520;"	d
CMP_PDD_GetCompareStatus	.\Static_Code\PDD\CMP_PDD.h	750;"	d
CMP_PDD_GetDacEnabled	.\Static_Code\PDD\CMP_PDD.h	879;"	d
CMP_PDD_GetDeviceEnabled	.\Static_Code\PDD\CMP_PDD.h	150;"	d
CMP_PDD_GetFilterCount	.\Static_Code\PDD\CMP_PDD.h	389;"	d
CMP_PDD_GetFilterPeriod	.\Static_Code\PDD\CMP_PDD.h	694;"	d
CMP_PDD_GetHysteresis	.\Static_Code\PDD\CMP_PDD.h	344;"	d
CMP_PDD_GetInterruptFlags	.\Static_Code\PDD\CMP_PDD.h	269;"	d
CMP_PDD_GetInterruptMask	.\Static_Code\PDD\CMP_PDD.h	246;"	d
CMP_PDD_GetNegativeInput	.\Static_Code\PDD\CMP_PDD.h	924;"	d
CMP_PDD_GetOutputPinEnabled	.\Static_Code\PDD\CMP_PDD.h	433;"	d
CMP_PDD_GetPositiveInput	.\Static_Code\PDD\CMP_PDD.h	969;"	d
CMP_PDD_GetPowerMode	.\Static_Code\PDD\CMP_PDD.h	563;"	d
CMP_PDD_GetReference	.\Static_Code\PDD\CMP_PDD.h	836;"	d
CMP_PDD_GetSamplingEnabled	.\Static_Code\PDD\CMP_PDD.h	651;"	d
CMP_PDD_GetVoltage	.\Static_Code\PDD\CMP_PDD.h	793;"	d
CMP_PDD_GetWindowingEnabled	.\Static_Code\PDD\CMP_PDD.h	607;"	d
CMP_PDD_HIGH_SPEED_MODE	.\Static_Code\PDD\CMP_PDD.h	80;"	d
CMP_PDD_HYSTERESIS_LEVEL_0	.\Static_Code\PDD\CMP_PDD.h	55;"	d
CMP_PDD_HYSTERESIS_LEVEL_1	.\Static_Code\PDD\CMP_PDD.h	56;"	d
CMP_PDD_HYSTERESIS_LEVEL_2	.\Static_Code\PDD\CMP_PDD.h	57;"	d
CMP_PDD_HYSTERESIS_LEVEL_3	.\Static_Code\PDD\CMP_PDD.h	58;"	d
CMP_PDD_H_	.\Static_Code\PDD\CMP_PDD.h	9;"	d
CMP_PDD_INVERTED_OUTPUT	.\Static_Code\PDD\CMP_PDD.h	76;"	d
CMP_PDD_LEVEL_SENSITIVE_MODE	.\Static_Code\PDD\CMP_PDD.h	83;"	d
CMP_PDD_LOW_POWER_MODE	.\Static_Code\PDD\CMP_PDD.h	79;"	d
CMP_PDD_NEGATIVE_INPUT_0	.\Static_Code\PDD\CMP_PDD.h	91;"	d
CMP_PDD_NEGATIVE_INPUT_1	.\Static_Code\PDD\CMP_PDD.h	92;"	d
CMP_PDD_NEGATIVE_INPUT_2	.\Static_Code\PDD\CMP_PDD.h	93;"	d
CMP_PDD_NEGATIVE_INPUT_3	.\Static_Code\PDD\CMP_PDD.h	94;"	d
CMP_PDD_NEGATIVE_INPUT_4	.\Static_Code\PDD\CMP_PDD.h	95;"	d
CMP_PDD_NEGATIVE_INPUT_5	.\Static_Code\PDD\CMP_PDD.h	96;"	d
CMP_PDD_NEGATIVE_INPUT_6	.\Static_Code\PDD\CMP_PDD.h	97;"	d
CMP_PDD_NEGATIVE_INPUT_7	.\Static_Code\PDD\CMP_PDD.h	98;"	d
CMP_PDD_NOT_INVERTED_OUTPUT	.\Static_Code\PDD\CMP_PDD.h	75;"	d
CMP_PDD_POSITIVE_INPUT_0	.\Static_Code\PDD\CMP_PDD.h	101;"	d
CMP_PDD_POSITIVE_INPUT_1	.\Static_Code\PDD\CMP_PDD.h	102;"	d
CMP_PDD_POSITIVE_INPUT_2	.\Static_Code\PDD\CMP_PDD.h	103;"	d
CMP_PDD_POSITIVE_INPUT_3	.\Static_Code\PDD\CMP_PDD.h	104;"	d
CMP_PDD_POSITIVE_INPUT_4	.\Static_Code\PDD\CMP_PDD.h	105;"	d
CMP_PDD_POSITIVE_INPUT_5	.\Static_Code\PDD\CMP_PDD.h	106;"	d
CMP_PDD_POSITIVE_INPUT_6	.\Static_Code\PDD\CMP_PDD.h	107;"	d
CMP_PDD_POSITIVE_INPUT_7	.\Static_Code\PDD\CMP_PDD.h	108;"	d
CMP_PDD_RISING_EDGE_FLAG	.\Static_Code\PDD\CMP_PDD.h	46;"	d
CMP_PDD_RISING_EDGE_INTERRUPT	.\Static_Code\PDD\CMP_PDD.h	42;"	d
CMP_PDD_RISING_EDGE_MODE	.\Static_Code\PDD\CMP_PDD.h	50;"	d
CMP_PDD_SetComparatorMode	.\Static_Code\PDD\CMP_PDD.h	732;"	d
CMP_PDD_SetComparatorOutputFilter	.\Static_Code\PDD\CMP_PDD.h	454;"	d
CMP_PDD_SetComparatorOutputInversion	.\Static_Code\PDD\CMP_PDD.h	498;"	d
CMP_PDD_SetFilterCount	.\Static_Code\PDD\CMP_PDD.h	365;"	d
CMP_PDD_SetFilterPeriod	.\Static_Code\PDD\CMP_PDD.h	671;"	d
CMP_PDD_SetHysteresis	.\Static_Code\PDD\CMP_PDD.h	319;"	d
CMP_PDD_SetInterruptMask	.\Static_Code\PDD\CMP_PDD.h	221;"	d
CMP_PDD_SetNegativeInput	.\Static_Code\PDD\CMP_PDD.h	900;"	d
CMP_PDD_SetPositiveInput	.\Static_Code\PDD\CMP_PDD.h	945;"	d
CMP_PDD_SetPowerMode	.\Static_Code\PDD\CMP_PDD.h	541;"	d
CMP_PDD_SetReference	.\Static_Code\PDD\CMP_PDD.h	814;"	d
CMP_PDD_SetVoltage	.\Static_Code\PDD\CMP_PDD.h	770;"	d
CMP_PDD_UNFILTERED_OUTPUT	.\Static_Code\PDD\CMP_PDD.h	72;"	d
CMP_PDD_V_REF_INPUT_1	.\Static_Code\PDD\CMP_PDD.h	87;"	d
CMP_PDD_V_REF_INPUT_2	.\Static_Code\PDD\CMP_PDD.h	88;"	d
CMP_SCR_CFF_MASK	.\Static_Code\IO_Map\MC56F82748.h	1590;"	d
CMP_SCR_CFF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1591;"	d
CMP_SCR_CFR_MASK	.\Static_Code\IO_Map\MC56F82748.h	1592;"	d
CMP_SCR_CFR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1593;"	d
CMP_SCR_COUT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1588;"	d
CMP_SCR_COUT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1589;"	d
CMP_SCR_IEF_MASK	.\Static_Code\IO_Map\MC56F82748.h	1594;"	d
CMP_SCR_IEF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1595;"	d
CMP_SCR_IER_MASK	.\Static_Code\IO_Map\MC56F82748.h	1596;"	d
CMP_SCR_IER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1597;"	d
CMP_SCR_REG	.\Static_Code\IO_Map\MC56F82748.h	1543;"	d
CM_MODE	.\Project_Settings\Startup_Code\56F83x_init.asm	/^CM_MODE                                                          EQU  $0100$/;"	d
CNT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CNT;                                    \/**< Counter Register, array offset: 0x0, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CNTR	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CNTR;                                   \/**< Timer Channel Counter Register, array offset: 0x5, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
CNTR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CNTR;                                   \/**< COP Counter Register, offset: 0x2 *\/$/;"	m	struct:COP_MemMap
CNTR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CNTR;                                   \/**< PIT Counter Register, offset: 0x2 *\/$/;"	m	struct:PIT_MemMap
COMP1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t COMP1;                                  \/**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
COMP2	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t COMP2;                                  \/**< Timer Channel Compare Register 2, array offset: 0x1, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
COP_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1773;"	d
COP_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	1775;"	d
COP_CNTR	.\Static_Code\IO_Map\MC56F82748.h	1791;"	d
COP_CNTR_COUNT_SERVICE	.\Static_Code\IO_Map\MC56F82748.h	1756;"	d
COP_CNTR_COUNT_SERVICE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1754;"	d
COP_CNTR_COUNT_SERVICE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1755;"	d
COP_CNTR_REG	.\Static_Code\IO_Map\MC56F82748.h	1712;"	d
COP_CTRL	.\Static_Code\IO_Map\MC56F82748.h	1789;"	d
COP_CTRL_CEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1733;"	d
COP_CTRL_CEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1734;"	d
COP_CTRL_CLKSEL	.\Static_Code\IO_Map\MC56F82748.h	1743;"	d
COP_CTRL_CLKSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1741;"	d
COP_CTRL_CLKSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1742;"	d
COP_CTRL_CLOREN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1739;"	d
COP_CTRL_CLOREN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1740;"	d
COP_CTRL_CSEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1737;"	d
COP_CTRL_CSEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1738;"	d
COP_CTRL_CWEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1735;"	d
COP_CTRL_CWEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1736;"	d
COP_CTRL_CWP_MASK	.\Static_Code\IO_Map\MC56F82748.h	1731;"	d
COP_CTRL_CWP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1732;"	d
COP_CTRL_INTEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1744;"	d
COP_CTRL_INTEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1745;"	d
COP_CTRL_PSS	.\Static_Code\IO_Map\MC56F82748.h	1748;"	d
COP_CTRL_PSS_MASK	.\Static_Code\IO_Map\MC56F82748.h	1746;"	d
COP_CTRL_PSS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1747;"	d
COP_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	1710;"	d
COP_INTVAL	.\Static_Code\IO_Map\MC56F82748.h	1792;"	d
COP_INTVAL_INTERRUPT_VALUE	.\Static_Code\IO_Map\MC56F82748.h	1760;"	d
COP_INTVAL_INTERRUPT_VALUE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1758;"	d
COP_INTVAL_INTERRUPT_VALUE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1759;"	d
COP_INTVAL_REG	.\Static_Code\IO_Map\MC56F82748.h	1713;"	d
COP_Init	.\Static_Code\Peripherals\COP_Init.c	/^void COP_Init(void) {$/;"	f
COP_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct COP_MemMap {$/;"	s
COP_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *COP_MemMapPtr;$/;"	t
COP_PDD_DIVIDE_1	.\Static_Code\PDD\COP_PDD.h	41;"	d
COP_PDD_DIVIDE_1024	.\Static_Code\PDD\COP_PDD.h	44;"	d
COP_PDD_DIVIDE_16	.\Static_Code\PDD\COP_PDD.h	42;"	d
COP_PDD_DIVIDE_256	.\Static_Code\PDD\COP_PDD.h	43;"	d
COP_PDD_DisableInterrupt	.\Static_Code\PDD\COP_PDD.h	277;"	d
COP_PDD_EnableDevice	.\Static_Code\PDD\COP_PDD.h	110;"	d
COP_PDD_EnableInterrupt	.\Static_Code\PDD\COP_PDD.h	259;"	d
COP_PDD_EnableLossOfReference	.\Static_Code\PDD\COP_PDD.h	197;"	d
COP_PDD_EnableStopMode	.\Static_Code\PDD\COP_PDD.h	174;"	d
COP_PDD_EnableWaitMode	.\Static_Code\PDD\COP_PDD.h	151;"	d
COP_PDD_EnableWriteProtect	.\Static_Code\PDD\COP_PDD.h	71;"	d
COP_PDD_GetEnableDeviceStatus	.\Static_Code\PDD\COP_PDD.h	130;"	d
COP_PDD_GetInterruptMask	.\Static_Code\PDD\COP_PDD.h	241;"	d
COP_PDD_GetWriteProtectStatus	.\Static_Code\PDD\COP_PDD.h	89;"	d
COP_PDD_H_	.\Static_Code\PDD\COP_PDD.h	9;"	d
COP_PDD_KEY_1	.\Static_Code\PDD\COP_PDD.h	47;"	d
COP_PDD_KEY_2	.\Static_Code\PDD\COP_PDD.h	48;"	d
COP_PDD_ReadControlReg	.\Static_Code\PDD\COP_PDD.h	338;"	d
COP_PDD_ReadCounterReg	.\Static_Code\PDD\COP_PDD.h	413;"	d
COP_PDD_ReadInterruptValueReg	.\Static_Code\PDD\COP_PDD.h	451;"	d
COP_PDD_ReadTimeoutReg	.\Static_Code\PDD\COP_PDD.h	376;"	d
COP_PDD_ReadWindowTimeoutReg	.\Static_Code\PDD\COP_PDD.h	489;"	d
COP_PDD_SOURCE_BUS_CLK	.\Static_Code\PDD\COP_PDD.h	53;"	d
COP_PDD_SOURCE_ROSC_200K	.\Static_Code\PDD\COP_PDD.h	54;"	d
COP_PDD_SOURCE_ROSC_8M	.\Static_Code\PDD\COP_PDD.h	51;"	d
COP_PDD_SOURCE_XTAL_OSC	.\Static_Code\PDD\COP_PDD.h	52;"	d
COP_PDD_SelectClockSource	.\Static_Code\PDD\COP_PDD.h	219;"	d
COP_PDD_SetPrescaler	.\Static_Code\PDD\COP_PDD.h	296;"	d
COP_PDD_WriteControlReg	.\Static_Code\PDD\COP_PDD.h	320;"	d
COP_PDD_WriteInterruptValueReg	.\Static_Code\PDD\COP_PDD.h	433;"	d
COP_PDD_WriteServiceReg	.\Static_Code\PDD\COP_PDD.h	395;"	d
COP_PDD_WriteTimeoutReg	.\Static_Code\PDD\COP_PDD.h	358;"	d
COP_PDD_WriteWindowTimeoutReg	.\Static_Code\PDD\COP_PDD.h	471;"	d
COP_TOUT	.\Static_Code\IO_Map\MC56F82748.h	1790;"	d
COP_TOUT_REG	.\Static_Code\IO_Map\MC56F82748.h	1711;"	d
COP_TOUT_TIMEOUT	.\Static_Code\IO_Map\MC56F82748.h	1752;"	d
COP_TOUT_TIMEOUT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1750;"	d
COP_TOUT_TIMEOUT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1751;"	d
COP_WINDOW	.\Static_Code\IO_Map\MC56F82748.h	1793;"	d
COP_WINDOW_REG	.\Static_Code\IO_Map\MC56F82748.h	1714;"	d
COP_WINDOW_WINDOW_VALUE	.\Static_Code\IO_Map\MC56F82748.h	1764;"	d
COP_WINDOW_WINDOW_VALUE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1762;"	d
COP_WINDOW_WINDOW_VALUE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1763;"	d
CPCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t CPCR;                                   \/**< Core control register, offset: 0xC *\/$/;"	m	struct:MCM_MemMap
CPP_DEPS	.\FLASH_SDM\sources.mk	/^CPP_DEPS := $/;"	m
CPP_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^CPP_DEPS_OS_FORMAT := $/;"	m
CPP_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^CPP_DEPS_QUOTED := $/;"	m
CPP_SRCS	.\FLASH_SDM\sources.mk	/^CPP_SRCS := $/;"	m
CPP_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^CPP_SRCS_OS_FORMAT := $/;"	m
CPP_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^CPP_SRCS_QUOTED := $/;"	m
CPU_AFTER_RESET_VALUES	.\Generated_Code\CPU_Config.h	112;"	d
CPU_BANDGAP_TRIM	.\Generated_Code\CPU_Config.h	327;"	d
CPU_BANDGAP_TRIM_VALUE	.\Generated_Code\CPU_Config.h	329;"	d
CPU_BOOT_ISR_INIT	.\Generated_Code\Vectors_Config.h	63;"	d
CPU_BUS_CLK_HZ	.\Generated_Code\Cpu.h	92;"	d
CPU_BUS_CLK_HZ_CLOCK_CONFIG0	.\Generated_Code\Cpu.h	96;"	d
CPU_BUS_CLK_HZ_CONFIG_0	.\Generated_Code\Cpu.h	105;"	d
CPU_CLOCK_CONFIGURATIONS_NUMBER	.\Generated_Code\CPU_Config.h	106;"	d
CPU_CLOCK_CONFIGURATION_0	.\Generated_Code\CPU_Config.h	107;"	d
CPU_CLOCK_CONFIG_0	.\Generated_Code\Cpu.h	102;"	d
CPU_CLOCK_CONFIG_NUMBER	.\Generated_Code\Cpu.h	93;"	d
CPU_CLOCK_SOURCE_EXTERNAL	.\Generated_Code\CPU_Config.h	/^  CPU_CLOCK_SOURCE_EXTERNAL$/;"	e	enum:__anon3
CPU_CLOCK_SOURCE_INTERNAL_FAST	.\Generated_Code\CPU_Config.h	/^  CPU_CLOCK_SOURCE_INTERNAL_FAST,$/;"	e	enum:__anon3
CPU_CLOCK_SOURCE_INTERNAL_SLOW	.\Generated_Code\CPU_Config.h	/^  CPU_CLOCK_SOURCE_INTERNAL_SLOW,$/;"	e	enum:__anon3
CPU_COMMON_INIT	.\Generated_Code\CPU_Config.h	354;"	d
CPU_COMPONENTS_INIT	.\Generated_Code\CPU_Config.h	362;"	d
CPU_CORE_CLK_HZ_CONFIG_0	.\Generated_Code\Cpu.h	103;"	d
CPU_DELAY_100US	.\Generated_Code\CPU_Config.h	78;"	d
CPU_DELAY_100US_CLOCK_CONFIG_0_LOOP_1	.\Generated_Code\CPU_Config.h	401;"	d
CPU_DERIVATIVE_MC56F82748VLH	.\Generated_Code\Cpu.h	124;"	d
CPU_DIRECT_ISR_ADDR_0	.\Generated_Code\Vectors_Config.h	71;"	d
CPU_DIRECT_ISR_ADDR_1	.\Generated_Code\Vectors_Config.h	72;"	d
CPU_DISABLE_INT	.\Generated_Code\CPU_Config.h	69;"	d
CPU_Delay100US	.\Static_Code\System\CPU_Init.c	/^asm void CPU_Delay100US(word us100)$/;"	f
CPU_DisableInt	.\Static_Code\System\CPU_Init.h	209;"	d
CPU_ENABLE_INT	.\Generated_Code\CPU_Config.h	68;"	d
CPU_ENABLE_PLL	.\Generated_Code\CPU_Config.h	79;"	d
CPU_EnableInt	.\Static_Code\System\CPU_Init.h	196;"	d
CPU_EnablePLL	.\Static_Code\System\CPU_Init.c	/^void CPU_EnablePLL(void)$/;"	f
CPU_FAMILY_56800	.\Generated_Code\Cpu.h	123;"	d
CPU_GET_BUS_FREQ_HZ	.\Generated_Code\CPU_Config.h	73;"	d
CPU_GET_CLOCK_CONFIGURATION	.\Generated_Code\CPU_Config.h	66;"	d
CPU_GET_RESET_SOURCE	.\Generated_Code\CPU_Config.h	70;"	d
CPU_GetBusFreqHz	.\Static_Code\System\CPU_Init.c	/^uint32_t CPU_GetBusFreqHz(void)$/;"	f
CPU_GetClockConfiguration	.\Static_Code\System\CPU_Init.c	/^LDD_TClockConfiguration CPU_GetClockConfiguration(void)$/;"	f
CPU_GetResetSource	.\Static_Code\System\CPU_Init.h	230;"	d
CPU_INDIRECT_ISR_ADDR_10	.\Generated_Code\Vectors_Config.h	81;"	d
CPU_INDIRECT_ISR_ADDR_100	.\Generated_Code\Vectors_Config.h	171;"	d
CPU_INDIRECT_ISR_ADDR_101	.\Generated_Code\Vectors_Config.h	172;"	d
CPU_INDIRECT_ISR_ADDR_102	.\Generated_Code\Vectors_Config.h	173;"	d
CPU_INDIRECT_ISR_ADDR_103	.\Generated_Code\Vectors_Config.h	174;"	d
CPU_INDIRECT_ISR_ADDR_104	.\Generated_Code\Vectors_Config.h	175;"	d
CPU_INDIRECT_ISR_ADDR_105	.\Generated_Code\Vectors_Config.h	176;"	d
CPU_INDIRECT_ISR_ADDR_106	.\Generated_Code\Vectors_Config.h	177;"	d
CPU_INDIRECT_ISR_ADDR_107	.\Generated_Code\Vectors_Config.h	178;"	d
CPU_INDIRECT_ISR_ADDR_108	.\Generated_Code\Vectors_Config.h	179;"	d
CPU_INDIRECT_ISR_ADDR_109	.\Generated_Code\Vectors_Config.h	180;"	d
CPU_INDIRECT_ISR_ADDR_11	.\Generated_Code\Vectors_Config.h	82;"	d
CPU_INDIRECT_ISR_ADDR_110	.\Generated_Code\Vectors_Config.h	181;"	d
CPU_INDIRECT_ISR_ADDR_12	.\Generated_Code\Vectors_Config.h	83;"	d
CPU_INDIRECT_ISR_ADDR_13	.\Generated_Code\Vectors_Config.h	84;"	d
CPU_INDIRECT_ISR_ADDR_14	.\Generated_Code\Vectors_Config.h	85;"	d
CPU_INDIRECT_ISR_ADDR_15	.\Generated_Code\Vectors_Config.h	86;"	d
CPU_INDIRECT_ISR_ADDR_16	.\Generated_Code\Vectors_Config.h	87;"	d
CPU_INDIRECT_ISR_ADDR_17	.\Generated_Code\Vectors_Config.h	88;"	d
CPU_INDIRECT_ISR_ADDR_18	.\Generated_Code\Vectors_Config.h	89;"	d
CPU_INDIRECT_ISR_ADDR_19	.\Generated_Code\Vectors_Config.h	90;"	d
CPU_INDIRECT_ISR_ADDR_2	.\Generated_Code\Vectors_Config.h	73;"	d
CPU_INDIRECT_ISR_ADDR_20	.\Generated_Code\Vectors_Config.h	91;"	d
CPU_INDIRECT_ISR_ADDR_21	.\Generated_Code\Vectors_Config.h	92;"	d
CPU_INDIRECT_ISR_ADDR_22	.\Generated_Code\Vectors_Config.h	93;"	d
CPU_INDIRECT_ISR_ADDR_23	.\Generated_Code\Vectors_Config.h	94;"	d
CPU_INDIRECT_ISR_ADDR_24	.\Generated_Code\Vectors_Config.h	95;"	d
CPU_INDIRECT_ISR_ADDR_25	.\Generated_Code\Vectors_Config.h	96;"	d
CPU_INDIRECT_ISR_ADDR_26	.\Generated_Code\Vectors_Config.h	97;"	d
CPU_INDIRECT_ISR_ADDR_27	.\Generated_Code\Vectors_Config.h	98;"	d
CPU_INDIRECT_ISR_ADDR_28	.\Generated_Code\Vectors_Config.h	99;"	d
CPU_INDIRECT_ISR_ADDR_29	.\Generated_Code\Vectors_Config.h	100;"	d
CPU_INDIRECT_ISR_ADDR_3	.\Generated_Code\Vectors_Config.h	74;"	d
CPU_INDIRECT_ISR_ADDR_30	.\Generated_Code\Vectors_Config.h	101;"	d
CPU_INDIRECT_ISR_ADDR_31	.\Generated_Code\Vectors_Config.h	102;"	d
CPU_INDIRECT_ISR_ADDR_32	.\Generated_Code\Vectors_Config.h	103;"	d
CPU_INDIRECT_ISR_ADDR_33	.\Generated_Code\Vectors_Config.h	104;"	d
CPU_INDIRECT_ISR_ADDR_34	.\Generated_Code\Vectors_Config.h	105;"	d
CPU_INDIRECT_ISR_ADDR_35	.\Generated_Code\Vectors_Config.h	106;"	d
CPU_INDIRECT_ISR_ADDR_36	.\Generated_Code\Vectors_Config.h	107;"	d
CPU_INDIRECT_ISR_ADDR_37	.\Generated_Code\Vectors_Config.h	108;"	d
CPU_INDIRECT_ISR_ADDR_38	.\Generated_Code\Vectors_Config.h	109;"	d
CPU_INDIRECT_ISR_ADDR_39	.\Generated_Code\Vectors_Config.h	110;"	d
CPU_INDIRECT_ISR_ADDR_4	.\Generated_Code\Vectors_Config.h	75;"	d
CPU_INDIRECT_ISR_ADDR_40	.\Generated_Code\Vectors_Config.h	111;"	d
CPU_INDIRECT_ISR_ADDR_41	.\Generated_Code\Vectors_Config.h	112;"	d
CPU_INDIRECT_ISR_ADDR_42	.\Generated_Code\Vectors_Config.h	113;"	d
CPU_INDIRECT_ISR_ADDR_43	.\Generated_Code\Vectors_Config.h	114;"	d
CPU_INDIRECT_ISR_ADDR_44	.\Generated_Code\Vectors_Config.h	115;"	d
CPU_INDIRECT_ISR_ADDR_45	.\Generated_Code\Vectors_Config.h	116;"	d
CPU_INDIRECT_ISR_ADDR_46	.\Generated_Code\Vectors_Config.h	117;"	d
CPU_INDIRECT_ISR_ADDR_47	.\Generated_Code\Vectors_Config.h	118;"	d
CPU_INDIRECT_ISR_ADDR_48	.\Generated_Code\Vectors_Config.h	119;"	d
CPU_INDIRECT_ISR_ADDR_49	.\Generated_Code\Vectors_Config.h	120;"	d
CPU_INDIRECT_ISR_ADDR_5	.\Generated_Code\Vectors_Config.h	76;"	d
CPU_INDIRECT_ISR_ADDR_50	.\Generated_Code\Vectors_Config.h	121;"	d
CPU_INDIRECT_ISR_ADDR_51	.\Generated_Code\Vectors_Config.h	122;"	d
CPU_INDIRECT_ISR_ADDR_52	.\Generated_Code\Vectors_Config.h	123;"	d
CPU_INDIRECT_ISR_ADDR_53	.\Generated_Code\Vectors_Config.h	124;"	d
CPU_INDIRECT_ISR_ADDR_54	.\Generated_Code\Vectors_Config.h	125;"	d
CPU_INDIRECT_ISR_ADDR_55	.\Generated_Code\Vectors_Config.h	126;"	d
CPU_INDIRECT_ISR_ADDR_56	.\Generated_Code\Vectors_Config.h	127;"	d
CPU_INDIRECT_ISR_ADDR_57	.\Generated_Code\Vectors_Config.h	128;"	d
CPU_INDIRECT_ISR_ADDR_58	.\Generated_Code\Vectors_Config.h	129;"	d
CPU_INDIRECT_ISR_ADDR_59	.\Generated_Code\Vectors_Config.h	130;"	d
CPU_INDIRECT_ISR_ADDR_6	.\Generated_Code\Vectors_Config.h	77;"	d
CPU_INDIRECT_ISR_ADDR_60	.\Generated_Code\Vectors_Config.h	131;"	d
CPU_INDIRECT_ISR_ADDR_61	.\Generated_Code\Vectors_Config.h	132;"	d
CPU_INDIRECT_ISR_ADDR_62	.\Generated_Code\Vectors_Config.h	133;"	d
CPU_INDIRECT_ISR_ADDR_63	.\Generated_Code\Vectors_Config.h	134;"	d
CPU_INDIRECT_ISR_ADDR_64	.\Generated_Code\Vectors_Config.h	135;"	d
CPU_INDIRECT_ISR_ADDR_65	.\Generated_Code\Vectors_Config.h	136;"	d
CPU_INDIRECT_ISR_ADDR_66	.\Generated_Code\Vectors_Config.h	137;"	d
CPU_INDIRECT_ISR_ADDR_67	.\Generated_Code\Vectors_Config.h	138;"	d
CPU_INDIRECT_ISR_ADDR_68	.\Generated_Code\Vectors_Config.h	139;"	d
CPU_INDIRECT_ISR_ADDR_69	.\Generated_Code\Vectors_Config.h	140;"	d
CPU_INDIRECT_ISR_ADDR_7	.\Generated_Code\Vectors_Config.h	78;"	d
CPU_INDIRECT_ISR_ADDR_70	.\Generated_Code\Vectors_Config.h	141;"	d
CPU_INDIRECT_ISR_ADDR_71	.\Generated_Code\Vectors_Config.h	142;"	d
CPU_INDIRECT_ISR_ADDR_72	.\Generated_Code\Vectors_Config.h	143;"	d
CPU_INDIRECT_ISR_ADDR_73	.\Generated_Code\Vectors_Config.h	144;"	d
CPU_INDIRECT_ISR_ADDR_74	.\Generated_Code\Vectors_Config.h	145;"	d
CPU_INDIRECT_ISR_ADDR_75	.\Generated_Code\Vectors_Config.h	146;"	d
CPU_INDIRECT_ISR_ADDR_76	.\Generated_Code\Vectors_Config.h	147;"	d
CPU_INDIRECT_ISR_ADDR_77	.\Generated_Code\Vectors_Config.h	148;"	d
CPU_INDIRECT_ISR_ADDR_78	.\Generated_Code\Vectors_Config.h	149;"	d
CPU_INDIRECT_ISR_ADDR_79	.\Generated_Code\Vectors_Config.h	150;"	d
CPU_INDIRECT_ISR_ADDR_8	.\Generated_Code\Vectors_Config.h	79;"	d
CPU_INDIRECT_ISR_ADDR_80	.\Generated_Code\Vectors_Config.h	151;"	d
CPU_INDIRECT_ISR_ADDR_81	.\Generated_Code\Vectors_Config.h	152;"	d
CPU_INDIRECT_ISR_ADDR_82	.\Generated_Code\Vectors_Config.h	153;"	d
CPU_INDIRECT_ISR_ADDR_83	.\Generated_Code\Vectors_Config.h	154;"	d
CPU_INDIRECT_ISR_ADDR_84	.\Generated_Code\Vectors_Config.h	155;"	d
CPU_INDIRECT_ISR_ADDR_85	.\Generated_Code\Vectors_Config.h	156;"	d
CPU_INDIRECT_ISR_ADDR_86	.\Generated_Code\Vectors_Config.h	157;"	d
CPU_INDIRECT_ISR_ADDR_87	.\Generated_Code\Vectors_Config.h	158;"	d
CPU_INDIRECT_ISR_ADDR_88	.\Generated_Code\Vectors_Config.h	159;"	d
CPU_INDIRECT_ISR_ADDR_89	.\Generated_Code\Vectors_Config.h	160;"	d
CPU_INDIRECT_ISR_ADDR_9	.\Generated_Code\Vectors_Config.h	80;"	d
CPU_INDIRECT_ISR_ADDR_90	.\Generated_Code\Vectors_Config.h	161;"	d
CPU_INDIRECT_ISR_ADDR_91	.\Generated_Code\Vectors_Config.h	162;"	d
CPU_INDIRECT_ISR_ADDR_92	.\Generated_Code\Vectors_Config.h	163;"	d
CPU_INDIRECT_ISR_ADDR_93	.\Generated_Code\Vectors_Config.h	164;"	d
CPU_INDIRECT_ISR_ADDR_94	.\Generated_Code\Vectors_Config.h	165;"	d
CPU_INDIRECT_ISR_ADDR_95	.\Generated_Code\Vectors_Config.h	166;"	d
CPU_INDIRECT_ISR_ADDR_96	.\Generated_Code\Vectors_Config.h	167;"	d
CPU_INDIRECT_ISR_ADDR_97	.\Generated_Code\Vectors_Config.h	168;"	d
CPU_INDIRECT_ISR_ADDR_98	.\Generated_Code\Vectors_Config.h	169;"	d
CPU_INDIRECT_ISR_ADDR_99	.\Generated_Code\Vectors_Config.h	170;"	d
CPU_INIT_SHADOW_REGS	.\Generated_Code\CPU_Config.h	77;"	d
CPU_INTC_VBA_VALUE	.\Generated_Code\CPU_Config.h	275;"	d
CPU_INT_FAST_CLK_HZ	.\Generated_Code\Cpu.h	99;"	d
CPU_INT_PRIORITY	.\Generated_Code\CPU_Config.h	350;"	d
CPU_INT_VECTOR_ROM	.\Generated_Code\Vectors_Config.h	62;"	d
CPU_InitShadowRegs	.\Static_Code\System\CPU_Init.c	/^asm void CPU_InitShadowRegs(TShadowRegs *Shadow)$/;"	f
CPU_LITTLE_ENDIAN	.\Generated_Code\Cpu.h	126;"	d
CPU_OPEN_BACKDOOR	.\Generated_Code\CPU_Config.h	74;"	d
CPU_OpenBackDoor	.\Static_Code\System\CPU_Init.c	/^LDD_TError CPU_OpenBackDoor(LDD_TBackDoorKey *KeyPtr)$/;"	f
CPU_PARTNUM_MC56F82748VLH	.\Generated_Code\Cpu.h	125;"	d
CPU_PERIPHERALS_INIT	.\Generated_Code\CPU_Config.h	358;"	d
CPU_PLL_CLK_HZ_CONFIG_0	.\Generated_Code\Cpu.h	106;"	d
CPU_RESET_PIN	.\Generated_Code\CPU_Config.h	334;"	d
CPU_SATURATION	.\Generated_Code\CPU_Config.h	299;"	d
CPU_SET_CLOCK_CONFIGURATION	.\Generated_Code\CPU_Config.h	65;"	d
CPU_SET_FLEX_NVM_PARTITION	.\Generated_Code\CPU_Config.h	76;"	d
CPU_SET_FLEX_RAM_FUNCTION	.\Generated_Code\CPU_Config.h	75;"	d
CPU_SET_OPERATION_MODE	.\Generated_Code\CPU_Config.h	67;"	d
CPU_SET_STOP_MODE	.\Generated_Code\CPU_Config.h	72;"	d
CPU_SET_WAIT_MODE	.\Generated_Code\CPU_Config.h	71;"	d
CPU_SHADOW_M01_VALUE	.\Generated_Code\CPU_Config.h	322;"	d
CPU_SHADOW_N3_VALUE	.\Generated_Code\CPU_Config.h	321;"	d
CPU_SHADOW_N_VALUE	.\Generated_Code\CPU_Config.h	320;"	d
CPU_SHADOW_R0_VALUE	.\Generated_Code\CPU_Config.h	314;"	d
CPU_SHADOW_R1_VALUE	.\Generated_Code\CPU_Config.h	315;"	d
CPU_SHADOW_R2_VALUE	.\Generated_Code\CPU_Config.h	316;"	d
CPU_SHADOW_R3_VALUE	.\Generated_Code\CPU_Config.h	317;"	d
CPU_SHADOW_R4_VALUE	.\Generated_Code\CPU_Config.h	318;"	d
CPU_SHADOW_R5_VALUE	.\Generated_Code\CPU_Config.h	319;"	d
CPU_SHADOW_REGISTERS	.\Generated_Code\CPU_Config.h	313;"	d
CPU_SYSTEM_CLK_HZ_CONFIG_0	.\Generated_Code\Cpu.h	104;"	d
CPU_SetClockConfiguration	.\Static_Code\System\CPU_Init.c	/^LDD_TError CPU_SetClockConfiguration(LDD_TClockConfiguration ModeID)$/;"	f
CPU_SetFlexNVMPartition	.\Static_Code\System\CPU_Init.c	/^LDD_TError CPU_SetFlexNVMPartition(void)$/;"	f
CPU_SetFlexRAMFunction	.\Static_Code\System\CPU_Init.c	/^LDD_TError CPU_SetFlexRAMFunction(LDD_TFlexRAMFunction Function)$/;"	f
CPU_SetOperationMode	.\Static_Code\System\CPU_Init.c	/^LDD_TError CPU_SetOperationMode(LDD_TDriverOperationMode OperationMode, LDD_TCallback ModeChangeCallback, LDD_TCallbackParam *ModeChangeCallbackParamPtr)$/;"	f
CPU_SetStopMode	.\Static_Code\System\CPU_Init.h	261;"	d
CPU_SetWaitMode	.\Static_Code\System\CPU_Init.h	246;"	d
CPU_TCK_PIN	.\Generated_Code\CPU_Config.h	343;"	d
CPU_TDI_PIN	.\Generated_Code\CPU_Config.h	339;"	d
CPU_TDO_PIN	.\Generated_Code\CPU_Config.h	341;"	d
CPU_TMS_PIN	.\Generated_Code\CPU_Config.h	345;"	d
CPU_UNUSED_PINS_DIRECTION	.\Generated_Code\CPU_Config.h	294;"	d
CPU_UNUSED_PINS_GPIOA	.\Generated_Code\CPU_Config.h	287;"	d
CPU_UNUSED_PINS_GPIOB	.\Generated_Code\CPU_Config.h	288;"	d
CPU_UNUSED_PINS_GPIOC	.\Generated_Code\CPU_Config.h	289;"	d
CPU_UNUSED_PINS_GPIOD	.\Generated_Code\CPU_Config.h	290;"	d
CPU_UNUSED_PINS_GPIOE	.\Generated_Code\CPU_Config.h	291;"	d
CPU_UNUSED_PINS_GPIOF	.\Generated_Code\CPU_Config.h	292;"	d
CPU_UNUSED_PINS_INIT	.\Generated_Code\CPU_Config.h	285;"	d
CPU_VECTOR_BASE_ADDRESS	.\Generated_Code\CPU_Config.h	274;"	d
CPU_XTAL_CLK_HZ_CONFIG_0	.\Generated_Code\Cpu.h	107;"	d
CR0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CR0;                                    \/**< CMP Control Register 0, offset: 0x0 *\/$/;"	m	struct:CMP_MemMap
CR1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CR1;                                    \/**< CMP Control Register 1, offset: 0x1 *\/$/;"	m	struct:CMP_MemMap
CRCH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CRCH;                                   \/**< CRC High Register, offset: 0x0 *\/$/;"	m	struct:CRC_MemMap
CRCL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CRCL;                                   \/**< CRC Low Register, offset: 0x1 *\/$/;"	m	struct:CRC_MemMap
CRC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	1870;"	d
CRC_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	1872;"	d
CRC_CRCH	.\Static_Code\IO_Map\MC56F82748.h	1886;"	d
CRC_CRCH_CRCH	.\Static_Code\IO_Map\MC56F82748.h	1853;"	d
CRC_CRCH_CRCH_MASK	.\Static_Code\IO_Map\MC56F82748.h	1851;"	d
CRC_CRCH_CRCH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1852;"	d
CRC_CRCH_REG	.\Static_Code\IO_Map\MC56F82748.h	1832;"	d
CRC_CRCL	.\Static_Code\IO_Map\MC56F82748.h	1887;"	d
CRC_CRCL_CRCL	.\Static_Code\IO_Map\MC56F82748.h	1857;"	d
CRC_CRCL_CRCL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1855;"	d
CRC_CRCL_CRCL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1856;"	d
CRC_CRCL_REG	.\Static_Code\IO_Map\MC56F82748.h	1833;"	d
CRC_Init	.\Static_Code\Peripherals\CRC_Init.c	/^void CRC_Init(void) {$/;"	f
CRC_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct CRC_MemMap {$/;"	s
CRC_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *CRC_MemMapPtr;$/;"	t
CRC_PDD_GetCRCDataLLRegister	.\Static_Code\PDD\CRC_PDD.h	162;"	d
CRC_PDD_GetCRCHighRegister	.\Static_Code\PDD\CRC_PDD.h	238;"	d
CRC_PDD_GetCRCLowRegister	.\Static_Code\PDD\CRC_PDD.h	200;"	d
CRC_PDD_GetTransposeRegister	.\Static_Code\PDD\CRC_PDD.h	99;"	d
CRC_PDD_H_	.\Static_Code\PDD\CRC_PDD.h	9;"	d
CRC_PDD_SetCRCDataLLRegister	.\Static_Code\PDD\CRC_PDD.h	144;"	d
CRC_PDD_SetCRCHighRegister	.\Static_Code\PDD\CRC_PDD.h	220;"	d
CRC_PDD_SetCRCLowRegister	.\Static_Code\PDD\CRC_PDD.h	182;"	d
CRC_PDD_SetSeedLow	.\Static_Code\PDD\CRC_PDD.h	120;"	d
CRC_PDD_SetTransposeRegister	.\Static_Code\PDD\CRC_PDD.h	81;"	d
CRC_PDD_Transpose	.\Static_Code\PDD\CRC_PDD.h	57;"	d
CRC_TRANSPOSE	.\Static_Code\IO_Map\MC56F82748.h	1888;"	d
CRC_TRANSPOSE_REG	.\Static_Code\IO_Map\MC56F82748.h	1834;"	d
CRC_TRANSPOSE_TRANSPOSE	.\Static_Code\IO_Map\MC56F82748.h	1861;"	d
CRC_TRANSPOSE_TRANSPOSE_MASK	.\Static_Code\IO_Map\MC56F82748.h	1859;"	d
CRC_TRANSPOSE_TRANSPOSE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1860;"	d
CSCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CSCTRL;                                 \/**< Timer Channel Comparator Status and Control Register, array offset: 0xA, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
CTL0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTL0;                                   \/**< MSCAN Control Register 0, offset: 0x0 *\/$/;"	m	struct:CAN_MemMap
CTL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTL1;                                   \/**< MSCAN Control Register 1, offset: 0x1 *\/$/;"	m	struct:CAN_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CTRL;                                   \/**< Control Register, array offset: 0x3, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CTRL;                                   \/**< Timer Channel Control Register, array offset: 0x6, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< COP Control Register, offset: 0x0 *\/$/;"	m	struct:COP_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< Control Register, offset: 0x0 *\/$/;"	m	struct:EWM_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< Control Register, offset: 0x0 *\/$/;"	m	struct:PMC_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< Control Register, offset: 0x0 *\/$/;"	m	struct:SIM_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< Control Register, offset: 0x1B *\/$/;"	m	struct:INTC_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< PIT Control Register, offset: 0x0 *\/$/;"	m	struct:PIT_MemMap
CTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL;                                   \/**< PLL Control Register, offset: 0x0 *\/$/;"	m	struct:OCCS_MemMap
CTRL0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL0;                                  \/**< Control Register 0, offset: 0x0 *\/$/;"	m	struct:DAC_MemMap
CTRL0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL0;                                  \/**< Crossbar A Control Register 0, offset: 0x15 *\/$/;"	m	struct:XBARA_MemMap
CTRL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL1;                                  \/**< ADC Control Register 1, offset: 0x0 *\/$/;"	m	struct:ADC_MemMap
CTRL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL1;                                  \/**< Control Register 1, offset: 0x6 *\/$/;"	m	struct:DAC_MemMap
CTRL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL1;                                  \/**< Crossbar A Control Register 1, offset: 0x16 *\/$/;"	m	struct:XBARA_MemMap
CTRL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL1;                                  \/**< QSCI Control Register 1, offset: 0x1 *\/$/;"	m	struct:QSCI_MemMap
CTRL2	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CTRL2;                                  \/**< Control 2 Register, array offset: 0x2, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CTRL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL2;                                  \/**< ADC Control Register 2, offset: 0x1 *\/$/;"	m	struct:ADC_MemMap
CTRL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL2;                                  \/**< QSCI Control Register 2, offset: 0x2 *\/$/;"	m	struct:QSCI_MemMap
CTRL3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL3;                                  \/**< ADC Control Register 3, offset: 0x54 *\/$/;"	m	struct:ADC_MemMap
CTRL3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t CTRL3;                                  \/**< QSCI Control Register 3, offset: 0x5 *\/$/;"	m	struct:QSCI_MemMap
CVAL0	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL0;                                  \/**< Capture Value 0 Register, array offset: 0x20, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL0CYC;                               \/**< Capture Value 0 Cycle Register, array offset: 0x21, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL1;                                  \/**< Capture Value 1 Register, array offset: 0x22, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL1CYC;                               \/**< Capture Value 1 Cycle Register, array offset: 0x23, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL2	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL2;                                  \/**< Capture Value 2 Register, array offset: 0x24, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL2CYC;                               \/**< Capture Value 2 Cycle Register, array offset: 0x25, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL3	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL3;                                  \/**< Capture Value 3 Register, array offset: 0x26, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL3CYC;                               \/**< Capture Value 3 Cycle Register, array offset: 0x27, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL4	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL4;                                  \/**< Capture Value 4 Register, array offset: 0x28, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL4CYC;                               \/**< Capture Value 4 Cycle Register, array offset: 0x29, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL5	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL5;                                  \/**< Capture Value 5 Register, array offset: 0x2A, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t CVAL5CYC;                               \/**< Capture Value 5 Cycle Register, array offset: 0x2B, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
CXX_DEPS	.\FLASH_SDM\sources.mk	/^CXX_DEPS := $/;"	m
CXX_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^CXX_DEPS_OS_FORMAT := $/;"	m
CXX_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^CXX_DEPS_QUOTED := $/;"	m
CXX_SRCS	.\FLASH_SDM\sources.mk	/^CXX_SRCS := $/;"	m
CXX_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^CXX_SRCS_OS_FORMAT := $/;"	m
CXX_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^CXX_SRCS_QUOTED := $/;"	m
C_DEPS	.\FLASH_SDM\sources.mk	/^C_DEPS := $/;"	m
C_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^C_DEPS_OS_FORMAT := $/;"	m
C_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^C_DEPS_QUOTED := $/;"	m
C_SRCS	.\FLASH_SDM\sources.mk	/^C_SRCS := $/;"	m
C_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^C_SRCS_OS_FORMAT := $/;"	m
C_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^C_SRCS_QUOTED := $/;"	m
C_UPPER_DEPS	.\FLASH_SDM\sources.mk	/^C_UPPER_DEPS := $/;"	m
C_UPPER_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^C_UPPER_DEPS_OS_FORMAT := $/;"	m
C_UPPER_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^C_UPPER_DEPS_QUOTED := $/;"	m
C_UPPER_SRCS	.\FLASH_SDM\sources.mk	/^C_UPPER_SRCS := $/;"	m
C_UPPER_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^C_UPPER_SRCS_OS_FORMAT := $/;"	m
C_UPPER_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^C_UPPER_SRCS_QUOTED := $/;"	m
Channel0_31PinMask	.\Generated_Code\PE_LDD.h	/^  uint32_t Channel0_31PinMask;         \/*!< Channel pin mask for channels 0 through 31 *\/$/;"	m	struct:__anon42
ChannelIdx	.\Generated_Code\PE_LDD.h	/^  uint8_t ChannelIdx;                  \/*!< Channel index *\/$/;"	m	struct:__anon44
ClockConfigurationID	.\Static_Code\System\CPU_Init.c	/^LDD_TClockConfiguration ClockConfigurationID = CPU_CLOCK_CONFIGURATION_0; \/* Active clock configuration *\/$/;"	v
Common_Init	.\Generated_Code\Cpu.c	/^void Common_Init(void)$/;"	f
Components_Init	.\Generated_Code\Cpu.c	/^void Components_Init(void)$/;"	f
CpuBusFreqHz	.\Generated_Code\CPU_Config.h	/^static const TCpuBusFreqHz CpuBusFreqHz[CPU_CLOCK_CONFIGURATIONS_NUMBER] = {$/;"	v
CpuClockDividers	.\Generated_Code\CPU_Config.h	/^static const TCpuClockDivider CpuClockDividers[CPU_CLOCK_CONFIGURATIONS_NUMBER] = {$/;"	v
CpuClockRates	.\Generated_Code\CPU_Config.h	/^static const TCpuClockRate CpuClockRates[CPU_CLOCK_CONFIGURATIONS_NUMBER] = {$/;"	v
CpuClockSources	.\Generated_Code\CPU_Config.h	/^static TCpuClockSource CpuClockSources[CPU_CLOCK_CONFIGURATIONS_NUMBER] = {$/;"	v
CpuNumberOfPllChecks	.\Generated_Code\CPU_Config.h	/^static const TCpuNumberOfPllChecks CpuNumberOfPllChecks[CPU_CLOCK_CONFIGURATIONS_NUMBER] = {$/;"	v
CpuPllEnabled	.\Generated_Code\CPU_Config.h	/^static const TCpuPllEnabled CpuPllEnabled[CPU_CLOCK_CONFIGURATIONS_NUMBER] = {$/;"	v
CpuUnhandledInterrupt	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt(void)$/;"	f	file:
CpuUnhandledInterrupt0	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt0(void)$/;"	f	file:
CpuUnhandledInterrupt1	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt1(void)$/;"	f	file:
CpuUnhandledInterrupt10	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt10(void)$/;"	f	file:
CpuUnhandledInterrupt100	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt100(void)$/;"	f	file:
CpuUnhandledInterrupt101	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt101(void)$/;"	f	file:
CpuUnhandledInterrupt102	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt102(void)$/;"	f	file:
CpuUnhandledInterrupt103	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt103(void)$/;"	f	file:
CpuUnhandledInterrupt104	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt104(void)$/;"	f	file:
CpuUnhandledInterrupt105	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt105(void)$/;"	f	file:
CpuUnhandledInterrupt106	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt106(void)$/;"	f	file:
CpuUnhandledInterrupt107	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt107(void)$/;"	f	file:
CpuUnhandledInterrupt108	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt108(void)$/;"	f	file:
CpuUnhandledInterrupt109	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt109(void)$/;"	f	file:
CpuUnhandledInterrupt11	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt11(void)$/;"	f	file:
CpuUnhandledInterrupt110	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt110(void)$/;"	f	file:
CpuUnhandledInterrupt12	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt12(void)$/;"	f	file:
CpuUnhandledInterrupt13	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt13(void)$/;"	f	file:
CpuUnhandledInterrupt14	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt14(void)$/;"	f	file:
CpuUnhandledInterrupt15	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt15(void)$/;"	f	file:
CpuUnhandledInterrupt16	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt16(void)$/;"	f	file:
CpuUnhandledInterrupt17	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt17(void)$/;"	f	file:
CpuUnhandledInterrupt18	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt18(void)$/;"	f	file:
CpuUnhandledInterrupt19	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt19(void)$/;"	f	file:
CpuUnhandledInterrupt2	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt2(void)$/;"	f	file:
CpuUnhandledInterrupt20	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt20(void)$/;"	f	file:
CpuUnhandledInterrupt21	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt21(void)$/;"	f	file:
CpuUnhandledInterrupt22	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt22(void)$/;"	f	file:
CpuUnhandledInterrupt23	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt23(void)$/;"	f	file:
CpuUnhandledInterrupt24	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt24(void)$/;"	f	file:
CpuUnhandledInterrupt25	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt25(void)$/;"	f	file:
CpuUnhandledInterrupt26	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt26(void)$/;"	f	file:
CpuUnhandledInterrupt27	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt27(void)$/;"	f	file:
CpuUnhandledInterrupt28	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt28(void)$/;"	f	file:
CpuUnhandledInterrupt29	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt29(void)$/;"	f	file:
CpuUnhandledInterrupt3	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt3(void)$/;"	f	file:
CpuUnhandledInterrupt30	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt30(void)$/;"	f	file:
CpuUnhandledInterrupt31	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt31(void)$/;"	f	file:
CpuUnhandledInterrupt32	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt32(void)$/;"	f	file:
CpuUnhandledInterrupt33	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt33(void)$/;"	f	file:
CpuUnhandledInterrupt34	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt34(void)$/;"	f	file:
CpuUnhandledInterrupt35	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt35(void)$/;"	f	file:
CpuUnhandledInterrupt36	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt36(void)$/;"	f	file:
CpuUnhandledInterrupt37	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt37(void)$/;"	f	file:
CpuUnhandledInterrupt38	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt38(void)$/;"	f	file:
CpuUnhandledInterrupt39	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt39(void)$/;"	f	file:
CpuUnhandledInterrupt4	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt4(void)$/;"	f	file:
CpuUnhandledInterrupt40	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt40(void)$/;"	f	file:
CpuUnhandledInterrupt41	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt41(void)$/;"	f	file:
CpuUnhandledInterrupt42	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt42(void)$/;"	f	file:
CpuUnhandledInterrupt43	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt43(void)$/;"	f	file:
CpuUnhandledInterrupt44	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt44(void)$/;"	f	file:
CpuUnhandledInterrupt45	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt45(void)$/;"	f	file:
CpuUnhandledInterrupt46	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt46(void)$/;"	f	file:
CpuUnhandledInterrupt47	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt47(void)$/;"	f	file:
CpuUnhandledInterrupt48	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt48(void)$/;"	f	file:
CpuUnhandledInterrupt49	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt49(void)$/;"	f	file:
CpuUnhandledInterrupt5	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt5(void)$/;"	f	file:
CpuUnhandledInterrupt50	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt50(void)$/;"	f	file:
CpuUnhandledInterrupt51	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt51(void)$/;"	f	file:
CpuUnhandledInterrupt52	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt52(void)$/;"	f	file:
CpuUnhandledInterrupt53	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt53(void)$/;"	f	file:
CpuUnhandledInterrupt54	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt54(void)$/;"	f	file:
CpuUnhandledInterrupt55	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt55(void)$/;"	f	file:
CpuUnhandledInterrupt56	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt56(void)$/;"	f	file:
CpuUnhandledInterrupt57	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt57(void)$/;"	f	file:
CpuUnhandledInterrupt58	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt58(void)$/;"	f	file:
CpuUnhandledInterrupt59	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt59(void)$/;"	f	file:
CpuUnhandledInterrupt6	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt6(void)$/;"	f	file:
CpuUnhandledInterrupt60	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt60(void)$/;"	f	file:
CpuUnhandledInterrupt61	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt61(void)$/;"	f	file:
CpuUnhandledInterrupt62	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt62(void)$/;"	f	file:
CpuUnhandledInterrupt63	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt63(void)$/;"	f	file:
CpuUnhandledInterrupt64	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt64(void)$/;"	f	file:
CpuUnhandledInterrupt65	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt65(void)$/;"	f	file:
CpuUnhandledInterrupt66	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt66(void)$/;"	f	file:
CpuUnhandledInterrupt67	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt67(void)$/;"	f	file:
CpuUnhandledInterrupt68	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt68(void)$/;"	f	file:
CpuUnhandledInterrupt69	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt69(void)$/;"	f	file:
CpuUnhandledInterrupt7	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt7(void)$/;"	f	file:
CpuUnhandledInterrupt70	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt70(void)$/;"	f	file:
CpuUnhandledInterrupt71	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt71(void)$/;"	f	file:
CpuUnhandledInterrupt72	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt72(void)$/;"	f	file:
CpuUnhandledInterrupt73	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt73(void)$/;"	f	file:
CpuUnhandledInterrupt74	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt74(void)$/;"	f	file:
CpuUnhandledInterrupt75	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt75(void)$/;"	f	file:
CpuUnhandledInterrupt76	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt76(void)$/;"	f	file:
CpuUnhandledInterrupt77	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt77(void)$/;"	f	file:
CpuUnhandledInterrupt78	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt78(void)$/;"	f	file:
CpuUnhandledInterrupt79	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt79(void)$/;"	f	file:
CpuUnhandledInterrupt8	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt8(void)$/;"	f	file:
CpuUnhandledInterrupt80	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt80(void)$/;"	f	file:
CpuUnhandledInterrupt81	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt81(void)$/;"	f	file:
CpuUnhandledInterrupt82	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt82(void)$/;"	f	file:
CpuUnhandledInterrupt83	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt83(void)$/;"	f	file:
CpuUnhandledInterrupt84	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt84(void)$/;"	f	file:
CpuUnhandledInterrupt85	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt85(void)$/;"	f	file:
CpuUnhandledInterrupt86	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt86(void)$/;"	f	file:
CpuUnhandledInterrupt87	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt87(void)$/;"	f	file:
CpuUnhandledInterrupt88	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt88(void)$/;"	f	file:
CpuUnhandledInterrupt89	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt89(void)$/;"	f	file:
CpuUnhandledInterrupt9	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt9(void)$/;"	f	file:
CpuUnhandledInterrupt90	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt90(void)$/;"	f	file:
CpuUnhandledInterrupt91	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt91(void)$/;"	f	file:
CpuUnhandledInterrupt92	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt92(void)$/;"	f	file:
CpuUnhandledInterrupt93	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt93(void)$/;"	f	file:
CpuUnhandledInterrupt94	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt94(void)$/;"	f	file:
CpuUnhandledInterrupt95	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt95(void)$/;"	f	file:
CpuUnhandledInterrupt96	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt96(void)$/;"	f	file:
CpuUnhandledInterrupt97	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt97(void)$/;"	f	file:
CpuUnhandledInterrupt98	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt98(void)$/;"	f	file:
CpuUnhandledInterrupt99	.\Static_Code\System\Vectors.c	/^static void CpuUnhandledInterrupt99(void)$/;"	f	file:
Cpu_DisableInt	.\Generated_Code\Cpu.h	164;"	d
Cpu_EnableInt	.\Generated_Code\Cpu.h	162;"	d
Cpu_SetStopMode	.\Generated_Code\Cpu.h	168;"	d
Cpu_SetWaitMode	.\Generated_Code\Cpu.h	166;"	d
CrcErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t CrcErrors;                  \/* CRC error counter *\/$/;"	m	struct:__anon40
CurrentAddress	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_TAddress       CurrentAddress; \/* Address of the flash memory location the error status is related to *\/$/;"	m	struct:__anon35
CurrentCommand	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_TCommand       CurrentCommand; \/* Last flash controller command *\/$/;"	m	struct:__anon35
CurrentDataPtr	.\Generated_Code\PE_LDD.h	/^  LDD_TData               *CurrentDataPtr; \/* Pointer to current input data the error status is related to *\/$/;"	m	struct:__anon35
CurrentDataSize	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_TDataSize      CurrentDataSize; \/* Size of the current input data to be programmed or erased in bytes *\/$/;"	m	struct:__anon35
CurrentErrorFlags	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_TErrorFlags    CurrentErrorFlags; \/* Bitfield with error flags. See FLASH2.h for details *\/$/;"	m	struct:__anon35
CurrentOperation	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_TOperationType CurrentOperation; \/* Current operation *\/$/;"	m	struct:__anon35
D	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t D;                                      \/**< I2C Data I\/O register, offset: 0x4 *\/$/;"	m	struct:I2C_MemMap
DACA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2040;"	d
DACA_CTRL0	.\Static_Code\IO_Map\MC56F82748.h	2058;"	d
DACA_CTRL1	.\Static_Code\IO_Map\MC56F82748.h	2068;"	d
DACA_DATAREG_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2059;"	d
DACA_DATAREG_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2060;"	d
DACA_Init	.\Static_Code\Peripherals\DACA_Init.c	/^void DACA_Init(void) {$/;"	f
DACA_MAXVAL_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2065;"	d
DACA_MAXVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2066;"	d
DACA_MINVAL_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2063;"	d
DACA_MINVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2064;"	d
DACA_STATUS	.\Static_Code\IO_Map\MC56F82748.h	2067;"	d
DACA_STEPVAL_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2061;"	d
DACA_STEPVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2062;"	d
DACB_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2042;"	d
DACB_CTRL0	.\Static_Code\IO_Map\MC56F82748.h	2070;"	d
DACB_CTRL1	.\Static_Code\IO_Map\MC56F82748.h	2080;"	d
DACB_DATAREG_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2071;"	d
DACB_DATAREG_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2072;"	d
DACB_Init	.\Static_Code\Peripherals\DACB_Init.c	/^void DACB_Init(void) {$/;"	f
DACB_MAXVAL_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2077;"	d
DACB_MAXVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2078;"	d
DACB_MINVAL_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2075;"	d
DACB_MINVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2076;"	d
DACB_STATUS	.\Static_Code\IO_Map\MC56F82748.h	2079;"	d
DACB_STEPVAL_FMT0	.\Static_Code\IO_Map\MC56F82748.h	2073;"	d
DACB_STEPVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	2074;"	d
DACCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DACCR;                                  \/**< DAC Control Register, offset: 0x4 *\/$/;"	m	struct:CMP_MemMap
DAC_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	2044;"	d
DAC_CTRL0_AUTO_MASK	.\Static_Code\IO_Map\MC56F82748.h	1976;"	d
DAC_CTRL0_AUTO_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1977;"	d
DAC_CTRL0_DMA_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1984;"	d
DAC_CTRL0_DMA_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1985;"	d
DAC_CTRL0_DOWN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1978;"	d
DAC_CTRL0_DOWN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1979;"	d
DAC_CTRL0_FILT_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1989;"	d
DAC_CTRL0_FILT_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1990;"	d
DAC_CTRL0_FORMAT_MASK	.\Static_Code\IO_Map\MC56F82748.h	1972;"	d
DAC_CTRL0_FORMAT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1973;"	d
DAC_CTRL0_HSLS_MASK	.\Static_Code\IO_Map\MC56F82748.h	1982;"	d
DAC_CTRL0_HSLS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1983;"	d
DAC_CTRL0_PDN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1970;"	d
DAC_CTRL0_PDN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1971;"	d
DAC_CTRL0_REG	.\Static_Code\IO_Map\MC56F82748.h	1943;"	d
DAC_CTRL0_SYNC_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	1974;"	d
DAC_CTRL0_SYNC_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1975;"	d
DAC_CTRL0_UP_MASK	.\Static_Code\IO_Map\MC56F82748.h	1980;"	d
DAC_CTRL0_UP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1981;"	d
DAC_CTRL0_WTMK_LVL	.\Static_Code\IO_Map\MC56F82748.h	1988;"	d
DAC_CTRL0_WTMK_LVL_MASK	.\Static_Code\IO_Map\MC56F82748.h	1986;"	d
DAC_CTRL0_WTMK_LVL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1987;"	d
DAC_CTRL1_FILT_CNT	.\Static_Code\IO_Map\MC56F82748.h	2031;"	d
DAC_CTRL1_FILT_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2029;"	d
DAC_CTRL1_FILT_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2030;"	d
DAC_CTRL1_REG	.\Static_Code\IO_Map\MC56F82748.h	1953;"	d
DAC_DATAREG_DATA	.\Static_Code\IO_Map\MC56F82748.h	1994;"	d
DAC_DATAREG_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	1992;"	d
DAC_DATAREG_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1993;"	d
DAC_DATAREG_FMT1_DATA	.\Static_Code\IO_Map\MC56F82748.h	1998;"	d
DAC_DATAREG_FMT1_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	1996;"	d
DAC_DATAREG_FMT1_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	1997;"	d
DAC_DATAREG_FMT1_REG	.\Static_Code\IO_Map\MC56F82748.h	1945;"	d
DAC_DATAREG_REG	.\Static_Code\IO_Map\MC56F82748.h	1944;"	d
DAC_MAXVAL_FMT1_MAXVAL	.\Static_Code\IO_Map\MC56F82748.h	2022;"	d
DAC_MAXVAL_FMT1_MAXVAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2020;"	d
DAC_MAXVAL_FMT1_MAXVAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2021;"	d
DAC_MAXVAL_FMT1_REG	.\Static_Code\IO_Map\MC56F82748.h	1951;"	d
DAC_MAXVAL_MAXVAL	.\Static_Code\IO_Map\MC56F82748.h	2018;"	d
DAC_MAXVAL_MAXVAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2016;"	d
DAC_MAXVAL_MAXVAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2017;"	d
DAC_MAXVAL_REG	.\Static_Code\IO_Map\MC56F82748.h	1950;"	d
DAC_MINVAL_FMT1_MINVAL	.\Static_Code\IO_Map\MC56F82748.h	2014;"	d
DAC_MINVAL_FMT1_MINVAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2012;"	d
DAC_MINVAL_FMT1_MINVAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2013;"	d
DAC_MINVAL_FMT1_REG	.\Static_Code\IO_Map\MC56F82748.h	1949;"	d
DAC_MINVAL_MINVAL	.\Static_Code\IO_Map\MC56F82748.h	2010;"	d
DAC_MINVAL_MINVAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2008;"	d
DAC_MINVAL_MINVAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2009;"	d
DAC_MINVAL_REG	.\Static_Code\IO_Map\MC56F82748.h	1948;"	d
DAC_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct DAC_MemMap {$/;"	s
DAC_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *DAC_MemMapPtr;$/;"	t
DAC_PDD_AUTOMATIC_WAVEFORM	.\Static_Code\PDD\DAC_PDD.h	60;"	d
DAC_PDD_BUFFER_WATERMARK_L0	.\Static_Code\PDD\DAC_PDD.h	45;"	d
DAC_PDD_BUFFER_WATERMARK_L2	.\Static_Code\PDD\DAC_PDD.h	46;"	d
DAC_PDD_BUFFER_WATERMARK_L4	.\Static_Code\PDD\DAC_PDD.h	47;"	d
DAC_PDD_BUFFER_WATERMARK_L6	.\Static_Code\PDD\DAC_PDD.h	48;"	d
DAC_PDD_DOWN_COUNTING	.\Static_Code\PDD\DAC_PDD.h	56;"	d
DAC_PDD_EnableDevice	.\Static_Code\PDD\DAC_PDD.h	89;"	d
DAC_PDD_EnableDmaRequest	.\Static_Code\PDD\DAC_PDD.h	272;"	d
DAC_PDD_EnableGlitchFilter	.\Static_Code\PDD\DAC_PDD.h	315;"	d
DAC_PDD_FIFO_EMPTY	.\Static_Code\PDD\DAC_PDD.h	68;"	d
DAC_PDD_FIFO_FULL	.\Static_Code\PDD\DAC_PDD.h	67;"	d
DAC_PDD_GetAutomaticMode	.\Static_Code\PDD\DAC_PDD.h	430;"	d
DAC_PDD_GetBufferWatermark	.\Static_Code\PDD\DAC_PDD.h	206;"	d
DAC_PDD_GetCountingMask	.\Static_Code\PDD\DAC_PDD.h	383;"	d
DAC_PDD_GetData	.\Static_Code\PDD\DAC_PDD.h	611;"	d
DAC_PDD_GetDataFormat	.\Static_Code\PDD\DAC_PDD.h	500;"	d
DAC_PDD_GetDataLeft	.\Static_Code\PDD\DAC_PDD.h	650;"	d
DAC_PDD_GetDeviceEnabled	.\Static_Code\PDD\DAC_PDD.h	112;"	d
DAC_PDD_GetDmaRequestEnabled	.\Static_Code\PDD\DAC_PDD.h	293;"	d
DAC_PDD_GetFifoStatusMask	.\Static_Code\PDD\DAC_PDD.h	569;"	d
DAC_PDD_GetGlitchFilter	.\Static_Code\PDD\DAC_PDD.h	547;"	d
DAC_PDD_GetGlitchFilterEnabled	.\Static_Code\PDD\DAC_PDD.h	336;"	d
DAC_PDD_GetMaximum	.\Static_Code\PDD\DAC_PDD.h	862;"	d
DAC_PDD_GetMaximumLeft	.\Static_Code\PDD\DAC_PDD.h	904;"	d
DAC_PDD_GetMinimum	.\Static_Code\PDD\DAC_PDD.h	778;"	d
DAC_PDD_GetMinimumLeft	.\Static_Code\PDD\DAC_PDD.h	820;"	d
DAC_PDD_GetPowerMode	.\Static_Code\PDD\DAC_PDD.h	249;"	d
DAC_PDD_GetStep	.\Static_Code\PDD\DAC_PDD.h	693;"	d
DAC_PDD_GetStepLeft	.\Static_Code\PDD\DAC_PDD.h	736;"	d
DAC_PDD_GetTriggerSource	.\Static_Code\PDD\DAC_PDD.h	159;"	d
DAC_PDD_HIGH_POWER	.\Static_Code\PDD\DAC_PDD.h	51;"	d
DAC_PDD_HW_TRIGGER	.\Static_Code\PDD\DAC_PDD.h	40;"	d
DAC_PDD_H_	.\Static_Code\PDD\DAC_PDD.h	9;"	d
DAC_PDD_JUSTIFIED_LEFT	.\Static_Code\PDD\DAC_PDD.h	64;"	d
DAC_PDD_JUSTIFIED_RIGHT	.\Static_Code\PDD\DAC_PDD.h	63;"	d
DAC_PDD_LOW_POWER	.\Static_Code\PDD\DAC_PDD.h	52;"	d
DAC_PDD_NORMAL_MODE	.\Static_Code\PDD\DAC_PDD.h	59;"	d
DAC_PDD_ReadBufferedDataReg	.\Static_Code\PDD\DAC_PDD.h	1064;"	d
DAC_PDD_ReadControl0Reg	.\Static_Code\PDD\DAC_PDD.h	944;"	d
DAC_PDD_ReadControl1Reg	.\Static_Code\PDD\DAC_PDD.h	984;"	d
DAC_PDD_ReadMaximumValueReg	.\Static_Code\PDD\DAC_PDD.h	1184;"	d
DAC_PDD_ReadMinimumValueReg	.\Static_Code\PDD\DAC_PDD.h	1144;"	d
DAC_PDD_ReadStatusReg	.\Static_Code\PDD\DAC_PDD.h	1024;"	d
DAC_PDD_ReadStepSizeReg	.\Static_Code\PDD\DAC_PDD.h	1104;"	d
DAC_PDD_SW_TRIGGER	.\Static_Code\PDD\DAC_PDD.h	41;"	d
DAC_PDD_SetAutomaticMode	.\Static_Code\PDD\DAC_PDD.h	407;"	d
DAC_PDD_SetBufferWatermark	.\Static_Code\PDD\DAC_PDD.h	181;"	d
DAC_PDD_SetCountingMask	.\Static_Code\PDD\DAC_PDD.h	358;"	d
DAC_PDD_SetData	.\Static_Code\PDD\DAC_PDD.h	592;"	d
DAC_PDD_SetDataFormat	.\Static_Code\PDD\DAC_PDD.h	477;"	d
DAC_PDD_SetDataLeft	.\Static_Code\PDD\DAC_PDD.h	631;"	d
DAC_PDD_SetGlitchFilter	.\Static_Code\PDD\DAC_PDD.h	522;"	d
DAC_PDD_SetMaximum	.\Static_Code\PDD\DAC_PDD.h	841;"	d
DAC_PDD_SetMaximumLeft	.\Static_Code\PDD\DAC_PDD.h	883;"	d
DAC_PDD_SetMinimum	.\Static_Code\PDD\DAC_PDD.h	757;"	d
DAC_PDD_SetMinimumLeft	.\Static_Code\PDD\DAC_PDD.h	799;"	d
DAC_PDD_SetPowerMode	.\Static_Code\PDD\DAC_PDD.h	227;"	d
DAC_PDD_SetStep	.\Static_Code\PDD\DAC_PDD.h	672;"	d
DAC_PDD_SetStepLeft	.\Static_Code\PDD\DAC_PDD.h	715;"	d
DAC_PDD_SetTrigger	.\Static_Code\PDD\DAC_PDD.h	137;"	d
DAC_PDD_SetWaveformMask	.\Static_Code\PDD\DAC_PDD.h	452;"	d
DAC_PDD_UP_COUNTING	.\Static_Code\PDD\DAC_PDD.h	55;"	d
DAC_PDD_WriteBufferedDataReg	.\Static_Code\PDD\DAC_PDD.h	1045;"	d
DAC_PDD_WriteControl0Reg	.\Static_Code\PDD\DAC_PDD.h	925;"	d
DAC_PDD_WriteControl1Reg	.\Static_Code\PDD\DAC_PDD.h	965;"	d
DAC_PDD_WriteMaximumValueReg	.\Static_Code\PDD\DAC_PDD.h	1165;"	d
DAC_PDD_WriteMinimumValueReg	.\Static_Code\PDD\DAC_PDD.h	1125;"	d
DAC_PDD_WriteStatusReg	.\Static_Code\PDD\DAC_PDD.h	1005;"	d
DAC_PDD_WriteStepSizeReg	.\Static_Code\PDD\DAC_PDD.h	1085;"	d
DAC_STATUS_EMPTY_MASK	.\Static_Code\IO_Map\MC56F82748.h	2024;"	d
DAC_STATUS_EMPTY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2025;"	d
DAC_STATUS_FULL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2026;"	d
DAC_STATUS_FULL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2027;"	d
DAC_STATUS_REG	.\Static_Code\IO_Map\MC56F82748.h	1952;"	d
DAC_STEPVAL_FMT1_REG	.\Static_Code\IO_Map\MC56F82748.h	1947;"	d
DAC_STEPVAL_FMT1_STEP	.\Static_Code\IO_Map\MC56F82748.h	2006;"	d
DAC_STEPVAL_FMT1_STEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2004;"	d
DAC_STEPVAL_FMT1_STEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2005;"	d
DAC_STEPVAL_REG	.\Static_Code\IO_Map\MC56F82748.h	1946;"	d
DAC_STEPVAL_STEP	.\Static_Code\IO_Map\MC56F82748.h	2002;"	d
DAC_STEPVAL_STEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2000;"	d
DAC_STEPVAL_STEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2001;"	d
DAR	.\Static_Code\IO_Map\MC56F82748.h	/^    uint32_t DAR;                                    \/**< Destination Address Register, array offset: 0x82, array step: 0x8 *\/$/;"	m	struct:DMA_MemMap::__anon57
DATA	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DATA;                                   \/**< QSCI Data Register, offset: 0x4 *\/$/;"	m	struct:QSCI_MemMap
DATA	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t DATA[4][4];                             \/**< Cache Data Storage, array offset: 0x100, array step: index*0x8, index2*0x2 *\/$/;"	m	struct:FMC_MemMap
DATAREG	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DATAREG;                                \/**< Buffered Data Register, offset: 0x1 *\/$/;"	m	union:DAC_MemMap::__anon52
DATAREG_FMT1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DATAREG_FMT1;                           \/**< Buffered Data Register, offset: 0x1 *\/$/;"	m	union:DAC_MemMap::__anon52
DCR	.\Static_Code\IO_Map\MC56F82748.h	/^    uint32_t DCR;                                    \/**< DMA Control Register, array offset: 0x86, array step: 0x8 *\/$/;"	m	struct:DMA_MemMap::__anon57
DDR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DDR;                                    \/**< GPIO Data Direction Register, offset: 0x2 *\/$/;"	m	struct:GPIO_MemMap
DIR_DOWN	.\Generated_Code\PE_LDD.h	/^  DIR_DOWN$/;"	e	enum:__anon6
DIR_UP	.\Generated_Code\PE_LDD.h	/^  DIR_UP,$/;"	e	enum:__anon6
DISMAP	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DISMAP[2];                              \/**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x16, array step: index*0x30, index2*0x1 *\/$/;"	m	struct:PWM_MemMap::__anon59
DIVBY	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DIVBY;                                  \/**< PLL Divide-By Register, offset: 0x1 *\/$/;"	m	struct:OCCS_MemMap
DMA	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DMA;                                    \/**< Timer Channel DMA Enable Register, array offset: 0xC, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
DMA	.\Static_Code\IO_Map\MC56F82748.h	/^  } DMA[4];$/;"	m	struct:DMA_MemMap	typeref:struct:DMA_MemMap::__anon57
DMAEN	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DMAEN;                                  \/**< DMA Enable Register, array offset: 0x14, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
DMA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2239;"	d
DMA_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	2241;"	d
DMA_DAR	.\Static_Code\IO_Map\MC56F82748.h	2275;"	d
DMA_DAR0	.\Static_Code\IO_Map\MC56F82748.h	2257;"	d
DMA_DAR1	.\Static_Code\IO_Map\MC56F82748.h	2261;"	d
DMA_DAR2	.\Static_Code\IO_Map\MC56F82748.h	2265;"	d
DMA_DAR3	.\Static_Code\IO_Map\MC56F82748.h	2269;"	d
DMA_DAR_DAR	.\Static_Code\IO_Map\MC56F82748.h	2176;"	d
DMA_DAR_DAR_MASK	.\Static_Code\IO_Map\MC56F82748.h	2174;"	d
DMA_DAR_DAR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2175;"	d
DMA_DAR_REG	.\Static_Code\IO_Map\MC56F82748.h	2130;"	d
DMA_DCR	.\Static_Code\IO_Map\MC56F82748.h	2277;"	d
DMA_DCR0	.\Static_Code\IO_Map\MC56F82748.h	2259;"	d
DMA_DCR1	.\Static_Code\IO_Map\MC56F82748.h	2263;"	d
DMA_DCR2	.\Static_Code\IO_Map\MC56F82748.h	2267;"	d
DMA_DCR3	.\Static_Code\IO_Map\MC56F82748.h	2271;"	d
DMA_DCR_AA_MASK	.\Static_Code\IO_Map\MC56F82748.h	2223;"	d
DMA_DCR_AA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2224;"	d
DMA_DCR_CS_MASK	.\Static_Code\IO_Map\MC56F82748.h	2225;"	d
DMA_DCR_CS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2226;"	d
DMA_DCR_DINC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2216;"	d
DMA_DCR_DINC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2217;"	d
DMA_DCR_DMOD	.\Static_Code\IO_Map\MC56F82748.h	2207;"	d
DMA_DCR_DMOD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2205;"	d
DMA_DCR_DMOD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2206;"	d
DMA_DCR_DSIZE	.\Static_Code\IO_Map\MC56F82748.h	2215;"	d
DMA_DCR_DSIZE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2213;"	d
DMA_DCR_DSIZE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2214;"	d
DMA_DCR_D_REQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	2203;"	d
DMA_DCR_D_REQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2204;"	d
DMA_DCR_EINT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2229;"	d
DMA_DCR_EINT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2230;"	d
DMA_DCR_ERQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	2227;"	d
DMA_DCR_ERQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2228;"	d
DMA_DCR_LCH1	.\Static_Code\IO_Map\MC56F82748.h	2199;"	d
DMA_DCR_LCH1_MASK	.\Static_Code\IO_Map\MC56F82748.h	2197;"	d
DMA_DCR_LCH1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2198;"	d
DMA_DCR_LCH2	.\Static_Code\IO_Map\MC56F82748.h	2196;"	d
DMA_DCR_LCH2_MASK	.\Static_Code\IO_Map\MC56F82748.h	2194;"	d
DMA_DCR_LCH2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2195;"	d
DMA_DCR_LINKCC	.\Static_Code\IO_Map\MC56F82748.h	2202;"	d
DMA_DCR_LINKCC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2200;"	d
DMA_DCR_LINKCC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2201;"	d
DMA_DCR_REG	.\Static_Code\IO_Map\MC56F82748.h	2132;"	d
DMA_DCR_SINC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2221;"	d
DMA_DCR_SINC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2222;"	d
DMA_DCR_SMOD	.\Static_Code\IO_Map\MC56F82748.h	2210;"	d
DMA_DCR_SMOD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2208;"	d
DMA_DCR_SMOD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2209;"	d
DMA_DCR_SSIZE	.\Static_Code\IO_Map\MC56F82748.h	2220;"	d
DMA_DCR_SSIZE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2218;"	d
DMA_DCR_SSIZE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2219;"	d
DMA_DCR_START_MASK	.\Static_Code\IO_Map\MC56F82748.h	2211;"	d
DMA_DCR_START_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2212;"	d
DMA_DSR_BCR	.\Static_Code\IO_Map\MC56F82748.h	2276;"	d
DMA_DSR_BCR0	.\Static_Code\IO_Map\MC56F82748.h	2258;"	d
DMA_DSR_BCR1	.\Static_Code\IO_Map\MC56F82748.h	2262;"	d
DMA_DSR_BCR2	.\Static_Code\IO_Map\MC56F82748.h	2266;"	d
DMA_DSR_BCR3	.\Static_Code\IO_Map\MC56F82748.h	2270;"	d
DMA_DSR_BCR_BCR	.\Static_Code\IO_Map\MC56F82748.h	2180;"	d
DMA_DSR_BCR_BCR_MASK	.\Static_Code\IO_Map\MC56F82748.h	2178;"	d
DMA_DSR_BCR_BCR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2179;"	d
DMA_DSR_BCR_BED_MASK	.\Static_Code\IO_Map\MC56F82748.h	2187;"	d
DMA_DSR_BCR_BED_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2188;"	d
DMA_DSR_BCR_BES_MASK	.\Static_Code\IO_Map\MC56F82748.h	2189;"	d
DMA_DSR_BCR_BES_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2190;"	d
DMA_DSR_BCR_BSY_MASK	.\Static_Code\IO_Map\MC56F82748.h	2183;"	d
DMA_DSR_BCR_BSY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2184;"	d
DMA_DSR_BCR_CE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2191;"	d
DMA_DSR_BCR_CE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2192;"	d
DMA_DSR_BCR_DONE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2181;"	d
DMA_DSR_BCR_DONE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2182;"	d
DMA_DSR_BCR_REG	.\Static_Code\IO_Map\MC56F82748.h	2131;"	d
DMA_DSR_BCR_REQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	2185;"	d
DMA_DSR_BCR_REQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2186;"	d
DMA_Init	.\Static_Code\Peripherals\DMA_Init.c	/^void DMA_Init(void) {$/;"	f
DMA_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct DMA_MemMap {$/;"	s
DMA_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *DMA_MemMapPtr;$/;"	t
DMA_PDD_16_BIT	.\Static_Code\PDD\DMA_PDD.h	104;"	d
DMA_PDD_32_BIT	.\Static_Code\PDD\DMA_PDD.h	105;"	d
DMA_PDD_8_BIT	.\Static_Code\PDD\DMA_PDD.h	103;"	d
DMA_PDD_CHANNEL_0	.\Static_Code\PDD\DMA_PDD.h	41;"	d
DMA_PDD_CHANNEL_1	.\Static_Code\PDD\DMA_PDD.h	42;"	d
DMA_PDD_CHANNEL_2	.\Static_Code\PDD\DMA_PDD.h	43;"	d
DMA_PDD_CHANNEL_3	.\Static_Code\PDD\DMA_PDD.h	44;"	d
DMA_PDD_CHANNEL_SOURCE_0	.\Static_Code\PDD\DMA_PDD.h	53;"	d
DMA_PDD_CHANNEL_SOURCE_1	.\Static_Code\PDD\DMA_PDD.h	54;"	d
DMA_PDD_CHANNEL_SOURCE_10	.\Static_Code\PDD\DMA_PDD.h	63;"	d
DMA_PDD_CHANNEL_SOURCE_11	.\Static_Code\PDD\DMA_PDD.h	64;"	d
DMA_PDD_CHANNEL_SOURCE_12	.\Static_Code\PDD\DMA_PDD.h	65;"	d
DMA_PDD_CHANNEL_SOURCE_13	.\Static_Code\PDD\DMA_PDD.h	66;"	d
DMA_PDD_CHANNEL_SOURCE_14	.\Static_Code\PDD\DMA_PDD.h	67;"	d
DMA_PDD_CHANNEL_SOURCE_15	.\Static_Code\PDD\DMA_PDD.h	68;"	d
DMA_PDD_CHANNEL_SOURCE_2	.\Static_Code\PDD\DMA_PDD.h	55;"	d
DMA_PDD_CHANNEL_SOURCE_3	.\Static_Code\PDD\DMA_PDD.h	56;"	d
DMA_PDD_CHANNEL_SOURCE_4	.\Static_Code\PDD\DMA_PDD.h	57;"	d
DMA_PDD_CHANNEL_SOURCE_5	.\Static_Code\PDD\DMA_PDD.h	58;"	d
DMA_PDD_CHANNEL_SOURCE_6	.\Static_Code\PDD\DMA_PDD.h	59;"	d
DMA_PDD_CHANNEL_SOURCE_7	.\Static_Code\PDD\DMA_PDD.h	60;"	d
DMA_PDD_CHANNEL_SOURCE_8	.\Static_Code\PDD\DMA_PDD.h	61;"	d
DMA_PDD_CHANNEL_SOURCE_9	.\Static_Code\PDD\DMA_PDD.h	62;"	d
DMA_PDD_CIRCULAR_BUFFER_128_BYTES	.\Static_Code\PDD\DMA_PDD.h	89;"	d
DMA_PDD_CIRCULAR_BUFFER_128_KBYTES	.\Static_Code\PDD\DMA_PDD.h	99;"	d
DMA_PDD_CIRCULAR_BUFFER_16_BYTES	.\Static_Code\PDD\DMA_PDD.h	86;"	d
DMA_PDD_CIRCULAR_BUFFER_16_KBYTES	.\Static_Code\PDD\DMA_PDD.h	96;"	d
DMA_PDD_CIRCULAR_BUFFER_1_KBYTE	.\Static_Code\PDD\DMA_PDD.h	92;"	d
DMA_PDD_CIRCULAR_BUFFER_256_BYTES	.\Static_Code\PDD\DMA_PDD.h	90;"	d
DMA_PDD_CIRCULAR_BUFFER_256_KBYTES	.\Static_Code\PDD\DMA_PDD.h	100;"	d
DMA_PDD_CIRCULAR_BUFFER_2_KBYTES	.\Static_Code\PDD\DMA_PDD.h	93;"	d
DMA_PDD_CIRCULAR_BUFFER_32_BYTES	.\Static_Code\PDD\DMA_PDD.h	87;"	d
DMA_PDD_CIRCULAR_BUFFER_32_KBYTES	.\Static_Code\PDD\DMA_PDD.h	97;"	d
DMA_PDD_CIRCULAR_BUFFER_4_KBYTES	.\Static_Code\PDD\DMA_PDD.h	94;"	d
DMA_PDD_CIRCULAR_BUFFER_512_BYTES	.\Static_Code\PDD\DMA_PDD.h	91;"	d
DMA_PDD_CIRCULAR_BUFFER_64_BYTES	.\Static_Code\PDD\DMA_PDD.h	88;"	d
DMA_PDD_CIRCULAR_BUFFER_64_KBYTES	.\Static_Code\PDD\DMA_PDD.h	98;"	d
DMA_PDD_CIRCULAR_BUFFER_8_KBYTES	.\Static_Code\PDD\DMA_PDD.h	95;"	d
DMA_PDD_CIRCULAR_BUFFER_DISABLED	.\Static_Code\PDD\DMA_PDD.h	85;"	d
DMA_PDD_CONFIGURATION_ERROR_FLAG	.\Static_Code\PDD\DMA_PDD.h	76;"	d
DMA_PDD_CYCLE_STEAL_AND_TRANSFER_COMPLETE_LINKING	.\Static_Code\PDD\DMA_PDD.h	109;"	d
DMA_PDD_CYCLE_STEAL_LINKING	.\Static_Code\PDD\DMA_PDD.h	110;"	d
DMA_PDD_CancelTransfer	.\Static_Code\PDD\DMA_PDD.h	1383;"	d
DMA_PDD_ClearDoneFlag	.\Static_Code\PDD\DMA_PDD.h	709;"	d
DMA_PDD_ClearInterruptFlags	.\Static_Code\PDD\DMA_PDD.h	204;"	d
DMA_PDD_ClearStateMachine	.\Static_Code\PDD\DMA_PDD.h	314;"	d
DMA_PDD_DisableInterrupts	.\Static_Code\PDD\DMA_PDD.h	156;"	d
DMA_PDD_ERROR_ON_DESTINATION_FLAG	.\Static_Code\PDD\DMA_PDD.h	78;"	d
DMA_PDD_ERROR_ON_SOURCE_FLAG	.\Static_Code\PDD\DMA_PDD.h	77;"	d
DMA_PDD_EnableAutoAlign	.\Static_Code\PDD\DMA_PDD.h	1120;"	d
DMA_PDD_EnableContinuousMode	.\Static_Code\PDD\DMA_PDD.h	1067;"	d
DMA_PDD_EnableCycleSteal	.\Static_Code\PDD\DMA_PDD.h	1020;"	d
DMA_PDD_EnableDestinationAddressIncrement	.\Static_Code\PDD\DMA_PDD.h	1268;"	d
DMA_PDD_EnableInterrupts	.\Static_Code\PDD\DMA_PDD.h	133;"	d
DMA_PDD_EnablePeripheralRequest	.\Static_Code\PDD\DMA_PDD.h	972;"	d
DMA_PDD_EnableRequestAutoDisable	.\Static_Code\PDD\DMA_PDD.h	1513;"	d
DMA_PDD_EnableSourceAddressIncrement	.\Static_Code\PDD\DMA_PDD.h	1169;"	d
DMA_PDD_EnableTransferCompleteInterrupt	.\Static_Code\PDD\DMA_PDD.h	924;"	d
DMA_PDD_GetAutoAlignEnabled	.\Static_Code\PDD\DMA_PDD.h	1143;"	d
DMA_PDD_GetBusyFlag	.\Static_Code\PDD\DMA_PDD.h	755;"	d
DMA_PDD_GetByteCount	.\Static_Code\PDD\DMA_PDD.h	854;"	d
DMA_PDD_GetChannel0Source	.\Static_Code\PDD\DMA_PDD.h	360;"	d
DMA_PDD_GetChannel1Source	.\Static_Code\PDD\DMA_PDD.h	405;"	d
DMA_PDD_GetChannel2Source	.\Static_Code\PDD\DMA_PDD.h	450;"	d
DMA_PDD_GetChannel3Source	.\Static_Code\PDD\DMA_PDD.h	495;"	d
DMA_PDD_GetChannelActivityFlags	.\Static_Code\PDD\DMA_PDD.h	686;"	d
DMA_PDD_GetChannelErrorFlags	.\Static_Code\PDD\DMA_PDD.h	805;"	d
DMA_PDD_GetChannelLinkingMode	.\Static_Code\PDD\DMA_PDD.h	1584;"	d
DMA_PDD_GetChannelSource	.\Static_Code\PDD\DMA_PDD.h	291;"	d
DMA_PDD_GetContinuousModeEnabled	.\Static_Code\PDD\DMA_PDD.h	1092;"	d
DMA_PDD_GetCycleStealEnabled	.\Static_Code\PDD\DMA_PDD.h	1043;"	d
DMA_PDD_GetDestinationAddress	.\Static_Code\PDD\DMA_PDD.h	579;"	d
DMA_PDD_GetDestinationAddressIncrementEnabled	.\Static_Code\PDD\DMA_PDD.h	1291;"	d
DMA_PDD_GetDestinationAddressModulo	.\Static_Code\PDD\DMA_PDD.h	1486;"	d
DMA_PDD_GetDestinationDataTransferSize	.\Static_Code\PDD\DMA_PDD.h	1339;"	d
DMA_PDD_GetDoneFlag	.\Static_Code\PDD\DMA_PDD.h	732;"	d
DMA_PDD_GetInterruptFlags	.\Static_Code\PDD\DMA_PDD.h	178;"	d
DMA_PDD_GetLinkChannel1	.\Static_Code\PDD\DMA_PDD.h	1633;"	d
DMA_PDD_GetLinkChannel2	.\Static_Code\PDD\DMA_PDD.h	1682;"	d
DMA_PDD_GetPeripheralRequestEnabled	.\Static_Code\PDD\DMA_PDD.h	995;"	d
DMA_PDD_GetRequestAutoDisableEnabled	.\Static_Code\PDD\DMA_PDD.h	1536;"	d
DMA_PDD_GetRequestPendingFlag	.\Static_Code\PDD\DMA_PDD.h	779;"	d
DMA_PDD_GetSourceAddress	.\Static_Code\PDD\DMA_PDD.h	536;"	d
DMA_PDD_GetSourceAddressIncrementEnabled	.\Static_Code\PDD\DMA_PDD.h	1192;"	d
DMA_PDD_GetSourceAddressModulo	.\Static_Code\PDD\DMA_PDD.h	1435;"	d
DMA_PDD_GetSourceDataTransferSize	.\Static_Code\PDD\DMA_PDD.h	1240;"	d
DMA_PDD_GetStatusByteCountRegister	.\Static_Code\PDD\DMA_PDD.h	664;"	d
DMA_PDD_GetTransferCompleteInterruptEnabled	.\Static_Code\PDD\DMA_PDD.h	947;"	d
DMA_PDD_H_	.\Static_Code\PDD\DMA_PDD.h	9;"	d
DMA_PDD_LINKING_DISABLED	.\Static_Code\PDD\DMA_PDD.h	108;"	d
DMA_PDD_ReadControlReg	.\Static_Code\PDD\DMA_PDD.h	899;"	d
DMA_PDD_ReadRequestControlReg	.\Static_Code\PDD\DMA_PDD.h	242;"	d
DMA_PDD_ReadStatusByteCountReg	.\Static_Code\PDD\DMA_PDD.h	643;"	d
DMA_PDD_SetByteCount	.\Static_Code\PDD\DMA_PDD.h	829;"	d
DMA_PDD_SetChannel0Source	.\Static_Code\PDD\DMA_PDD.h	337;"	d
DMA_PDD_SetChannel1Source	.\Static_Code\PDD\DMA_PDD.h	382;"	d
DMA_PDD_SetChannel2Source	.\Static_Code\PDD\DMA_PDD.h	427;"	d
DMA_PDD_SetChannel3Source	.\Static_Code\PDD\DMA_PDD.h	472;"	d
DMA_PDD_SetChannelLinkingMode	.\Static_Code\PDD\DMA_PDD.h	1559;"	d
DMA_PDD_SetChannelSource	.\Static_Code\PDD\DMA_PDD.h	263;"	d
DMA_PDD_SetDestinationAddress	.\Static_Code\PDD\DMA_PDD.h	558;"	d
DMA_PDD_SetDestinationAddressModulo	.\Static_Code\PDD\DMA_PDD.h	1460;"	d
DMA_PDD_SetDestinationDataTransferSize	.\Static_Code\PDD\DMA_PDD.h	1314;"	d
DMA_PDD_SetLinkChannel1	.\Static_Code\PDD\DMA_PDD.h	1608;"	d
DMA_PDD_SetLinkChannel2	.\Static_Code\PDD\DMA_PDD.h	1657;"	d
DMA_PDD_SetSourceAddress	.\Static_Code\PDD\DMA_PDD.h	516;"	d
DMA_PDD_SetSourceAddressModulo	.\Static_Code\PDD\DMA_PDD.h	1409;"	d
DMA_PDD_SetSourceDataTransferSize	.\Static_Code\PDD\DMA_PDD.h	1215;"	d
DMA_PDD_StartTransfer	.\Static_Code\PDD\DMA_PDD.h	1363;"	d
DMA_PDD_TRANSFER_BUSY_FLAG	.\Static_Code\PDD\DMA_PDD.h	72;"	d
DMA_PDD_TRANSFER_COMPLETE_DISABLE	.\Static_Code\PDD\DMA_PDD.h	82;"	d
DMA_PDD_TRANSFER_COMPLETE_ENABLE	.\Static_Code\PDD\DMA_PDD.h	81;"	d
DMA_PDD_TRANSFER_COMPLETE_FLAG	.\Static_Code\PDD\DMA_PDD.h	50;"	d
DMA_PDD_TRANSFER_COMPLETE_INTERRUPT	.\Static_Code\PDD\DMA_PDD.h	47;"	d
DMA_PDD_TRANSFER_COMPLETE_LINKING	.\Static_Code\PDD\DMA_PDD.h	111;"	d
DMA_PDD_TRANSFER_DONE_FLAG	.\Static_Code\PDD\DMA_PDD.h	71;"	d
DMA_PDD_TRANSFER_REQUEST_PENDING_FLAG	.\Static_Code\PDD\DMA_PDD.h	73;"	d
DMA_PDD_WriteControlReg	.\Static_Code\PDD\DMA_PDD.h	879;"	d
DMA_PDD_WriteRequestControlReg	.\Static_Code\PDD\DMA_PDD.h	224;"	d
DMA_PDD_WriteStatusByteCountReg	.\Static_Code\PDD\DMA_PDD.h	601;"	d
DMA_PDD_WriteStatusByteCountRegister	.\Static_Code\PDD\DMA_PDD.h	622;"	d
DMA_REQC	.\Static_Code\IO_Map\MC56F82748.h	2255;"	d
DMA_REQC_CFSM0_MASK	.\Static_Code\IO_Map\MC56F82748.h	2167;"	d
DMA_REQC_CFSM0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2168;"	d
DMA_REQC_CFSM1_MASK	.\Static_Code\IO_Map\MC56F82748.h	2162;"	d
DMA_REQC_CFSM1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2163;"	d
DMA_REQC_CFSM2_MASK	.\Static_Code\IO_Map\MC56F82748.h	2157;"	d
DMA_REQC_CFSM2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2158;"	d
DMA_REQC_CFSM3_MASK	.\Static_Code\IO_Map\MC56F82748.h	2152;"	d
DMA_REQC_CFSM3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2153;"	d
DMA_REQC_DMAC0	.\Static_Code\IO_Map\MC56F82748.h	2166;"	d
DMA_REQC_DMAC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	2164;"	d
DMA_REQC_DMAC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2165;"	d
DMA_REQC_DMAC1	.\Static_Code\IO_Map\MC56F82748.h	2161;"	d
DMA_REQC_DMAC1_MASK	.\Static_Code\IO_Map\MC56F82748.h	2159;"	d
DMA_REQC_DMAC1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2160;"	d
DMA_REQC_DMAC2	.\Static_Code\IO_Map\MC56F82748.h	2156;"	d
DMA_REQC_DMAC2_MASK	.\Static_Code\IO_Map\MC56F82748.h	2154;"	d
DMA_REQC_DMAC2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2155;"	d
DMA_REQC_DMAC3	.\Static_Code\IO_Map\MC56F82748.h	2151;"	d
DMA_REQC_DMAC3_MASK	.\Static_Code\IO_Map\MC56F82748.h	2149;"	d
DMA_REQC_DMAC3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2150;"	d
DMA_REQC_REG	.\Static_Code\IO_Map\MC56F82748.h	2128;"	d
DMA_SAR	.\Static_Code\IO_Map\MC56F82748.h	2274;"	d
DMA_SAR0	.\Static_Code\IO_Map\MC56F82748.h	2256;"	d
DMA_SAR1	.\Static_Code\IO_Map\MC56F82748.h	2260;"	d
DMA_SAR2	.\Static_Code\IO_Map\MC56F82748.h	2264;"	d
DMA_SAR3	.\Static_Code\IO_Map\MC56F82748.h	2268;"	d
DMA_SAR_REG	.\Static_Code\IO_Map\MC56F82748.h	2129;"	d
DMA_SAR_SAR	.\Static_Code\IO_Map\MC56F82748.h	2172;"	d
DMA_SAR_SAR_MASK	.\Static_Code\IO_Map\MC56F82748.h	2170;"	d
DMA_SAR_SAR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2171;"	d
DOM_NONE	.\Generated_Code\PE_LDD.h	/^  DOM_NONE,$/;"	e	enum:__anon4
DOM_RUN	.\Generated_Code\PE_LDD.h	/^  DOM_RUN,$/;"	e	enum:__anon4
DOM_SLEEP	.\Generated_Code\PE_LDD.h	/^  DOM_SLEEP,$/;"	e	enum:__anon4
DOM_STOP	.\Generated_Code\PE_LDD.h	/^  DOM_STOP$/;"	e	enum:__anon4
DOM_WAIT	.\Generated_Code\PE_LDD.h	/^  DOM_WAIT,$/;"	e	enum:__anon4
DR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DR;                                     \/**< GPIO Data Register, offset: 0x1 *\/$/;"	m	struct:GPIO_MemMap
DRIVE	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DRIVE;                                  \/**< GPIO Drive Strength Control Register, offset: 0xB *\/$/;"	m	struct:GPIO_MemMap
DSR_BCR	.\Static_Code\IO_Map\MC56F82748.h	/^      uint32_t DSR_BCR;                                \/**< DMA Status Register \/ Byte Count Register, array offset: 0x84, array step: 0x8 *\/$/;"	m	union:DMA_MemMap::__anon57::__anon58
DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DTCNT0;                                 \/**< Deadtime Count Register 0, array offset: 0x18, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t DTCNT1;                                 \/**< Deadtime Count Register 1, array offset: 0x19, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
DTSRCSEL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t DTSRCSEL;                               \/**< PWM Source Select Register, offset: 0xC3 *\/$/;"	m	struct:PWM_MemMap
Data	.\Generated_Code\PE_LDD.h	/^  uint8_t *Data;                       \/* Message data buffer *\/$/;"	m	struct:__anon41
Day	.\Generated_Code\PE_LDD.h	/^  uint16_t Day;                        \/* Days (1 - 31) *\/$/;"	m	struct:__anon10
DayOfWeek	.\Generated_Code\PE_LDD.h	/^  uint16_t DayOfWeek;                  \/* Day of week (0-Sunday, .. 6-Saturday)  *\/$/;"	m	struct:__anon10
DerivativeGain	.\Static_Code\System\PE_Types.h	/^   Word16 DerivativeGain;$/;"	m	struct:__anon82
DerivativeGainScale	.\Static_Code\System\PE_Types.h	/^   Word16 DerivativeGainScale;$/;"	m	struct:__anon82
DeviceDataPrv__DEFAULT_RTOS_ALLOC	.\Generated_Code\BitIoLdd1.c	/^static BitIoLdd1_TDeviceData DeviceDataPrv__DEFAULT_RTOS_ALLOC;$/;"	v	file:
DeviceDataPrv__DEFAULT_RTOS_ALLOC	.\Generated_Code\TU1.c	/^static TU1_TDeviceData DeviceDataPrv__DEFAULT_RTOS_ALLOC;$/;"	v	file:
DownCounting	.\Generated_Code\PE_LDD.h	/^  unsigned int DownCounting : 1;       \/* Enables down counting *\/$/;"	m	struct:__anon30
EDGE_BOTH	.\Generated_Code\PE_LDD.h	/^  EDGE_BOTH$/;"	e	enum:__anon8
EDGE_FALLING	.\Generated_Code\PE_LDD.h	/^  EDGE_FALLING,$/;"	e	enum:__anon8
EDGE_NONE	.\Generated_Code\PE_LDD.h	/^  EDGE_NONE,$/;"	e	enum:__anon8
EDGE_RISING	.\Generated_Code\PE_LDD.h	/^  EDGE_RISING,$/;"	e	enum:__anon8
ENBL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t ENBL;                                   \/**< Timer Channel Enable Register, array offset: 0xF, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
ERR_ARBITR	.\Static_Code\System\PE_Error.h	30;"	d
ERR_BREAK	.\Static_Code\System\PE_Error.h	28;"	d
ERR_BUSOFF	.\Static_Code\System\PE_Error.h	21;"	d
ERR_BUSY	.\Static_Code\System\PE_Error.h	17;"	d
ERR_COMMON	.\Static_Code\System\PE_Error.h	34;"	d
ERR_CRC	.\Static_Code\System\PE_Error.h	29;"	d
ERR_DISABLED	.\Static_Code\System\PE_Error.h	16;"	d
ERR_ENABLED	.\Static_Code\System\PE_Error.h	15;"	d
ERR_FAILED	.\Static_Code\System\PE_Error.h	36;"	d
ERR_FAULT	.\Static_Code\System\PE_Error.h	27;"	d
ERR_FRAMING	.\Static_Code\System\PE_Error.h	23;"	d
ERR_IDLE	.\Static_Code\System\PE_Error.h	26;"	d
ERR_LINSYNC	.\Static_Code\System\PE_Error.h	35;"	d
ERR_MATH	.\Static_Code\System\PE_Error.h	14;"	d
ERR_NOISE	.\Static_Code\System\PE_Error.h	25;"	d
ERR_NOTAVAIL	.\Static_Code\System\PE_Error.h	18;"	d
ERR_OK	.\Static_Code\System\PE_Error.h	9;"	d
ERR_OVERFLOW	.\Static_Code\System\PE_Error.h	13;"	d
ERR_OVERRUN	.\Static_Code\System\PE_Error.h	22;"	d
ERR_PARAM_ADDRESS	.\Static_Code\System\PE_Error.h	47;"	d
ERR_PARAM_ADDRESS_TYPE	.\Static_Code\System\PE_Error.h	51;"	d
ERR_PARAM_ATTRIBUTE_SET	.\Static_Code\System\PE_Error.h	59;"	d
ERR_PARAM_BUFFER_COUNT	.\Static_Code\System\PE_Error.h	55;"	d
ERR_PARAM_CHIP_SELECT	.\Static_Code\System\PE_Error.h	58;"	d
ERR_PARAM_COMMAND	.\Static_Code\System\PE_Error.h	53;"	d
ERR_PARAM_COMMAND_TYPE	.\Static_Code\System\PE_Error.h	52;"	d
ERR_PARAM_CONDITION	.\Static_Code\System\PE_Error.h	61;"	d
ERR_PARAM_DATA	.\Static_Code\System\PE_Error.h	41;"	d
ERR_PARAM_GROUP	.\Static_Code\System\PE_Error.h	57;"	d
ERR_PARAM_HIGH_VALUE	.\Static_Code\System\PE_Error.h	46;"	d
ERR_PARAM_ID	.\Static_Code\System\PE_Error.h	56;"	d
ERR_PARAM_INDEX	.\Static_Code\System\PE_Error.h	40;"	d
ERR_PARAM_LENGTH	.\Static_Code\System\PE_Error.h	50;"	d
ERR_PARAM_LOW_VALUE	.\Static_Code\System\PE_Error.h	45;"	d
ERR_PARAM_MASK	.\Static_Code\System\PE_Error.h	38;"	d
ERR_PARAM_MODE	.\Static_Code\System\PE_Error.h	39;"	d
ERR_PARAM_PARITY	.\Static_Code\System\PE_Error.h	48;"	d
ERR_PARAM_RANGE	.\Static_Code\System\PE_Error.h	44;"	d
ERR_PARAM_RECIPIENT	.\Static_Code\System\PE_Error.h	54;"	d
ERR_PARAM_SAMPLE_COUNT	.\Static_Code\System\PE_Error.h	60;"	d
ERR_PARAM_SIZE	.\Static_Code\System\PE_Error.h	42;"	d
ERR_PARAM_TICKS	.\Static_Code\System\PE_Error.h	62;"	d
ERR_PARAM_VALUE	.\Static_Code\System\PE_Error.h	43;"	d
ERR_PARAM_WIDTH	.\Static_Code\System\PE_Error.h	49;"	d
ERR_PARITY	.\Static_Code\System\PE_Error.h	24;"	d
ERR_PROTECT	.\Static_Code\System\PE_Error.h	31;"	d
ERR_QFULL	.\Static_Code\System\PE_Error.h	37;"	d
ERR_RANGE	.\Static_Code\System\PE_Error.h	11;"	d
ERR_RXEMPTY	.\Static_Code\System\PE_Error.h	19;"	d
ERR_SPEED	.\Static_Code\System\PE_Error.h	10;"	d
ERR_TXFULL	.\Static_Code\System\PE_Error.h	20;"	d
ERR_UNDERFLOW	.\Static_Code\System\PE_Error.h	32;"	d
ERR_UNDERRUN	.\Static_Code\System\PE_Error.h	33;"	d
ERR_VALUE	.\Static_Code\System\PE_Error.h	12;"	d
EWM_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2377;"	d
EWM_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	2379;"	d
EWM_CLKCTRL	.\Static_Code\IO_Map\MC56F82748.h	2397;"	d
EWM_CLKCTRL_CLKSEL	.\Static_Code\IO_Map\MC56F82748.h	2364;"	d
EWM_CLKCTRL_CLKSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2362;"	d
EWM_CLKCTRL_CLKSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2363;"	d
EWM_CLKCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	2323;"	d
EWM_CLKPRESCALER	.\Static_Code\IO_Map\MC56F82748.h	2398;"	d
EWM_CLKPRESCALER_CLK_DIV	.\Static_Code\IO_Map\MC56F82748.h	2368;"	d
EWM_CLKPRESCALER_CLK_DIV_MASK	.\Static_Code\IO_Map\MC56F82748.h	2366;"	d
EWM_CLKPRESCALER_CLK_DIV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2367;"	d
EWM_CLKPRESCALER_REG	.\Static_Code\IO_Map\MC56F82748.h	2324;"	d
EWM_CMPH	.\Static_Code\IO_Map\MC56F82748.h	2396;"	d
EWM_CMPH_COMPAREH	.\Static_Code\IO_Map\MC56F82748.h	2360;"	d
EWM_CMPH_COMPAREH_MASK	.\Static_Code\IO_Map\MC56F82748.h	2358;"	d
EWM_CMPH_COMPAREH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2359;"	d
EWM_CMPH_REG	.\Static_Code\IO_Map\MC56F82748.h	2322;"	d
EWM_CMPL	.\Static_Code\IO_Map\MC56F82748.h	2395;"	d
EWM_CMPL_COMPAREL	.\Static_Code\IO_Map\MC56F82748.h	2356;"	d
EWM_CMPL_COMPAREL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2354;"	d
EWM_CMPL_COMPAREL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2355;"	d
EWM_CMPL_REG	.\Static_Code\IO_Map\MC56F82748.h	2321;"	d
EWM_CTRL	.\Static_Code\IO_Map\MC56F82748.h	2393;"	d
EWM_CTRL_ASSIN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2343;"	d
EWM_CTRL_ASSIN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2344;"	d
EWM_CTRL_EWMEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2341;"	d
EWM_CTRL_EWMEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2342;"	d
EWM_CTRL_INEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2345;"	d
EWM_CTRL_INEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2346;"	d
EWM_CTRL_INTEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2347;"	d
EWM_CTRL_INTEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2348;"	d
EWM_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	2319;"	d
EWM_Init	.\Static_Code\Peripherals\EWM_Init.c	/^void EWM_Init(void) {$/;"	f
EWM_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct EWM_MemMap {$/;"	s
EWM_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *EWM_MemMapPtr;$/;"	t
EWM_PDD_GetEnableDeviceStatus	.\Static_Code\PDD\EWM_PDD.h	65;"	d
EWM_PDD_H_	.\Static_Code\PDD\EWM_PDD.h	9;"	d
EWM_PDD_KEY_1	.\Static_Code\PDD\EWM_PDD.h	41;"	d
EWM_PDD_KEY_2	.\Static_Code\PDD\EWM_PDD.h	42;"	d
EWM_PDD_ReadClockControlReg	.\Static_Code\PDD\EWM_PDD.h	283;"	d
EWM_PDD_ReadClockPrescalerReg	.\Static_Code\PDD\EWM_PDD.h	321;"	d
EWM_PDD_ReadCompareHighReg	.\Static_Code\PDD\EWM_PDD.h	245;"	d
EWM_PDD_ReadCompareLowReg	.\Static_Code\PDD\EWM_PDD.h	207;"	d
EWM_PDD_ReadControlReg	.\Static_Code\PDD\EWM_PDD.h	150;"	d
EWM_PDD_SOURCE_BUS_CLK	.\Static_Code\PDD\EWM_PDD.h	47;"	d
EWM_PDD_SOURCE_ROSC_200K	.\Static_Code\PDD\EWM_PDD.h	48;"	d
EWM_PDD_SOURCE_ROSC_8M	.\Static_Code\PDD\EWM_PDD.h	45;"	d
EWM_PDD_SOURCE_XTAL_OSC	.\Static_Code\PDD\EWM_PDD.h	46;"	d
EWM_PDD_SelectClockSource	.\Static_Code\PDD\EWM_PDD.h	85;"	d
EWM_PDD_SetPrescaler	.\Static_Code\PDD\EWM_PDD.h	108;"	d
EWM_PDD_WriteClockControlReg	.\Static_Code\PDD\EWM_PDD.h	265;"	d
EWM_PDD_WriteClockPrescalerReg	.\Static_Code\PDD\EWM_PDD.h	303;"	d
EWM_PDD_WriteCompareHighReg	.\Static_Code\PDD\EWM_PDD.h	227;"	d
EWM_PDD_WriteCompareLowReg	.\Static_Code\PDD\EWM_PDD.h	189;"	d
EWM_PDD_WriteControlReg	.\Static_Code\PDD\EWM_PDD.h	132;"	d
EWM_PDD_WriteServiceReg	.\Static_Code\PDD\EWM_PDD.h	169;"	d
EWM_SERV	.\Static_Code\IO_Map\MC56F82748.h	2394;"	d
EWM_SERV_REG	.\Static_Code\IO_Map\MC56F82748.h	2320;"	d
EWM_SERV_SERVICE	.\Static_Code\IO_Map\MC56F82748.h	2352;"	d
EWM_SERV_SERVICE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2350;"	d
EWM_SERV_SERVICE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2351;"	d
EXECUTABLES	.\FLASH_SDM\sources.mk	/^EXECUTABLES := $/;"	m
EXECUTABLES_OS_FORMAT	.\FLASH_SDM\sources.mk	/^EXECUTABLES_OS_FORMAT := $/;"	m
EXECUTABLES_QUOTED	.\FLASH_SDM\sources.mk	/^EXECUTABLES_QUOTED := $/;"	m
EXT_MODE	.\Static_Code\System\PE_Const.h	24;"	d
EncPulses	.\Static_Code\System\PE_Types.h	/^        UWord16 EncPulses;$/;"	m	struct:__anon73
EncSignals	.\Static_Code\System\PE_Types.h	/^        decoder_sEncSignals  EncSignals;$/;"	m	union:__anon75
EnterCritical	.\Static_Code\System\PE_Types.h	685;"	d
Errors	.\Generated_Code\PE_LDD.h	/^  uint32_t Errors;                     \/* Error counter *\/$/;"	m	struct:__anon40
ExitCritical	.\Static_Code\System\PE_Types.h	703;"	d
F	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t F;                                      \/**< I2C Frequency Divider register, offset: 0x1 *\/$/;"	m	struct:I2C_MemMap
FALSE	.\Static_Code\System\PE_Types.h	17;"	d
FAULT	.\Static_Code\IO_Map\MC56F82748.h	/^  } FAULT[2];$/;"	m	struct:PWM_MemMap	typeref:struct:PWM_MemMap::__anon60
FCCOB0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB0;                                  \/**< Flash Common Command Object Registers, offset: 0x7 *\/$/;"	m	struct:FTFA_MemMap
FCCOB1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB1;                                  \/**< Flash Common Command Object Registers, offset: 0x6 *\/$/;"	m	struct:FTFA_MemMap
FCCOB2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB2;                                  \/**< Flash Common Command Object Registers, offset: 0x5 *\/$/;"	m	struct:FTFA_MemMap
FCCOB3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB3;                                  \/**< Flash Common Command Object Registers, offset: 0x4 *\/$/;"	m	struct:FTFA_MemMap
FCCOB4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB4;                                  \/**< Flash Common Command Object Registers, offset: 0xB *\/$/;"	m	struct:FTFA_MemMap
FCCOB5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB5;                                  \/**< Flash Common Command Object Registers, offset: 0xA *\/$/;"	m	struct:FTFA_MemMap
FCCOB6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB6;                                  \/**< Flash Common Command Object Registers, offset: 0x9 *\/$/;"	m	struct:FTFA_MemMap
FCCOB7	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB7;                                  \/**< Flash Common Command Object Registers, offset: 0x8 *\/$/;"	m	struct:FTFA_MemMap
FCCOB8	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB8;                                  \/**< Flash Common Command Object Registers, offset: 0xF *\/$/;"	m	struct:FTFA_MemMap
FCCOB9	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOB9;                                  \/**< Flash Common Command Object Registers, offset: 0xE *\/$/;"	m	struct:FTFA_MemMap
FCCOBA	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOBA;                                  \/**< Flash Common Command Object Registers, offset: 0xD *\/$/;"	m	struct:FTFA_MemMap
FCCOBB	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCCOBB;                                  \/**< Flash Common Command Object Registers, offset: 0xC *\/$/;"	m	struct:FTFA_MemMap
FCNFG	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FCNFG;                                   \/**< Flash Configuration Register, offset: 0x1 *\/$/;"	m	struct:FTFA_MemMap
FCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FCTRL;                                  \/**< Fault Control Register, array offset: 0xC6, array step: 0x4 *\/$/;"	m	struct:PWM_MemMap::__anon60
FFILT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FFILT;                                  \/**< Fault Filter Register, array offset: 0xC8, array step: 0x4 *\/$/;"	m	struct:PWM_MemMap::__anon60
FILT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FILT;                                   \/**< Timer Channel Input Filter Register, array offset: 0xB, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
FIM0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FIM0;                                   \/**< Fast Interrupt 0 Match Register, offset: 0xE *\/$/;"	m	struct:INTC_MemMap
FIM1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FIM1;                                   \/**< Fast Interrupt 1 Match Register, offset: 0x11 *\/$/;"	m	struct:INTC_MemMap
FIVAH0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FIVAH0;                                 \/**< Fast Interrupt 0 Vector Address High Register, offset: 0x10 *\/$/;"	m	struct:INTC_MemMap
FIVAH1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FIVAH1;                                 \/**< Fast Interrupt 1 Vector Address High Register, offset: 0x13 *\/$/;"	m	struct:INTC_MemMap
FIVAL0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FIVAL0;                                 \/**< Fast Interrupt 0 Vector Address Low Register, offset: 0xF *\/$/;"	m	struct:INTC_MemMap
FIVAL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FIVAL1;                                 \/**< Fast Interrupt 1 Vector Address Low Register, offset: 0x12 *\/$/;"	m	struct:INTC_MemMap
FLT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FLT;                                    \/**< I2C Programmable Input Glitch Filter register, offset: 0x6 *\/$/;"	m	struct:I2C_MemMap
FMC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2526;"	d
FMC_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	2528;"	d
FMC_DATA	.\Static_Code\IO_Map\MC56F82748.h	2579;"	d
FMC_DATAW0S0	.\Static_Code\IO_Map\MC56F82748.h	2560;"	d
FMC_DATAW0S1	.\Static_Code\IO_Map\MC56F82748.h	2561;"	d
FMC_DATAW0S2	.\Static_Code\IO_Map\MC56F82748.h	2562;"	d
FMC_DATAW0S3	.\Static_Code\IO_Map\MC56F82748.h	2563;"	d
FMC_DATAW1S0	.\Static_Code\IO_Map\MC56F82748.h	2564;"	d
FMC_DATAW1S1	.\Static_Code\IO_Map\MC56F82748.h	2565;"	d
FMC_DATAW1S2	.\Static_Code\IO_Map\MC56F82748.h	2566;"	d
FMC_DATAW1S3	.\Static_Code\IO_Map\MC56F82748.h	2567;"	d
FMC_DATAW2S0	.\Static_Code\IO_Map\MC56F82748.h	2568;"	d
FMC_DATAW2S1	.\Static_Code\IO_Map\MC56F82748.h	2569;"	d
FMC_DATAW2S2	.\Static_Code\IO_Map\MC56F82748.h	2570;"	d
FMC_DATAW2S3	.\Static_Code\IO_Map\MC56F82748.h	2571;"	d
FMC_DATAW3S0	.\Static_Code\IO_Map\MC56F82748.h	2572;"	d
FMC_DATAW3S1	.\Static_Code\IO_Map\MC56F82748.h	2573;"	d
FMC_DATAW3S2	.\Static_Code\IO_Map\MC56F82748.h	2574;"	d
FMC_DATAW3S3	.\Static_Code\IO_Map\MC56F82748.h	2575;"	d
FMC_DATA_REG	.\Static_Code\IO_Map\MC56F82748.h	2443;"	d
FMC_DATA_data	.\Static_Code\IO_Map\MC56F82748.h	2517;"	d
FMC_DATA_data_MASK	.\Static_Code\IO_Map\MC56F82748.h	2515;"	d
FMC_DATA_data_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2516;"	d
FMC_Init	.\Static_Code\Peripherals\FMC_Init.c	/^void FMC_Init(void) {$/;"	f
FMC_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct FMC_MemMap {$/;"	s
FMC_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *FMC_MemMapPtr;$/;"	t
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_1	.\Static_Code\PDD\FMC_PDD.h	45;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_10	.\Static_Code\PDD\FMC_PDD.h	54;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_11	.\Static_Code\PDD\FMC_PDD.h	55;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_12	.\Static_Code\PDD\FMC_PDD.h	56;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_13	.\Static_Code\PDD\FMC_PDD.h	57;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_14	.\Static_Code\PDD\FMC_PDD.h	58;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_15	.\Static_Code\PDD\FMC_PDD.h	59;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_16	.\Static_Code\PDD\FMC_PDD.h	60;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_2	.\Static_Code\PDD\FMC_PDD.h	46;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_3	.\Static_Code\PDD\FMC_PDD.h	47;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_4	.\Static_Code\PDD\FMC_PDD.h	48;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_5	.\Static_Code\PDD\FMC_PDD.h	49;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_6	.\Static_Code\PDD\FMC_PDD.h	50;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_7	.\Static_Code\PDD\FMC_PDD.h	51;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_8	.\Static_Code\PDD\FMC_PDD.h	52;"	d
FMC_PDD_ACCESS_TIME_SYSTEM_CLOCK_9	.\Static_Code\PDD\FMC_PDD.h	53;"	d
FMC_PDD_CACHE_INVALIDATE_WAY_0	.\Static_Code\PDD\FMC_PDD.h	70;"	d
FMC_PDD_CACHE_INVALIDATE_WAY_1	.\Static_Code\PDD\FMC_PDD.h	71;"	d
FMC_PDD_CACHE_INVALIDATE_WAY_2	.\Static_Code\PDD\FMC_PDD.h	72;"	d
FMC_PDD_CACHE_INVALIDATE_WAY_3	.\Static_Code\PDD\FMC_PDD.h	73;"	d
FMC_PDD_CACHE_INVALIDATE_WAY_ALL	.\Static_Code\PDD\FMC_PDD.h	74;"	d
FMC_PDD_CACHE_LOCK_WAY_0	.\Static_Code\PDD\FMC_PDD.h	63;"	d
FMC_PDD_CACHE_LOCK_WAY_1	.\Static_Code\PDD\FMC_PDD.h	64;"	d
FMC_PDD_CACHE_LOCK_WAY_2	.\Static_Code\PDD\FMC_PDD.h	65;"	d
FMC_PDD_CACHE_LOCK_WAY_3	.\Static_Code\PDD\FMC_PDD.h	66;"	d
FMC_PDD_CACHE_LOCK_WAY_ALL	.\Static_Code\PDD\FMC_PDD.h	67;"	d
FMC_PDD_EnableDataCache	.\Static_Code\PDD\FMC_PDD.h	517;"	d
FMC_PDD_EnableDataPrefetch	.\Static_Code\PDD\FMC_PDD.h	563;"	d
FMC_PDD_EnableInstructionCache	.\Static_Code\PDD\FMC_PDD.h	540;"	d
FMC_PDD_EnableInstructionPrefetch	.\Static_Code\PDD\FMC_PDD.h	586;"	d
FMC_PDD_EnableMaster0Prefetch	.\Static_Code\PDD\FMC_PDD.h	172;"	d
FMC_PDD_EnableMaster1Prefetch	.\Static_Code\PDD\FMC_PDD.h	149;"	d
FMC_PDD_EnableMaster2Prefetch	.\Static_Code\PDD\FMC_PDD.h	126;"	d
FMC_PDD_EnableMaster3Prefetch	.\Static_Code\PDD\FMC_PDD.h	103;"	d
FMC_PDD_EnableSingleEntryBuffer	.\Static_Code\PDD\FMC_PDD.h	609;"	d
FMC_PDD_GetCacheLockWay	.\Static_Code\PDD\FMC_PDD.h	386;"	d
FMC_PDD_GetMemoryWidth	.\Static_Code\PDD\FMC_PDD.h	470;"	d
FMC_PDD_GetReadWaitStateControl	.\Static_Code\PDD\FMC_PDD.h	343;"	d
FMC_PDD_H_	.\Static_Code\PDD\FMC_PDD.h	9;"	d
FMC_PDD_InvalidateFlashCache	.\Static_Code\PDD\FMC_PDD.h	448;"	d
FMC_PDD_InvalideFlashCacheWay	.\Static_Code\PDD\FMC_PDD.h	408;"	d
FMC_PDD_InvalidePrefetchSpeculationBuffer	.\Static_Code\PDD\FMC_PDD.h	430;"	d
FMC_PDD_LRU_REPLACEMENT_FOR_ALL_4_WAYS	.\Static_Code\PDD\FMC_PDD.h	81;"	d
FMC_PDD_LRU_WITH_01_IFETCHES_23_DATA_WAYS	.\Static_Code\PDD\FMC_PDD.h	82;"	d
FMC_PDD_LRU_WITH_02_IFETCHES_3_DATA_WAYS	.\Static_Code\PDD\FMC_PDD.h	83;"	d
FMC_PDD_MEMORY_WIDTH_32BITS	.\Static_Code\PDD\FMC_PDD.h	77;"	d
FMC_PDD_MEMORY_WIDTH_64BITS	.\Static_Code\PDD\FMC_PDD.h	78;"	d
FMC_PDD_NO_ACCESS	.\Static_Code\PDD\FMC_PDD.h	41;"	d
FMC_PDD_READ_ONLY_ACCESS	.\Static_Code\PDD\FMC_PDD.h	42;"	d
FMC_PDD_ReadCacheDataStorageWaySetReg	.\Static_Code\PDD\FMC_PDD.h	718;"	d
FMC_PDD_ReadCacheTagStorageWaySetReg	.\Static_Code\PDD\FMC_PDD.h	671;"	d
FMC_PDD_ReadFlashAccessProtectionReg	.\Static_Code\PDD\FMC_PDD.h	304;"	d
FMC_PDD_ReadFlashControlReg	.\Static_Code\PDD\FMC_PDD.h	629;"	d
FMC_PDD_SetCacheLockWayMask	.\Static_Code\PDD\FMC_PDD.h	364;"	d
FMC_PDD_SetCacheReplacementControl	.\Static_Code\PDD\FMC_PDD.h	492;"	d
FMC_PDD_SetMaster0AccessProtection	.\Static_Code\PDD\FMC_PDD.h	280;"	d
FMC_PDD_SetMaster1AccessProtection	.\Static_Code\PDD\FMC_PDD.h	252;"	d
FMC_PDD_SetMaster2AccessProtection	.\Static_Code\PDD\FMC_PDD.h	224;"	d
FMC_PDD_SetMaster3AccessProtection	.\Static_Code\PDD\FMC_PDD.h	196;"	d
FMC_PDD_WriteCacheDataStorageWaySetReg	.\Static_Code\PDD\FMC_PDD.h	741;"	d
FMC_PDD_WriteCacheTagStorageWaySetReg	.\Static_Code\PDD\FMC_PDD.h	694;"	d
FMC_PDD_WriteFlashAccessProtectionReg	.\Static_Code\PDD\FMC_PDD.h	325;"	d
FMC_PDD_WriteFlashControlReg	.\Static_Code\PDD\FMC_PDD.h	650;"	d
FMC_PFAPR	.\Static_Code\IO_Map\MC56F82748.h	2542;"	d
FMC_PFAPR_M0AP	.\Static_Code\IO_Map\MC56F82748.h	2462;"	d
FMC_PFAPR_M0AP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2460;"	d
FMC_PFAPR_M0AP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2461;"	d
FMC_PFAPR_M0PFD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2472;"	d
FMC_PFAPR_M0PFD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2473;"	d
FMC_PFAPR_M1AP	.\Static_Code\IO_Map\MC56F82748.h	2465;"	d
FMC_PFAPR_M1AP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2463;"	d
FMC_PFAPR_M1AP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2464;"	d
FMC_PFAPR_M1PFD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2474;"	d
FMC_PFAPR_M1PFD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2475;"	d
FMC_PFAPR_M2AP	.\Static_Code\IO_Map\MC56F82748.h	2468;"	d
FMC_PFAPR_M2AP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2466;"	d
FMC_PFAPR_M2AP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2467;"	d
FMC_PFAPR_M2PFD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2476;"	d
FMC_PFAPR_M2PFD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2477;"	d
FMC_PFAPR_M3AP	.\Static_Code\IO_Map\MC56F82748.h	2471;"	d
FMC_PFAPR_M3AP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2469;"	d
FMC_PFAPR_M3AP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2470;"	d
FMC_PFAPR_M3PFD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2478;"	d
FMC_PFAPR_M3PFD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2479;"	d
FMC_PFAPR_REG	.\Static_Code\IO_Map\MC56F82748.h	2440;"	d
FMC_PFB0CR	.\Static_Code\IO_Map\MC56F82748.h	2543;"	d
FMC_PFB0CR_B0DCE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2489;"	d
FMC_PFB0CR_B0DCE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2490;"	d
FMC_PFB0CR_B0DPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2485;"	d
FMC_PFB0CR_B0DPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2486;"	d
FMC_PFB0CR_B0ICE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2487;"	d
FMC_PFB0CR_B0ICE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2488;"	d
FMC_PFB0CR_B0IPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2483;"	d
FMC_PFB0CR_B0IPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2484;"	d
FMC_PFB0CR_B0MW	.\Static_Code\IO_Map\MC56F82748.h	2496;"	d
FMC_PFB0CR_B0MW_MASK	.\Static_Code\IO_Map\MC56F82748.h	2494;"	d
FMC_PFB0CR_B0MW_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2495;"	d
FMC_PFB0CR_B0RWSC	.\Static_Code\IO_Map\MC56F82748.h	2507;"	d
FMC_PFB0CR_B0RWSC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2505;"	d
FMC_PFB0CR_B0RWSC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2506;"	d
FMC_PFB0CR_B0SEBE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2481;"	d
FMC_PFB0CR_B0SEBE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2482;"	d
FMC_PFB0CR_CINV_WAY	.\Static_Code\IO_Map\MC56F82748.h	2501;"	d
FMC_PFB0CR_CINV_WAY_MASK	.\Static_Code\IO_Map\MC56F82748.h	2499;"	d
FMC_PFB0CR_CINV_WAY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2500;"	d
FMC_PFB0CR_CLCK_WAY	.\Static_Code\IO_Map\MC56F82748.h	2504;"	d
FMC_PFB0CR_CLCK_WAY_MASK	.\Static_Code\IO_Map\MC56F82748.h	2502;"	d
FMC_PFB0CR_CLCK_WAY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2503;"	d
FMC_PFB0CR_CRC	.\Static_Code\IO_Map\MC56F82748.h	2493;"	d
FMC_PFB0CR_CRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2491;"	d
FMC_PFB0CR_CRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2492;"	d
FMC_PFB0CR_REG	.\Static_Code\IO_Map\MC56F82748.h	2441;"	d
FMC_PFB0CR_S_B_INV_MASK	.\Static_Code\IO_Map\MC56F82748.h	2497;"	d
FMC_PFB0CR_S_B_INV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2498;"	d
FMC_TAGVD	.\Static_Code\IO_Map\MC56F82748.h	2578;"	d
FMC_TAGVDW0S0	.\Static_Code\IO_Map\MC56F82748.h	2544;"	d
FMC_TAGVDW0S1	.\Static_Code\IO_Map\MC56F82748.h	2545;"	d
FMC_TAGVDW0S2	.\Static_Code\IO_Map\MC56F82748.h	2546;"	d
FMC_TAGVDW0S3	.\Static_Code\IO_Map\MC56F82748.h	2547;"	d
FMC_TAGVDW1S0	.\Static_Code\IO_Map\MC56F82748.h	2548;"	d
FMC_TAGVDW1S1	.\Static_Code\IO_Map\MC56F82748.h	2549;"	d
FMC_TAGVDW1S2	.\Static_Code\IO_Map\MC56F82748.h	2550;"	d
FMC_TAGVDW1S3	.\Static_Code\IO_Map\MC56F82748.h	2551;"	d
FMC_TAGVDW2S0	.\Static_Code\IO_Map\MC56F82748.h	2552;"	d
FMC_TAGVDW2S1	.\Static_Code\IO_Map\MC56F82748.h	2553;"	d
FMC_TAGVDW2S2	.\Static_Code\IO_Map\MC56F82748.h	2554;"	d
FMC_TAGVDW2S3	.\Static_Code\IO_Map\MC56F82748.h	2555;"	d
FMC_TAGVDW3S0	.\Static_Code\IO_Map\MC56F82748.h	2556;"	d
FMC_TAGVDW3S1	.\Static_Code\IO_Map\MC56F82748.h	2557;"	d
FMC_TAGVDW3S2	.\Static_Code\IO_Map\MC56F82748.h	2558;"	d
FMC_TAGVDW3S3	.\Static_Code\IO_Map\MC56F82748.h	2559;"	d
FMC_TAGVD_REG	.\Static_Code\IO_Map\MC56F82748.h	2442;"	d
FMC_TAGVD_tag	.\Static_Code\IO_Map\MC56F82748.h	2513;"	d
FMC_TAGVD_tag_MASK	.\Static_Code\IO_Map\MC56F82748.h	2511;"	d
FMC_TAGVD_tag_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2512;"	d
FMC_TAGVD_valid_MASK	.\Static_Code\IO_Map\MC56F82748.h	2509;"	d
FMC_TAGVD_valid_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2510;"	d
FOPT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FOPT;                                    \/**< Flash Option Register, offset: 0x3 *\/$/;"	m	struct:FTFA_MemMap
FPR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t FPR;                                    \/**< CMP Filter Period Register, offset: 0x2 *\/$/;"	m	struct:CMP_MemMap
FPROT0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FPROT0;                                  \/**< Program Flash Protection Registers, offset: 0x13 *\/$/;"	m	struct:FTFA_MemMap
FPROT1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FPROT1;                                  \/**< Program Flash Protection Registers, offset: 0x12 *\/$/;"	m	struct:FTFA_MemMap
FPROT2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FPROT2;                                  \/**< Program Flash Protection Registers, offset: 0x11 *\/$/;"	m	struct:FTFA_MemMap
FPROT3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FPROT3;                                  \/**< Program Flash Protection Registers, offset: 0x10 *\/$/;"	m	struct:FTFA_MemMap
FRAC16	.\Sources\Events.h	61;"	d
FRAC32	.\Sources\Events.h	63;"	d
FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FRACVAL1;                               \/**< Fractional Value Register 1, array offset: 0x6, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FRACVAL2;                               \/**< Fractional Value Register 2, array offset: 0x8, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FRACVAL3;                               \/**< Fractional Value Register 3, array offset: 0xA, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FRACVAL4;                               \/**< Fractional Value Register 4, array offset: 0xC, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FRACVAL5;                               \/**< Fractional Value Register 5, array offset: 0xE, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
FRCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FRCTRL;                                 \/**< Fractional Control Register, array offset: 0x10, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
FSEC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FSEC;                                    \/**< Flash Security Register, offset: 0x2 *\/$/;"	m	struct:FTFA_MemMap
FSTAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t FSTAT;                                   \/**< Flash Status Register, offset: 0x0 *\/$/;"	m	struct:FTFA_MemMap
FSTS	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FSTS;                                   \/**< Fault Status Register, array offset: 0xC7, array step: 0x4 *\/$/;"	m	struct:PWM_MemMap::__anon60
FTFA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2779;"	d
FTFA_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	2781;"	d
FTFA_FCCOB0	.\Static_Code\IO_Map\MC56F82748.h	2802;"	d
FTFA_FCCOB0_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2722;"	d
FTFA_FCCOB0_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2720;"	d
FTFA_FCCOB0_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2721;"	d
FTFA_FCCOB0_REG	.\Static_Code\IO_Map\MC56F82748.h	2642;"	d
FTFA_FCCOB1	.\Static_Code\IO_Map\MC56F82748.h	2801;"	d
FTFA_FCCOB1_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2718;"	d
FTFA_FCCOB1_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2716;"	d
FTFA_FCCOB1_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2717;"	d
FTFA_FCCOB1_REG	.\Static_Code\IO_Map\MC56F82748.h	2641;"	d
FTFA_FCCOB2	.\Static_Code\IO_Map\MC56F82748.h	2800;"	d
FTFA_FCCOB2_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2714;"	d
FTFA_FCCOB2_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2712;"	d
FTFA_FCCOB2_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2713;"	d
FTFA_FCCOB2_REG	.\Static_Code\IO_Map\MC56F82748.h	2640;"	d
FTFA_FCCOB3	.\Static_Code\IO_Map\MC56F82748.h	2799;"	d
FTFA_FCCOB3_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2710;"	d
FTFA_FCCOB3_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2708;"	d
FTFA_FCCOB3_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2709;"	d
FTFA_FCCOB3_REG	.\Static_Code\IO_Map\MC56F82748.h	2639;"	d
FTFA_FCCOB4	.\Static_Code\IO_Map\MC56F82748.h	2806;"	d
FTFA_FCCOB4_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2738;"	d
FTFA_FCCOB4_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2736;"	d
FTFA_FCCOB4_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2737;"	d
FTFA_FCCOB4_REG	.\Static_Code\IO_Map\MC56F82748.h	2646;"	d
FTFA_FCCOB5	.\Static_Code\IO_Map\MC56F82748.h	2805;"	d
FTFA_FCCOB5_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2734;"	d
FTFA_FCCOB5_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2732;"	d
FTFA_FCCOB5_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2733;"	d
FTFA_FCCOB5_REG	.\Static_Code\IO_Map\MC56F82748.h	2645;"	d
FTFA_FCCOB6	.\Static_Code\IO_Map\MC56F82748.h	2804;"	d
FTFA_FCCOB6_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2730;"	d
FTFA_FCCOB6_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2728;"	d
FTFA_FCCOB6_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2729;"	d
FTFA_FCCOB6_REG	.\Static_Code\IO_Map\MC56F82748.h	2644;"	d
FTFA_FCCOB7	.\Static_Code\IO_Map\MC56F82748.h	2803;"	d
FTFA_FCCOB7_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2726;"	d
FTFA_FCCOB7_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2724;"	d
FTFA_FCCOB7_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2725;"	d
FTFA_FCCOB7_REG	.\Static_Code\IO_Map\MC56F82748.h	2643;"	d
FTFA_FCCOB8	.\Static_Code\IO_Map\MC56F82748.h	2810;"	d
FTFA_FCCOB8_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2754;"	d
FTFA_FCCOB8_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2752;"	d
FTFA_FCCOB8_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2753;"	d
FTFA_FCCOB8_REG	.\Static_Code\IO_Map\MC56F82748.h	2650;"	d
FTFA_FCCOB9	.\Static_Code\IO_Map\MC56F82748.h	2809;"	d
FTFA_FCCOB9_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2750;"	d
FTFA_FCCOB9_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2748;"	d
FTFA_FCCOB9_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2749;"	d
FTFA_FCCOB9_REG	.\Static_Code\IO_Map\MC56F82748.h	2649;"	d
FTFA_FCCOBA	.\Static_Code\IO_Map\MC56F82748.h	2808;"	d
FTFA_FCCOBA_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2746;"	d
FTFA_FCCOBA_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2744;"	d
FTFA_FCCOBA_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2745;"	d
FTFA_FCCOBA_REG	.\Static_Code\IO_Map\MC56F82748.h	2648;"	d
FTFA_FCCOBB	.\Static_Code\IO_Map\MC56F82748.h	2807;"	d
FTFA_FCCOBB_CCOBn	.\Static_Code\IO_Map\MC56F82748.h	2742;"	d
FTFA_FCCOBB_CCOBn_MASK	.\Static_Code\IO_Map\MC56F82748.h	2740;"	d
FTFA_FCCOBB_CCOBn_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2741;"	d
FTFA_FCCOBB_REG	.\Static_Code\IO_Map\MC56F82748.h	2647;"	d
FTFA_FCNFG	.\Static_Code\IO_Map\MC56F82748.h	2796;"	d
FTFA_FCNFG_CCIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2688;"	d
FTFA_FCNFG_CCIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2689;"	d
FTFA_FCNFG_ERSAREQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	2684;"	d
FTFA_FCNFG_ERSAREQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2685;"	d
FTFA_FCNFG_ERSSUSP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2682;"	d
FTFA_FCNFG_ERSSUSP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2683;"	d
FTFA_FCNFG_RDCOLLIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2686;"	d
FTFA_FCNFG_RDCOLLIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2687;"	d
FTFA_FCNFG_REG	.\Static_Code\IO_Map\MC56F82748.h	2636;"	d
FTFA_FOPT	.\Static_Code\IO_Map\MC56F82748.h	2798;"	d
FTFA_FOPT_OPT	.\Static_Code\IO_Map\MC56F82748.h	2706;"	d
FTFA_FOPT_OPT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2704;"	d
FTFA_FOPT_OPT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2705;"	d
FTFA_FOPT_REG	.\Static_Code\IO_Map\MC56F82748.h	2638;"	d
FTFA_FPROT0	.\Static_Code\IO_Map\MC56F82748.h	2814;"	d
FTFA_FPROT0_PROT	.\Static_Code\IO_Map\MC56F82748.h	2770;"	d
FTFA_FPROT0_PROT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2768;"	d
FTFA_FPROT0_PROT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2769;"	d
FTFA_FPROT0_REG	.\Static_Code\IO_Map\MC56F82748.h	2654;"	d
FTFA_FPROT1	.\Static_Code\IO_Map\MC56F82748.h	2813;"	d
FTFA_FPROT1_PROT	.\Static_Code\IO_Map\MC56F82748.h	2766;"	d
FTFA_FPROT1_PROT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2764;"	d
FTFA_FPROT1_PROT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2765;"	d
FTFA_FPROT1_REG	.\Static_Code\IO_Map\MC56F82748.h	2653;"	d
FTFA_FPROT2	.\Static_Code\IO_Map\MC56F82748.h	2812;"	d
FTFA_FPROT2_PROT	.\Static_Code\IO_Map\MC56F82748.h	2762;"	d
FTFA_FPROT2_PROT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2760;"	d
FTFA_FPROT2_PROT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2761;"	d
FTFA_FPROT2_REG	.\Static_Code\IO_Map\MC56F82748.h	2652;"	d
FTFA_FPROT3	.\Static_Code\IO_Map\MC56F82748.h	2811;"	d
FTFA_FPROT3_PROT	.\Static_Code\IO_Map\MC56F82748.h	2758;"	d
FTFA_FPROT3_PROT_MASK	.\Static_Code\IO_Map\MC56F82748.h	2756;"	d
FTFA_FPROT3_PROT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2757;"	d
FTFA_FPROT3_REG	.\Static_Code\IO_Map\MC56F82748.h	2651;"	d
FTFA_FSEC	.\Static_Code\IO_Map\MC56F82748.h	2797;"	d
FTFA_FSEC_FSLACC	.\Static_Code\IO_Map\MC56F82748.h	2696;"	d
FTFA_FSEC_FSLACC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2694;"	d
FTFA_FSEC_FSLACC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2695;"	d
FTFA_FSEC_KEYEN	.\Static_Code\IO_Map\MC56F82748.h	2702;"	d
FTFA_FSEC_KEYEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2700;"	d
FTFA_FSEC_KEYEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2701;"	d
FTFA_FSEC_MEEN	.\Static_Code\IO_Map\MC56F82748.h	2699;"	d
FTFA_FSEC_MEEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2697;"	d
FTFA_FSEC_MEEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2698;"	d
FTFA_FSEC_REG	.\Static_Code\IO_Map\MC56F82748.h	2637;"	d
FTFA_FSEC_SEC	.\Static_Code\IO_Map\MC56F82748.h	2693;"	d
FTFA_FSEC_SEC_MASK	.\Static_Code\IO_Map\MC56F82748.h	2691;"	d
FTFA_FSEC_SEC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2692;"	d
FTFA_FSTAT	.\Static_Code\IO_Map\MC56F82748.h	2795;"	d
FTFA_FSTAT_ACCERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	2675;"	d
FTFA_FSTAT_ACCERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2676;"	d
FTFA_FSTAT_CCIF_MASK	.\Static_Code\IO_Map\MC56F82748.h	2679;"	d
FTFA_FSTAT_CCIF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2680;"	d
FTFA_FSTAT_FPVIOL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2673;"	d
FTFA_FSTAT_FPVIOL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2674;"	d
FTFA_FSTAT_MGSTAT0_MASK	.\Static_Code\IO_Map\MC56F82748.h	2671;"	d
FTFA_FSTAT_MGSTAT0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2672;"	d
FTFA_FSTAT_RDCOLERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	2677;"	d
FTFA_FSTAT_RDCOLERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2678;"	d
FTFA_FSTAT_REG	.\Static_Code\IO_Map\MC56F82748.h	2635;"	d
FTFA_Init	.\Static_Code\Peripherals\FTFA_Init.c	/^void FTFA_Init(void) {$/;"	f
FTFA_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct FTFA_MemMap {$/;"	s
FTFA_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *FTFA_MemMapPtr;$/;"	t
FTFA_PDD_ACCESS_ERROR	.\Static_Code\PDD\FTFA_PDD.h	43;"	d
FTFA_PDD_BACKDOOR_KEY_DISABLED	.\Static_Code\PDD\FTFA_PDD.h	65;"	d
FTFA_PDD_BACKDOOR_KEY_ENABLED	.\Static_Code\PDD\FTFA_PDD.h	64;"	d
FTFA_PDD_COMMAND_COMPLETE	.\Static_Code\PDD\FTFA_PDD.h	41;"	d
FTFA_PDD_COMMAND_COMPLETE_INT	.\Static_Code\PDD\FTFA_PDD.h	48;"	d
FTFA_PDD_COMMAND_COMPLETION_STATUS	.\Static_Code\PDD\FTFA_PDD.h	45;"	d
FTFA_PDD_ClearAccessErrorFlag	.\Static_Code\PDD\FTFA_PDD.h	181;"	d
FTFA_PDD_ClearCommandCompleteFlag	.\Static_Code\PDD\FTFA_PDD.h	137;"	d
FTFA_PDD_ClearFlags	.\Static_Code\PDD\FTFA_PDD.h	244;"	d
FTFA_PDD_ClearProtectionViolationErrorFlag	.\Static_Code\PDD\FTFA_PDD.h	203;"	d
FTFA_PDD_ClearReadCollisionErrorFlag	.\Static_Code\PDD\FTFA_PDD.h	159;"	d
FTFA_PDD_DisableInterrupts	.\Static_Code\PDD\FTFA_PDD.h	344;"	d
FTFA_PDD_ERASE_ALL_BLOCKS	.\Static_Code\PDD\FTFA_PDD.h	60;"	d
FTFA_PDD_ERASE_FLASH_SECTOR	.\Static_Code\PDD\FTFA_PDD.h	56;"	d
FTFA_PDD_EnableInterrupts	.\Static_Code\PDD\FTFA_PDD.h	320;"	d
FTFA_PDD_FACTORY_ACCESS_DENIED	.\Static_Code\PDD\FTFA_PDD.h	73;"	d
FTFA_PDD_FACTORY_ACCESS_GRANTED	.\Static_Code\PDD\FTFA_PDD.h	72;"	d
FTFA_PDD_GetBackdoorEnable	.\Static_Code\PDD\FTFA_PDD.h	424;"	d
FTFA_PDD_GetEraseAllRequest	.\Static_Code\PDD\FTFA_PDD.h	368;"	d
FTFA_PDD_GetFactoryAccess	.\Static_Code\PDD\FTFA_PDD.h	476;"	d
FTFA_PDD_GetFlags	.\Static_Code\PDD\FTFA_PDD.h	262;"	d
FTFA_PDD_GetMassEraseEnable	.\Static_Code\PDD\FTFA_PDD.h	450;"	d
FTFA_PDD_GetPFlashProtectionState	.\Static_Code\PDD\FTFA_PDD.h	1357;"	d
FTFA_PDD_GetSecurityState	.\Static_Code\PDD\FTFA_PDD.h	504;"	d
FTFA_PDD_H_	.\Static_Code\PDD\FTFA_PDD.h	9;"	d
FTFA_PDD_LaunchCommand	.\Static_Code\PDD\FTFA_PDD.h	225;"	d
FTFA_PDD_MASS_ERASE_DISABLED	.\Static_Code\PDD\FTFA_PDD.h	69;"	d
FTFA_PDD_MASS_ERASE_ENABLED	.\Static_Code\PDD\FTFA_PDD.h	68;"	d
FTFA_PDD_PDD_READ_ONCE	.\Static_Code\PDD\FTFA_PDD.h	58;"	d
FTFA_PDD_PROGRAM_CHECK	.\Static_Code\PDD\FTFA_PDD.h	53;"	d
FTFA_PDD_PROGRAM_LONGWORD	.\Static_Code\PDD\FTFA_PDD.h	55;"	d
FTFA_PDD_PROGRAM_ONCE	.\Static_Code\PDD\FTFA_PDD.h	59;"	d
FTFA_PDD_PROTECTED	.\Static_Code\PDD\FTFA_PDD.h	81;"	d
FTFA_PDD_PROTECTION_VIOLATION	.\Static_Code\PDD\FTFA_PDD.h	44;"	d
FTFA_PDD_READ_1S_ALL_BLOCKS	.\Static_Code\PDD\FTFA_PDD.h	57;"	d
FTFA_PDD_READ_1S_SECTION	.\Static_Code\PDD\FTFA_PDD.h	52;"	d
FTFA_PDD_READ_COLLISION_ERROR	.\Static_Code\PDD\FTFA_PDD.h	42;"	d
FTFA_PDD_READ_COLLISION_ERROR_INT	.\Static_Code\PDD\FTFA_PDD.h	49;"	d
FTFA_PDD_READ_RESOURCE	.\Static_Code\PDD\FTFA_PDD.h	54;"	d
FTFA_PDD_ReadConfigReg	.\Static_Code\PDD\FTFA_PDD.h	280;"	d
FTFA_PDD_ReadFCCOB0Reg	.\Static_Code\PDD\FTFA_PDD.h	544;"	d
FTFA_PDD_ReadFCCOB1Reg	.\Static_Code\PDD\FTFA_PDD.h	562;"	d
FTFA_PDD_ReadFCCOB2Reg	.\Static_Code\PDD\FTFA_PDD.h	580;"	d
FTFA_PDD_ReadFCCOB3Reg	.\Static_Code\PDD\FTFA_PDD.h	598;"	d
FTFA_PDD_ReadFCCOB4Reg	.\Static_Code\PDD\FTFA_PDD.h	616;"	d
FTFA_PDD_ReadFCCOB5Reg	.\Static_Code\PDD\FTFA_PDD.h	634;"	d
FTFA_PDD_ReadFCCOB6Reg	.\Static_Code\PDD\FTFA_PDD.h	652;"	d
FTFA_PDD_ReadFCCOB7Reg	.\Static_Code\PDD\FTFA_PDD.h	670;"	d
FTFA_PDD_ReadFCCOB8Reg	.\Static_Code\PDD\FTFA_PDD.h	688;"	d
FTFA_PDD_ReadFCCOB9Reg	.\Static_Code\PDD\FTFA_PDD.h	706;"	d
FTFA_PDD_ReadFCCOBAReg	.\Static_Code\PDD\FTFA_PDD.h	724;"	d
FTFA_PDD_ReadFCCOBBReg	.\Static_Code\PDD\FTFA_PDD.h	742;"	d
FTFA_PDD_ReadOptionReg	.\Static_Code\PDD\FTFA_PDD.h	526;"	d
FTFA_PDD_ReadProgramFlashProtection0Reg	.\Static_Code\PDD\FTFA_PDD.h	1375;"	d
FTFA_PDD_ReadProgramFlashProtection1Reg	.\Static_Code\PDD\FTFA_PDD.h	1414;"	d
FTFA_PDD_ReadProgramFlashProtection2Reg	.\Static_Code\PDD\FTFA_PDD.h	1453;"	d
FTFA_PDD_ReadProgramFlashProtection3Reg	.\Static_Code\PDD\FTFA_PDD.h	1492;"	d
FTFA_PDD_ReadSecurityReg	.\Static_Code\PDD\FTFA_PDD.h	404;"	d
FTFA_PDD_ReadStatusReg	.\Static_Code\PDD\FTFA_PDD.h	99;"	d
FTFA_PDD_SECURED	.\Static_Code\PDD\FTFA_PDD.h	77;"	d
FTFA_PDD_SetFCCOBAddress	.\Static_Code\PDD\FTFA_PDD.h	1023;"	d
FTFA_PDD_SetFCCOBCommand	.\Static_Code\PDD\FTFA_PDD.h	1002;"	d
FTFA_PDD_SetFCCOBDataSize	.\Static_Code\PDD\FTFA_PDD.h	1055;"	d
FTFA_PDD_SetPFlashProtectionState	.\Static_Code\PDD\FTFA_PDD.h	1335;"	d
FTFA_PDD_SuspendErasing	.\Static_Code\PDD\FTFA_PDD.h	386;"	d
FTFA_PDD_UNPROTECTED	.\Static_Code\PDD\FTFA_PDD.h	80;"	d
FTFA_PDD_UNSECURED	.\Static_Code\PDD\FTFA_PDD.h	76;"	d
FTFA_PDD_VERIFY_BACKDOOR_ACCESS_KEY	.\Static_Code\PDD\FTFA_PDD.h	61;"	d
FTFA_PDD_WriteConfigReg	.\Static_Code\PDD\FTFA_PDD.h	300;"	d
FTFA_PDD_WriteFCCOB0Reg	.\Static_Code\PDD\FTFA_PDD.h	762;"	d
FTFA_PDD_WriteFCCOB1Reg	.\Static_Code\PDD\FTFA_PDD.h	782;"	d
FTFA_PDD_WriteFCCOB2Reg	.\Static_Code\PDD\FTFA_PDD.h	802;"	d
FTFA_PDD_WriteFCCOB3Reg	.\Static_Code\PDD\FTFA_PDD.h	822;"	d
FTFA_PDD_WriteFCCOB4Reg	.\Static_Code\PDD\FTFA_PDD.h	842;"	d
FTFA_PDD_WriteFCCOB5Reg	.\Static_Code\PDD\FTFA_PDD.h	862;"	d
FTFA_PDD_WriteFCCOB6Reg	.\Static_Code\PDD\FTFA_PDD.h	882;"	d
FTFA_PDD_WriteFCCOB7Reg	.\Static_Code\PDD\FTFA_PDD.h	902;"	d
FTFA_PDD_WriteFCCOB8Reg	.\Static_Code\PDD\FTFA_PDD.h	922;"	d
FTFA_PDD_WriteFCCOB9Reg	.\Static_Code\PDD\FTFA_PDD.h	942;"	d
FTFA_PDD_WriteFCCOBAReg	.\Static_Code\PDD\FTFA_PDD.h	962;"	d
FTFA_PDD_WriteFCCOBBReg	.\Static_Code\PDD\FTFA_PDD.h	982;"	d
FTFA_PDD_WriteFCCOBData0	.\Static_Code\PDD\FTFA_PDD.h	1082;"	d
FTFA_PDD_WriteFCCOBData1	.\Static_Code\PDD\FTFA_PDD.h	1102;"	d
FTFA_PDD_WriteFCCOBData2	.\Static_Code\PDD\FTFA_PDD.h	1122;"	d
FTFA_PDD_WriteFCCOBData3	.\Static_Code\PDD\FTFA_PDD.h	1142;"	d
FTFA_PDD_WriteFCCOBData4	.\Static_Code\PDD\FTFA_PDD.h	1162;"	d
FTFA_PDD_WriteFCCOBData5	.\Static_Code\PDD\FTFA_PDD.h	1182;"	d
FTFA_PDD_WriteFCCOBData6	.\Static_Code\PDD\FTFA_PDD.h	1202;"	d
FTFA_PDD_WriteFCCOBData7	.\Static_Code\PDD\FTFA_PDD.h	1222;"	d
FTFA_PDD_WriteFCCOBFirstLongWordData	.\Static_Code\PDD\FTFA_PDD.h	1263;"	d
FTFA_PDD_WriteFCCOBLongWordData	.\Static_Code\PDD\FTFA_PDD.h	1242;"	d
FTFA_PDD_WriteFCCOBSecondLongWordData	.\Static_Code\PDD\FTFA_PDD.h	1299;"	d
FTFA_PDD_WriteProgramFlashProtection0Reg	.\Static_Code\PDD\FTFA_PDD.h	1396;"	d
FTFA_PDD_WriteProgramFlashProtection1Reg	.\Static_Code\PDD\FTFA_PDD.h	1435;"	d
FTFA_PDD_WriteProgramFlashProtection2Reg	.\Static_Code\PDD\FTFA_PDD.h	1474;"	d
FTFA_PDD_WriteProgramFlashProtection3Reg	.\Static_Code\PDD\FTFA_PDD.h	1513;"	d
FTFA_PDD_WriteStatusReg	.\Static_Code\PDD\FTFA_PDD.h	119;"	d
FTFA_SAFE_ROUTINE_SIZE	.\Static_Code\System\CPU_Init.c	73;"	d	file:
FTFA_SafeRoutine	.\Static_Code\System\CPU_Init.c	/^  uint16_t FTFA_SafeRoutine[FTFA_SAFE_ROUTINE_SIZE]; \/* Safe routine buffer *\/$/;"	m	struct:__anon62	file:
FTFA_SafeRoutine	.\Static_Code\System\CPU_Init.c	/^const static uint16_t FTFA_SafeRoutine[FTFA_SAFE_ROUTINE_SIZE] = {$/;"	v	file:
FTFA_TSafeRoutine	.\Static_Code\System\CPU_Init.c	/^} FTFA_TSafeRoutine;                   \/* Safe routine buffer type *\/$/;"	t	typeref:struct:__anon62	file:
FTFA_TSafeRoutinePtr	.\Static_Code\System\CPU_Init.c	/^typedef void (* FTFA_TSafeRoutinePtr)(void); \/* Safe routine pointer type *\/$/;"	t	file:
FTST	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t FTST;                                   \/**< Fault Test Register, array offset: 0xC9, array step: 0x4 *\/$/;"	m	struct:PWM_MemMap::__anon60
Finit_56800_	.\Project_Settings\Startup_Code\56F83x_init.asm	/^Finit_56800_:$/;"	l
Finit_56800_END	.\Project_Settings\Startup_Code\56F83x_init.asm	/^Finit_56800_END:$/;"	l
FormErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t FormErrors;                 \/* Message form error counter *\/$/;"	m	struct:__anon40
Frac16	.\Static_Code\System\PE_Types.h	/^typedef short          Frac16;$/;"	t
Frac32	.\Static_Code\System\PE_Types.h	/^typedef long           Frac32;$/;"	t
FrameType	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_TFrameType FrameType;        \/* Type of the frame DATA\/REMOTE *\/$/;"	m	struct:__anon41
FramingErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t FramingErrors;              \/* Number of receiver framing errors *\/$/;"	m	struct:__anon19
GC1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GC1;                                    \/**< Gain Control 1 Register, offset: 0x50 *\/$/;"	m	struct:ADC_MemMap
GC2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GC2;                                    \/**< Gain Control 2 Register, offset: 0x51 *\/$/;"	m	struct:ADC_MemMap
GC3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GC3;                                    \/**< Gain Control 3 Register, offset: 0x6F *\/$/;"	m	struct:ADC_MemMap
GPIOA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2957;"	d
GPIOA_DDR	.\Static_Code\IO_Map\MC56F82748.h	2985;"	d
GPIOA_DR	.\Static_Code\IO_Map\MC56F82748.h	2984;"	d
GPIOA_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	2994;"	d
GPIOA_IAR	.\Static_Code\IO_Map\MC56F82748.h	2987;"	d
GPIOA_IENR	.\Static_Code\IO_Map\MC56F82748.h	2988;"	d
GPIOA_IESR	.\Static_Code\IO_Map\MC56F82748.h	2991;"	d
GPIOA_IPOLR	.\Static_Code\IO_Map\MC56F82748.h	2989;"	d
GPIOA_IPR	.\Static_Code\IO_Map\MC56F82748.h	2990;"	d
GPIOA_Init	.\Static_Code\Peripherals\GPIOA_Init.c	/^void GPIOA_Init(void) {$/;"	f
GPIOA_PER	.\Static_Code\IO_Map\MC56F82748.h	2986;"	d
GPIOA_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	2992;"	d
GPIOA_PUR	.\Static_Code\IO_Map\MC56F82748.h	2983;"	d
GPIOA_PUS	.\Static_Code\IO_Map\MC56F82748.h	2995;"	d
GPIOA_RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	2993;"	d
GPIOA_SRE	.\Static_Code\IO_Map\MC56F82748.h	2996;"	d
GPIOB_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2959;"	d
GPIOB_DDR	.\Static_Code\IO_Map\MC56F82748.h	3000;"	d
GPIOB_DR	.\Static_Code\IO_Map\MC56F82748.h	2999;"	d
GPIOB_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	3009;"	d
GPIOB_IAR	.\Static_Code\IO_Map\MC56F82748.h	3002;"	d
GPIOB_IENR	.\Static_Code\IO_Map\MC56F82748.h	3003;"	d
GPIOB_IESR	.\Static_Code\IO_Map\MC56F82748.h	3006;"	d
GPIOB_IPOLR	.\Static_Code\IO_Map\MC56F82748.h	3004;"	d
GPIOB_IPR	.\Static_Code\IO_Map\MC56F82748.h	3005;"	d
GPIOB_Init	.\Static_Code\Peripherals\GPIOB_Init.c	/^void GPIOB_Init(void) {$/;"	f
GPIOB_PER	.\Static_Code\IO_Map\MC56F82748.h	3001;"	d
GPIOB_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	3007;"	d
GPIOB_PUR	.\Static_Code\IO_Map\MC56F82748.h	2998;"	d
GPIOB_PUS	.\Static_Code\IO_Map\MC56F82748.h	3010;"	d
GPIOB_RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	3008;"	d
GPIOB_SRE	.\Static_Code\IO_Map\MC56F82748.h	3011;"	d
GPIOC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2961;"	d
GPIOC_DDR	.\Static_Code\IO_Map\MC56F82748.h	3015;"	d
GPIOC_DR	.\Static_Code\IO_Map\MC56F82748.h	3014;"	d
GPIOC_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	3024;"	d
GPIOC_IAR	.\Static_Code\IO_Map\MC56F82748.h	3017;"	d
GPIOC_IENR	.\Static_Code\IO_Map\MC56F82748.h	3018;"	d
GPIOC_IESR	.\Static_Code\IO_Map\MC56F82748.h	3021;"	d
GPIOC_IPOLR	.\Static_Code\IO_Map\MC56F82748.h	3019;"	d
GPIOC_IPR	.\Static_Code\IO_Map\MC56F82748.h	3020;"	d
GPIOC_Init	.\Static_Code\Peripherals\GPIOC_Init.c	/^void GPIOC_Init(void) {$/;"	f
GPIOC_PER	.\Static_Code\IO_Map\MC56F82748.h	3016;"	d
GPIOC_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	3022;"	d
GPIOC_PUR	.\Static_Code\IO_Map\MC56F82748.h	3013;"	d
GPIOC_PUS	.\Static_Code\IO_Map\MC56F82748.h	3025;"	d
GPIOC_RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	3023;"	d
GPIOC_SRE	.\Static_Code\IO_Map\MC56F82748.h	3026;"	d
GPIOD_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2963;"	d
GPIOD_DDR	.\Static_Code\IO_Map\MC56F82748.h	3030;"	d
GPIOD_DR	.\Static_Code\IO_Map\MC56F82748.h	3029;"	d
GPIOD_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	3039;"	d
GPIOD_IAR	.\Static_Code\IO_Map\MC56F82748.h	3032;"	d
GPIOD_IENR	.\Static_Code\IO_Map\MC56F82748.h	3033;"	d
GPIOD_IESR	.\Static_Code\IO_Map\MC56F82748.h	3036;"	d
GPIOD_IPOLR	.\Static_Code\IO_Map\MC56F82748.h	3034;"	d
GPIOD_IPR	.\Static_Code\IO_Map\MC56F82748.h	3035;"	d
GPIOD_Init	.\Static_Code\Peripherals\GPIOD_Init.c	/^void GPIOD_Init(void) {$/;"	f
GPIOD_PER	.\Static_Code\IO_Map\MC56F82748.h	3031;"	d
GPIOD_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	3037;"	d
GPIOD_PUR	.\Static_Code\IO_Map\MC56F82748.h	3028;"	d
GPIOD_PUS	.\Static_Code\IO_Map\MC56F82748.h	3040;"	d
GPIOD_RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	3038;"	d
GPIOD_SRE	.\Static_Code\IO_Map\MC56F82748.h	3041;"	d
GPIOE0_ClrVal	.\Generated_Code\GPIOE0.h	157;"	d
GPIOE0_GetVal	.\Generated_Code\GPIOE0.h	131;"	d
GPIOE0_PutVal	.\Generated_Code\GPIOE0.h	146;"	d
GPIOE0_SetVal	.\Generated_Code\GPIOE0.h	168;"	d
GPIOE_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2965;"	d
GPIOE_DDR	.\Static_Code\IO_Map\MC56F82748.h	3045;"	d
GPIOE_DR	.\Static_Code\IO_Map\MC56F82748.h	3044;"	d
GPIOE_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	3054;"	d
GPIOE_IAR	.\Static_Code\IO_Map\MC56F82748.h	3047;"	d
GPIOE_IENR	.\Static_Code\IO_Map\MC56F82748.h	3048;"	d
GPIOE_IESR	.\Static_Code\IO_Map\MC56F82748.h	3051;"	d
GPIOE_IPOLR	.\Static_Code\IO_Map\MC56F82748.h	3049;"	d
GPIOE_IPR	.\Static_Code\IO_Map\MC56F82748.h	3050;"	d
GPIOE_Init	.\Static_Code\Peripherals\GPIOE_Init.c	/^void GPIOE_Init(void) {$/;"	f
GPIOE_PER	.\Static_Code\IO_Map\MC56F82748.h	3046;"	d
GPIOE_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	3052;"	d
GPIOE_PUR	.\Static_Code\IO_Map\MC56F82748.h	3043;"	d
GPIOE_PUS	.\Static_Code\IO_Map\MC56F82748.h	3055;"	d
GPIOE_RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	3053;"	d
GPIOE_SRE	.\Static_Code\IO_Map\MC56F82748.h	3056;"	d
GPIOF_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	2967;"	d
GPIOF_DDR	.\Static_Code\IO_Map\MC56F82748.h	3060;"	d
GPIOF_DR	.\Static_Code\IO_Map\MC56F82748.h	3059;"	d
GPIOF_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	3069;"	d
GPIOF_IAR	.\Static_Code\IO_Map\MC56F82748.h	3062;"	d
GPIOF_IENR	.\Static_Code\IO_Map\MC56F82748.h	3063;"	d
GPIOF_IESR	.\Static_Code\IO_Map\MC56F82748.h	3066;"	d
GPIOF_IPOLR	.\Static_Code\IO_Map\MC56F82748.h	3064;"	d
GPIOF_IPR	.\Static_Code\IO_Map\MC56F82748.h	3065;"	d
GPIOF_Init	.\Static_Code\Peripherals\GPIOF_Init.c	/^void GPIOF_Init(void) {$/;"	f
GPIOF_PER	.\Static_Code\IO_Map\MC56F82748.h	3061;"	d
GPIOF_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	3067;"	d
GPIOF_PUR	.\Static_Code\IO_Map\MC56F82748.h	3058;"	d
GPIOF_PUS	.\Static_Code\IO_Map\MC56F82748.h	3070;"	d
GPIOF_RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	3068;"	d
GPIOF_SRE	.\Static_Code\IO_Map\MC56F82748.h	3071;"	d
GPIO_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	2969;"	d
GPIO_DDR_DD	.\Static_Code\IO_Map\MC56F82748.h	2904;"	d
GPIO_DDR_DD_MASK	.\Static_Code\IO_Map\MC56F82748.h	2902;"	d
GPIO_DDR_DD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2903;"	d
GPIO_DDR_REG	.\Static_Code\IO_Map\MC56F82748.h	2866;"	d
GPIO_DRIVE_DRIVE	.\Static_Code\IO_Map\MC56F82748.h	2940;"	d
GPIO_DRIVE_DRIVE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2938;"	d
GPIO_DRIVE_DRIVE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2939;"	d
GPIO_DRIVE_REG	.\Static_Code\IO_Map\MC56F82748.h	2875;"	d
GPIO_DR_D	.\Static_Code\IO_Map\MC56F82748.h	2900;"	d
GPIO_DR_D_MASK	.\Static_Code\IO_Map\MC56F82748.h	2898;"	d
GPIO_DR_D_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2899;"	d
GPIO_DR_REG	.\Static_Code\IO_Map\MC56F82748.h	2865;"	d
GPIO_IAR_IA	.\Static_Code\IO_Map\MC56F82748.h	2912;"	d
GPIO_IAR_IA_MASK	.\Static_Code\IO_Map\MC56F82748.h	2910;"	d
GPIO_IAR_IA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2911;"	d
GPIO_IAR_REG	.\Static_Code\IO_Map\MC56F82748.h	2868;"	d
GPIO_IENR_IEN	.\Static_Code\IO_Map\MC56F82748.h	2916;"	d
GPIO_IENR_IEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	2914;"	d
GPIO_IENR_IEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2915;"	d
GPIO_IENR_REG	.\Static_Code\IO_Map\MC56F82748.h	2869;"	d
GPIO_IESR_IES	.\Static_Code\IO_Map\MC56F82748.h	2928;"	d
GPIO_IESR_IES_MASK	.\Static_Code\IO_Map\MC56F82748.h	2926;"	d
GPIO_IESR_IES_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2927;"	d
GPIO_IESR_REG	.\Static_Code\IO_Map\MC56F82748.h	2872;"	d
GPIO_IPOLR_IPOL	.\Static_Code\IO_Map\MC56F82748.h	2920;"	d
GPIO_IPOLR_IPOL_MASK	.\Static_Code\IO_Map\MC56F82748.h	2918;"	d
GPIO_IPOLR_IPOL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2919;"	d
GPIO_IPOLR_REG	.\Static_Code\IO_Map\MC56F82748.h	2870;"	d
GPIO_IPR_IP	.\Static_Code\IO_Map\MC56F82748.h	2924;"	d
GPIO_IPR_IP_MASK	.\Static_Code\IO_Map\MC56F82748.h	2922;"	d
GPIO_IPR_IP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2923;"	d
GPIO_IPR_REG	.\Static_Code\IO_Map\MC56F82748.h	2871;"	d
GPIO_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct GPIO_MemMap {$/;"	s
GPIO_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *GPIO_MemMapPtr;$/;"	t
GPIO_PDD_AssertInterruptMask	.\Static_Code\PDD\GPIO_PDD.h	1027;"	d
GPIO_PDD_ClearInterruptFlags	.\Static_Code\PDD\GPIO_PDD.h	1308;"	d
GPIO_PDD_ClearPortDataOutputMask	.\Static_Code\PDD\GPIO_PDD.h	262;"	d
GPIO_PDD_DeassertInterruptMask	.\Static_Code\PDD\GPIO_PDD.h	1054;"	d
GPIO_PDD_DisableInterrupts	.\Static_Code\PDD\GPIO_PDD.h	1167;"	d
GPIO_PDD_EnableInterrupts	.\Static_Code\PDD\GPIO_PDD.h	1141;"	d
GPIO_PDD_EnablePeripheralModeMask	.\Static_Code\PDD\GPIO_PDD.h	936;"	d
GPIO_PDD_EnablePullResistorMask	.\Static_Code\PDD\GPIO_PDD.h	559;"	d
GPIO_PDD_GetEnableInterruptMask	.\Static_Code\PDD\GPIO_PDD.h	1197;"	d
GPIO_PDD_GetInterruptFlags	.\Static_Code\PDD\GPIO_PDD.h	1282;"	d
GPIO_PDD_GetPortData	.\Static_Code\PDD\GPIO_PDD.h	157;"	d
GPIO_PDD_GetPortDataInput	.\Static_Code\PDD\GPIO_PDD.h	80;"	d
GPIO_PDD_H_	.\Static_Code\PDD\GPIO_PDD.h	9;"	d
GPIO_PDD_PIN_0	.\Static_Code\PDD\GPIO_PDD.h	41;"	d
GPIO_PDD_PIN_1	.\Static_Code\PDD\GPIO_PDD.h	42;"	d
GPIO_PDD_PIN_10	.\Static_Code\PDD\GPIO_PDD.h	51;"	d
GPIO_PDD_PIN_11	.\Static_Code\PDD\GPIO_PDD.h	52;"	d
GPIO_PDD_PIN_12	.\Static_Code\PDD\GPIO_PDD.h	53;"	d
GPIO_PDD_PIN_13	.\Static_Code\PDD\GPIO_PDD.h	54;"	d
GPIO_PDD_PIN_14	.\Static_Code\PDD\GPIO_PDD.h	55;"	d
GPIO_PDD_PIN_15	.\Static_Code\PDD\GPIO_PDD.h	56;"	d
GPIO_PDD_PIN_2	.\Static_Code\PDD\GPIO_PDD.h	43;"	d
GPIO_PDD_PIN_3	.\Static_Code\PDD\GPIO_PDD.h	44;"	d
GPIO_PDD_PIN_4	.\Static_Code\PDD\GPIO_PDD.h	45;"	d
GPIO_PDD_PIN_5	.\Static_Code\PDD\GPIO_PDD.h	46;"	d
GPIO_PDD_PIN_6	.\Static_Code\PDD\GPIO_PDD.h	47;"	d
GPIO_PDD_PIN_7	.\Static_Code\PDD\GPIO_PDD.h	48;"	d
GPIO_PDD_PIN_8	.\Static_Code\PDD\GPIO_PDD.h	49;"	d
GPIO_PDD_PIN_9	.\Static_Code\PDD\GPIO_PDD.h	50;"	d
GPIO_PDD_ReadDataReg	.\Static_Code\PDD\GPIO_PDD.h	208;"	d
GPIO_PDD_ReadDriveStrengthReg	.\Static_Code\PDD\GPIO_PDD.h	811;"	d
GPIO_PDD_ReadInterruptAssertReg	.\Static_Code\PDD\GPIO_PDD.h	1115;"	d
GPIO_PDD_ReadInterruptEdgeSensitiveReg	.\Static_Code\PDD\GPIO_PDD.h	1399;"	d
GPIO_PDD_ReadInterruptEnableReg	.\Static_Code\PDD\GPIO_PDD.h	1258;"	d
GPIO_PDD_ReadInterruptPendingReg	.\Static_Code\PDD\GPIO_PDD.h	1338;"	d
GPIO_PDD_ReadInterruptPolarityReg	.\Static_Code\PDD\GPIO_PDD.h	1495;"	d
GPIO_PDD_ReadPeripheralEnableReg	.\Static_Code\PDD\GPIO_PDD.h	1000;"	d
GPIO_PDD_ReadPortDirectionReg	.\Static_Code\PDD\GPIO_PDD.h	433;"	d
GPIO_PDD_ReadPullEnableReg	.\Static_Code\PDD\GPIO_PDD.h	622;"	d
GPIO_PDD_ReadPullSelectReg	.\Static_Code\PDD\GPIO_PDD.h	528;"	d
GPIO_PDD_ReadPushPullReg	.\Static_Code\PDD\GPIO_PDD.h	716;"	d
GPIO_PDD_ReadRawDataReg	.\Static_Code\PDD\GPIO_PDD.h	106;"	d
GPIO_PDD_ReadSlewRateReg	.\Static_Code\PDD\GPIO_PDD.h	906;"	d
GPIO_PDD_SetDriveStrengthMask	.\Static_Code\PDD\GPIO_PDD.h	747;"	d
GPIO_PDD_SetInterruptPolarityMask	.\Static_Code\PDD\GPIO_PDD.h	1430;"	d
GPIO_PDD_SetPortData	.\Static_Code\PDD\GPIO_PDD.h	132;"	d
GPIO_PDD_SetPortDataOutputMask	.\Static_Code\PDD\GPIO_PDD.h	235;"	d
GPIO_PDD_SetPortDirectionMask	.\Static_Code\PDD\GPIO_PDD.h	370;"	d
GPIO_PDD_SetPortInputDirectionMask	.\Static_Code\PDD\GPIO_PDD.h	315;"	d
GPIO_PDD_SetPortOutputDirectionMask	.\Static_Code\PDD\GPIO_PDD.h	341;"	d
GPIO_PDD_SetPullSelectMask	.\Static_Code\PDD\GPIO_PDD.h	465;"	d
GPIO_PDD_SetPushPullMask	.\Static_Code\PDD\GPIO_PDD.h	653;"	d
GPIO_PDD_SetSlewRateMask	.\Static_Code\PDD\GPIO_PDD.h	842;"	d
GPIO_PDD_TogglePortDataOutputMask	.\Static_Code\PDD\GPIO_PDD.h	289;"	d
GPIO_PDD_WriteDataReg	.\Static_Code\PDD\GPIO_PDD.h	183;"	d
GPIO_PDD_WriteDriveStrengthReg	.\Static_Code\PDD\GPIO_PDD.h	782;"	d
GPIO_PDD_WriteInterruptAssertReg	.\Static_Code\PDD\GPIO_PDD.h	1085;"	d
GPIO_PDD_WriteInterruptEdgeSensitiveReg	.\Static_Code\PDD\GPIO_PDD.h	1369;"	d
GPIO_PDD_WriteInterruptEnableReg	.\Static_Code\PDD\GPIO_PDD.h	1228;"	d
GPIO_PDD_WriteInterruptPolarityReg	.\Static_Code\PDD\GPIO_PDD.h	1465;"	d
GPIO_PDD_WritePeripheralEnableReg	.\Static_Code\PDD\GPIO_PDD.h	971;"	d
GPIO_PDD_WritePortDirectionReg	.\Static_Code\PDD\GPIO_PDD.h	405;"	d
GPIO_PDD_WritePullEnableReg	.\Static_Code\PDD\GPIO_PDD.h	593;"	d
GPIO_PDD_WritePullSelectReg	.\Static_Code\PDD\GPIO_PDD.h	500;"	d
GPIO_PDD_WritePushPullReg	.\Static_Code\PDD\GPIO_PDD.h	688;"	d
GPIO_PDD_WriteSlewRateReg	.\Static_Code\PDD\GPIO_PDD.h	877;"	d
GPIO_PER_PE	.\Static_Code\IO_Map\MC56F82748.h	2908;"	d
GPIO_PER_PE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2906;"	d
GPIO_PER_PE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2907;"	d
GPIO_PER_REG	.\Static_Code\IO_Map\MC56F82748.h	2867;"	d
GPIO_PPMODE_PPMODE	.\Static_Code\IO_Map\MC56F82748.h	2932;"	d
GPIO_PPMODE_PPMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2930;"	d
GPIO_PPMODE_PPMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2931;"	d
GPIO_PPMODE_REG	.\Static_Code\IO_Map\MC56F82748.h	2873;"	d
GPIO_PUR_PU	.\Static_Code\IO_Map\MC56F82748.h	2896;"	d
GPIO_PUR_PU_MASK	.\Static_Code\IO_Map\MC56F82748.h	2894;"	d
GPIO_PUR_PU_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2895;"	d
GPIO_PUR_REG	.\Static_Code\IO_Map\MC56F82748.h	2864;"	d
GPIO_PUS_PUS	.\Static_Code\IO_Map\MC56F82748.h	2944;"	d
GPIO_PUS_PUS_MASK	.\Static_Code\IO_Map\MC56F82748.h	2942;"	d
GPIO_PUS_PUS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2943;"	d
GPIO_PUS_REG	.\Static_Code\IO_Map\MC56F82748.h	2876;"	d
GPIO_RAWDATA_RAW_DATA	.\Static_Code\IO_Map\MC56F82748.h	2936;"	d
GPIO_RAWDATA_RAW_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	2934;"	d
GPIO_RAWDATA_RAW_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2935;"	d
GPIO_RAWDATA_REG	.\Static_Code\IO_Map\MC56F82748.h	2874;"	d
GPIO_SRE_REG	.\Static_Code\IO_Map\MC56F82748.h	2877;"	d
GPIO_SRE_SRE	.\Static_Code\IO_Map\MC56F82748.h	2948;"	d
GPIO_SRE_SRE_MASK	.\Static_Code\IO_Map\MC56F82748.h	2946;"	d
GPIO_SRE_SRE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	2947;"	d
GPSAL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSAL;                                  \/**< GPIOA LSBs Peripheral Select Register, offset: 0x17 *\/$/;"	m	struct:SIM_MemMap
GPSBL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSBL;                                  \/**< GPIOB LSBs Peripheral Select Register, offset: 0x18 *\/$/;"	m	struct:SIM_MemMap
GPSCH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSCH;                                  \/**< GPIOC MSBs Peripheral Select Register, offset: 0x1A *\/$/;"	m	struct:SIM_MemMap
GPSCL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSCL;                                  \/**< GPIOC LSBs Peripheral Select Register, offset: 0x19 *\/$/;"	m	struct:SIM_MemMap
GPSEL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSEL;                                  \/**< GPIOE LSBs Peripheral Select Register, offset: 0x1C *\/$/;"	m	struct:SIM_MemMap
GPSFH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSFH;                                  \/**< GPIOF MSBs Peripheral Select Register, offset: 0x1F *\/$/;"	m	struct:SIM_MemMap
GPSFL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t GPSFL;                                  \/**< GPIOF LSBs Peripheral Select Register, offset: 0x1E *\/$/;"	m	struct:SIM_MemMap
GROUPS	.\Static_Code\IO_Map\MC56F82748.h	/^  } GROUPS[4];$/;"	m	struct:TMR_MemMap	typeref:struct:TMR_MemMap::__anon61
HIGH_SPEED	.\Static_Code\System\PE_Const.h	10;"	d
HILIM	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t HILIM[16];                              \/**< ADC High Limit Registers, array offset: 0x2E, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
HILIMSTAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t HILIMSTAT;                              \/**< ADC High Limit Status Register, offset: 0xC *\/$/;"	m	struct:ADC_MemMap
HILIMSTAT2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t HILIMSTAT2;                             \/**< ADC High Limit Status Register 2, offset: 0x5D *\/$/;"	m	struct:ADC_MemMap
HILIM_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t HILIM_2[4];                             \/**< ADC High Limit Registers 2, array offset: 0x67, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
HOLD	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t HOLD;                                   \/**< Timer Channel Hold Register, array offset: 0x4, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
HighLimitValue	.\Generated_Code\PE_LDD.h	/^  uint16_t HighLimitValue;             \/*!< High limit value *\/$/;"	m	struct:__anon44
Hour	.\Generated_Code\PE_LDD.h	/^  uint16_t Hour;                       \/* Hours (0 - 23) *\/$/;"	m	struct:__anon9
I2C_A1	.\Static_Code\IO_Map\MC56F82748.h	3278;"	d
I2C_A1_AD	.\Static_Code\IO_Map\MC56F82748.h	3149;"	d
I2C_A1_AD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3147;"	d
I2C_A1_AD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3148;"	d
I2C_A1_REG	.\Static_Code\IO_Map\MC56F82748.h	3119;"	d
I2C_A2	.\Static_Code\IO_Map\MC56F82748.h	3287;"	d
I2C_A2_REG	.\Static_Code\IO_Map\MC56F82748.h	3128;"	d
I2C_A2_SAD	.\Static_Code\IO_Map\MC56F82748.h	3245;"	d
I2C_A2_SAD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3243;"	d
I2C_A2_SAD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3244;"	d
I2C_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	3262;"	d
I2C_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	3264;"	d
I2C_C1	.\Static_Code\IO_Map\MC56F82748.h	3280;"	d
I2C_C1_DMAEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3158;"	d
I2C_C1_DMAEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3159;"	d
I2C_C1_IICEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3172;"	d
I2C_C1_IICEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3173;"	d
I2C_C1_IICIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3170;"	d
I2C_C1_IICIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3171;"	d
I2C_C1_MST_MASK	.\Static_Code\IO_Map\MC56F82748.h	3168;"	d
I2C_C1_MST_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3169;"	d
I2C_C1_REG	.\Static_Code\IO_Map\MC56F82748.h	3121;"	d
I2C_C1_RSTA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3162;"	d
I2C_C1_RSTA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3163;"	d
I2C_C1_TXAK_MASK	.\Static_Code\IO_Map\MC56F82748.h	3164;"	d
I2C_C1_TXAK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3165;"	d
I2C_C1_TX_MASK	.\Static_Code\IO_Map\MC56F82748.h	3166;"	d
I2C_C1_TX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3167;"	d
I2C_C1_WUEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3160;"	d
I2C_C1_WUEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3161;"	d
I2C_C2	.\Static_Code\IO_Map\MC56F82748.h	3283;"	d
I2C_C2_AD	.\Static_Code\IO_Map\MC56F82748.h	3198;"	d
I2C_C2_ADEXT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3205;"	d
I2C_C2_ADEXT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3206;"	d
I2C_C2_AD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3196;"	d
I2C_C2_AD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3197;"	d
I2C_C2_GCAEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3207;"	d
I2C_C2_GCAEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3208;"	d
I2C_C2_HDRS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3203;"	d
I2C_C2_HDRS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3204;"	d
I2C_C2_REG	.\Static_Code\IO_Map\MC56F82748.h	3124;"	d
I2C_C2_RMEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3199;"	d
I2C_C2_RMEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3200;"	d
I2C_C2_SBRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3201;"	d
I2C_C2_SBRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3202;"	d
I2C_D	.\Static_Code\IO_Map\MC56F82748.h	3282;"	d
I2C_D_DATA	.\Static_Code\IO_Map\MC56F82748.h	3194;"	d
I2C_D_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3192;"	d
I2C_D_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3193;"	d
I2C_D_REG	.\Static_Code\IO_Map\MC56F82748.h	3123;"	d
I2C_F	.\Static_Code\IO_Map\MC56F82748.h	3279;"	d
I2C_FLT	.\Static_Code\IO_Map\MC56F82748.h	3284;"	d
I2C_FLT_FLT	.\Static_Code\IO_Map\MC56F82748.h	3212;"	d
I2C_FLT_FLT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3210;"	d
I2C_FLT_FLT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3211;"	d
I2C_FLT_REG	.\Static_Code\IO_Map\MC56F82748.h	3125;"	d
I2C_FLT_SHEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3219;"	d
I2C_FLT_SHEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3220;"	d
I2C_FLT_SSIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3215;"	d
I2C_FLT_SSIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3216;"	d
I2C_FLT_STARTF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3213;"	d
I2C_FLT_STARTF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3214;"	d
I2C_FLT_STOPF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3217;"	d
I2C_FLT_STOPF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3218;"	d
I2C_F_ICR	.\Static_Code\IO_Map\MC56F82748.h	3153;"	d
I2C_F_ICR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3151;"	d
I2C_F_ICR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3152;"	d
I2C_F_MULT	.\Static_Code\IO_Map\MC56F82748.h	3156;"	d
I2C_F_MULT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3154;"	d
I2C_F_MULT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3155;"	d
I2C_F_REG	.\Static_Code\IO_Map\MC56F82748.h	3120;"	d
I2C_Init	.\Static_Code\Peripherals\I2C_Init.c	/^void I2C_Init(void) {$/;"	f
I2C_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct I2C_MemMap {$/;"	s
I2C_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *I2C_MemMapPtr;$/;"	t
I2C_PDD_ACK_AFTER_RX_DATA	.\Static_Code\PDD\I2C_PDD.h	80;"	d
I2C_PDD_ACK_FOLLOWING_RX_DATA	.\Static_Code\PDD\I2C_PDD.h	79;"	d
I2C_PDD_ADDRESSED_AS_SLAVE	.\Static_Code\PDD\I2C_PDD.h	48;"	d
I2C_PDD_ARBIT_LOST	.\Static_Code\PDD\I2C_PDD.h	46;"	d
I2C_PDD_BUS_BUSY	.\Static_Code\PDD\I2C_PDD.h	76;"	d
I2C_PDD_BUS_CLOCK	.\Static_Code\PDD\I2C_PDD.h	83;"	d
I2C_PDD_BUS_CLOCK_DIV64	.\Static_Code\PDD\I2C_PDD.h	84;"	d
I2C_PDD_BUS_IDLE	.\Static_Code\PDD\I2C_PDD.h	75;"	d
I2C_PDD_BUS_IS_BUSY	.\Static_Code\PDD\I2C_PDD.h	47;"	d
I2C_PDD_BUS_START_FLAG	.\Static_Code\PDD\I2C_PDD.h	53;"	d
I2C_PDD_BUS_STOP_FLAG	.\Static_Code\PDD\I2C_PDD.h	52;"	d
I2C_PDD_ClearBusStatusInterruptFlags	.\Static_Code\PDD\I2C_PDD.h	943;"	d
I2C_PDD_ClearInterruptFlags	.\Static_Code\PDD\I2C_PDD.h	619;"	d
I2C_PDD_ClearSCLTimeoutInterruptFlags	.\Static_Code\PDD\I2C_PDD.h	1281;"	d
I2C_PDD_DisableBusStopOrStartInterrupt	.\Static_Code\PDD\I2C_PDD.h	987;"	d
I2C_PDD_DisableInterrupt	.\Static_Code\PDD\I2C_PDD.h	325;"	d
I2C_PDD_DisableSCLTimeoutInterrupt	.\Static_Code\PDD\I2C_PDD.h	1325;"	d
I2C_PDD_EnableAddressExtension	.\Static_Code\PDD\I2C_PDD.h	725;"	d
I2C_PDD_EnableBusStopOrStartInterrupt	.\Static_Code\PDD\I2C_PDD.h	965;"	d
I2C_PDD_EnableDevice	.\Static_Code\PDD\I2C_PDD.h	287;"	d
I2C_PDD_EnableDmaRequest	.\Static_Code\PDD\I2C_PDD.h	495;"	d
I2C_PDD_EnableFastSmBusNackAck	.\Static_Code\PDD\I2C_PDD.h	1115;"	d
I2C_PDD_EnableGeneralCallAddress	.\Static_Code\PDD\I2C_PDD.h	702;"	d
I2C_PDD_EnableInterrupt	.\Static_Code\PDD\I2C_PDD.h	307;"	d
I2C_PDD_EnableRangeAddressMatch	.\Static_Code\PDD\I2C_PDD.h	807;"	d
I2C_PDD_EnableSCLTimeoutInterrupt	.\Static_Code\PDD\I2C_PDD.h	1303;"	d
I2C_PDD_EnableSecondI2CAddress	.\Static_Code\PDD\I2C_PDD.h	1198;"	d
I2C_PDD_EnableSlaveBaudControlByMaster	.\Static_Code\PDD\I2C_PDD.h	784;"	d
I2C_PDD_EnableSmBusAlertResponseAddress	.\Static_Code\PDD\I2C_PDD.h	1166;"	d
I2C_PDD_EnableStopHoldOffMode	.\Static_Code\PDD\I2C_PDD.h	895;"	d
I2C_PDD_EnableTransmitAcknowledge	.\Static_Code\PDD\I2C_PDD.h	431;"	d
I2C_PDD_EnableWakeUp	.\Static_Code\PDD\I2C_PDD.h	472;"	d
I2C_PDD_FREQUENCY_MUL_1	.\Static_Code\PDD\I2C_PDD.h	62;"	d
I2C_PDD_FREQUENCY_MUL_2	.\Static_Code\PDD\I2C_PDD.h	63;"	d
I2C_PDD_FREQUENCY_MUL_4	.\Static_Code\PDD\I2C_PDD.h	64;"	d
I2C_PDD_GetBusStatus	.\Static_Code\PDD\I2C_PDD.h	573;"	d
I2C_PDD_GetFastSmBusAcknowledge	.\Static_Code\PDD\I2C_PDD.h	1144;"	d
I2C_PDD_GetInterruptFlags	.\Static_Code\PDD\I2C_PDD.h	591;"	d
I2C_PDD_GetMasterMode	.\Static_Code\PDD\I2C_PDD.h	367;"	d
I2C_PDD_GetSCLTimeoutInterruptFlags	.\Static_Code\PDD\I2C_PDD.h	1258;"	d
I2C_PDD_GetTransmitMode	.\Static_Code\PDD\I2C_PDD.h	409;"	d
I2C_PDD_H_	.\Static_Code\PDD\I2C_PDD.h	9;"	d
I2C_PDD_INTERRUPT_FLAG	.\Static_Code\PDD\I2C_PDD.h	43;"	d
I2C_PDD_MASTER_MODE	.\Static_Code\PDD\I2C_PDD.h	67;"	d
I2C_PDD_RANGE_ADDRESS_MATCH	.\Static_Code\PDD\I2C_PDD.h	45;"	d
I2C_PDD_RX_ACKNOWLEDGE	.\Static_Code\PDD\I2C_PDD.h	42;"	d
I2C_PDD_RX_DIRECTION	.\Static_Code\PDD\I2C_PDD.h	72;"	d
I2C_PDD_ReadAddress1Reg	.\Static_Code\PDD\I2C_PDD.h	156;"	d
I2C_PDD_ReadAddress2Reg	.\Static_Code\PDD\I2C_PDD.h	1410;"	d
I2C_PDD_ReadBusStatusFlags	.\Static_Code\PDD\I2C_PDD.h	923;"	d
I2C_PDD_ReadControl1Reg	.\Static_Code\PDD\I2C_PDD.h	515;"	d
I2C_PDD_ReadControl2Reg	.\Static_Code\PDD\I2C_PDD.h	827;"	d
I2C_PDD_ReadDataReg	.\Static_Code\PDD\I2C_PDD.h	662;"	d
I2C_PDD_ReadFrequencyDividerReg	.\Static_Code\PDD\I2C_PDD.h	245;"	d
I2C_PDD_ReadInputGlitchFilterReg	.\Static_Code\PDD\I2C_PDD.h	1009;"	d
I2C_PDD_ReadRangeAddressReg	.\Static_Code\PDD\I2C_PDD.h	1072;"	d
I2C_PDD_ReadSMBusControlAndStatusReg	.\Static_Code\PDD\I2C_PDD.h	1347;"	d
I2C_PDD_ReadSclLowTimeoutHighReg	.\Static_Code\PDD\I2C_PDD.h	1480;"	d
I2C_PDD_ReadSclLowTimeoutLowReg	.\Static_Code\PDD\I2C_PDD.h	1519;"	d
I2C_PDD_ReadStatusReg	.\Static_Code\PDD\I2C_PDD.h	554;"	d
I2C_PDD_RepeatStart	.\Static_Code\PDD\I2C_PDD.h	451;"	d
I2C_PDD_SCL_HI_AND_SDA_HI_TIMEOUT	.\Static_Code\PDD\I2C_PDD.h	58;"	d
I2C_PDD_SCL_HI_AND_SDA_LOW_TIMEOUT	.\Static_Code\PDD\I2C_PDD.h	59;"	d
I2C_PDD_SCL_LOW_TIMEOUT	.\Static_Code\PDD\I2C_PDD.h	57;"	d
I2C_PDD_SLAVE_MODE	.\Static_Code\PDD\I2C_PDD.h	68;"	d
I2C_PDD_SLAVE_TRANSMIT	.\Static_Code\PDD\I2C_PDD.h	44;"	d
I2C_PDD_SetFrequencyDivider	.\Static_Code\PDD\I2C_PDD.h	198;"	d
I2C_PDD_SetFrequencyMultiplier	.\Static_Code\PDD\I2C_PDD.h	223;"	d
I2C_PDD_SetInputGlitchFilter	.\Static_Code\PDD\I2C_PDD.h	869;"	d
I2C_PDD_SetMasterMode	.\Static_Code\PDD\I2C_PDD.h	346;"	d
I2C_PDD_SetPadsHighDriveMode	.\Static_Code\PDD\I2C_PDD.h	763;"	d
I2C_PDD_SetPadsNormalDriveMode	.\Static_Code\PDD\I2C_PDD.h	745;"	d
I2C_PDD_SetRangeAddress	.\Static_Code\PDD\I2C_PDD.h	1050;"	d
I2C_PDD_SetSCLLowTimeout	.\Static_Code\PDD\I2C_PDD.h	1453;"	d
I2C_PDD_SetSCLTimeoutBusClockSource	.\Static_Code\PDD\I2C_PDD.h	1230;"	d
I2C_PDD_SetSMBusSlaveAddress	.\Static_Code\PDD\I2C_PDD.h	1388;"	d
I2C_PDD_SetSlaveAddress10bits	.\Static_Code\PDD\I2C_PDD.h	129;"	d
I2C_PDD_SetSlaveAddress7bits	.\Static_Code\PDD\I2C_PDD.h	103;"	d
I2C_PDD_SetTransmitMode	.\Static_Code\PDD\I2C_PDD.h	388;"	d
I2C_PDD_TX_COMPLETE	.\Static_Code\PDD\I2C_PDD.h	49;"	d
I2C_PDD_TX_DIRECTION	.\Static_Code\PDD\I2C_PDD.h	71;"	d
I2C_PDD_WriteAddress1Reg	.\Static_Code\PDD\I2C_PDD.h	177;"	d
I2C_PDD_WriteAddress2Reg	.\Static_Code\PDD\I2C_PDD.h	1431;"	d
I2C_PDD_WriteControl1Reg	.\Static_Code\PDD\I2C_PDD.h	536;"	d
I2C_PDD_WriteControl2Reg	.\Static_Code\PDD\I2C_PDD.h	848;"	d
I2C_PDD_WriteDataReg	.\Static_Code\PDD\I2C_PDD.h	681;"	d
I2C_PDD_WriteFrequencyDividerReg	.\Static_Code\PDD\I2C_PDD.h	266;"	d
I2C_PDD_WriteInputGlitchFilterReg	.\Static_Code\PDD\I2C_PDD.h	1030;"	d
I2C_PDD_WriteRangeAddressReg	.\Static_Code\PDD\I2C_PDD.h	1093;"	d
I2C_PDD_WriteSMBusControlAndStatusReg	.\Static_Code\PDD\I2C_PDD.h	1368;"	d
I2C_PDD_WriteSclLowTimeoutHighReg	.\Static_Code\PDD\I2C_PDD.h	1501;"	d
I2C_PDD_WriteSclLowTimeoutLowReg	.\Static_Code\PDD\I2C_PDD.h	1540;"	d
I2C_PDD_WriteStatusReg	.\Static_Code\PDD\I2C_PDD.h	644;"	d
I2C_RA	.\Static_Code\IO_Map\MC56F82748.h	3285;"	d
I2C_RA_RAD	.\Static_Code\IO_Map\MC56F82748.h	3224;"	d
I2C_RA_RAD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3222;"	d
I2C_RA_RAD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3223;"	d
I2C_RA_REG	.\Static_Code\IO_Map\MC56F82748.h	3126;"	d
I2C_S	.\Static_Code\IO_Map\MC56F82748.h	3281;"	d
I2C_SLTH	.\Static_Code\IO_Map\MC56F82748.h	3288;"	d
I2C_SLTH_REG	.\Static_Code\IO_Map\MC56F82748.h	3129;"	d
I2C_SLTH_SSLT	.\Static_Code\IO_Map\MC56F82748.h	3249;"	d
I2C_SLTH_SSLT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3247;"	d
I2C_SLTH_SSLT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3248;"	d
I2C_SLTL	.\Static_Code\IO_Map\MC56F82748.h	3289;"	d
I2C_SLTL_REG	.\Static_Code\IO_Map\MC56F82748.h	3130;"	d
I2C_SLTL_SSLT	.\Static_Code\IO_Map\MC56F82748.h	3253;"	d
I2C_SLTL_SSLT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3251;"	d
I2C_SLTL_SSLT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3252;"	d
I2C_SMB	.\Static_Code\IO_Map\MC56F82748.h	3286;"	d
I2C_SMB_ALERTEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3238;"	d
I2C_SMB_ALERTEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3239;"	d
I2C_SMB_FACK_MASK	.\Static_Code\IO_Map\MC56F82748.h	3240;"	d
I2C_SMB_FACK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3241;"	d
I2C_SMB_REG	.\Static_Code\IO_Map\MC56F82748.h	3127;"	d
I2C_SMB_SHTF1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3230;"	d
I2C_SMB_SHTF1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3231;"	d
I2C_SMB_SHTF2IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3226;"	d
I2C_SMB_SHTF2IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3227;"	d
I2C_SMB_SHTF2_MASK	.\Static_Code\IO_Map\MC56F82748.h	3228;"	d
I2C_SMB_SHTF2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3229;"	d
I2C_SMB_SIICAEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3236;"	d
I2C_SMB_SIICAEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3237;"	d
I2C_SMB_SLTF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3232;"	d
I2C_SMB_SLTF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3233;"	d
I2C_SMB_TCKSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	3234;"	d
I2C_SMB_TCKSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3235;"	d
I2C_S_ARBL_MASK	.\Static_Code\IO_Map\MC56F82748.h	3183;"	d
I2C_S_ARBL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3184;"	d
I2C_S_BUSY_MASK	.\Static_Code\IO_Map\MC56F82748.h	3185;"	d
I2C_S_BUSY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3186;"	d
I2C_S_IAAS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3187;"	d
I2C_S_IAAS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3188;"	d
I2C_S_IICIF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3177;"	d
I2C_S_IICIF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3178;"	d
I2C_S_RAM_MASK	.\Static_Code\IO_Map\MC56F82748.h	3181;"	d
I2C_S_RAM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3182;"	d
I2C_S_REG	.\Static_Code\IO_Map\MC56F82748.h	3122;"	d
I2C_S_RXAK_MASK	.\Static_Code\IO_Map\MC56F82748.h	3175;"	d
I2C_S_RXAK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3176;"	d
I2C_S_SRW_MASK	.\Static_Code\IO_Map\MC56F82748.h	3179;"	d
I2C_S_SRW_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3180;"	d
I2C_S_TCF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3189;"	d
I2C_S_TCF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3190;"	d
IAR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IAR;                                    \/**< GPIO Interrupt Assert Register, offset: 0x4 *\/$/;"	m	struct:GPIO_MemMap
IDAC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IDAC;                                   \/**< MSCAN Identifier Acceptance Control Register, offset: 0xB *\/$/;"	m	struct:CAN_MemMap
IDAR_BANK_1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IDAR_BANK_1[4];                         \/**< MSCAN Identifier Acceptance Registers (First Bank), array offset: 0x10, array step: 0x1 *\/$/;"	m	struct:CAN_MemMap
IDAR_BANK_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IDAR_BANK_2[4];                         \/**< MSCAN Identifier Acceptance Registers (Second Bank), array offset: 0x18, array step: 0x1 *\/$/;"	m	struct:CAN_MemMap
IDMR_BANK_1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IDMR_BANK_1[4];                         \/**< MSCAN Identifier Mask Registers (First Bank), array offset: 0x14, array step: 0x1 *\/$/;"	m	struct:CAN_MemMap
IDMR_BANK_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IDMR_BANK_2[4];                         \/**< MSCAN Identifier Mask Registers (Second Bank), array offset: 0x1C, array step: 0x1 *\/$/;"	m	struct:CAN_MemMap
IENR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IENR;                                   \/**< GPIO Interrupt Enable Register, offset: 0x5 *\/$/;"	m	struct:GPIO_MemMap
IESR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IESR;                                   \/**< GPIO Interrupt Edge Sensitive Register, offset: 0x8 *\/$/;"	m	struct:GPIO_MemMap
INIT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t INIT;                                   \/**< Initial Count Register, array offset: 0x1, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
INTC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	3674;"	d
INTC_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	3676;"	d
INTC_CTRL	.\Static_Code\IO_Map\MC56F82748.h	3716;"	d
INTC_CTRL_INT_DIS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3656;"	d
INTC_CTRL_INT_DIS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3657;"	d
INTC_CTRL_INT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3664;"	d
INTC_CTRL_INT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3665;"	d
INTC_CTRL_IPIC	.\Static_Code\IO_Map\MC56F82748.h	3663;"	d
INTC_CTRL_IPIC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3661;"	d
INTC_CTRL_IPIC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3662;"	d
INTC_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	3379;"	d
INTC_CTRL_VAB	.\Static_Code\IO_Map\MC56F82748.h	3660;"	d
INTC_CTRL_VAB_MASK	.\Static_Code\IO_Map\MC56F82748.h	3658;"	d
INTC_CTRL_VAB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3659;"	d
INTC_FIM0	.\Static_Code\IO_Map\MC56F82748.h	3703;"	d
INTC_FIM0_FAST_INTERRUPT_0	.\Static_Code\IO_Map\MC56F82748.h	3606;"	d
INTC_FIM0_FAST_INTERRUPT_0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3604;"	d
INTC_FIM0_FAST_INTERRUPT_0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3605;"	d
INTC_FIM0_REG	.\Static_Code\IO_Map\MC56F82748.h	3366;"	d
INTC_FIM1	.\Static_Code\IO_Map\MC56F82748.h	3706;"	d
INTC_FIM1_FAST_INTERRUPT_1	.\Static_Code\IO_Map\MC56F82748.h	3618;"	d
INTC_FIM1_FAST_INTERRUPT_1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3616;"	d
INTC_FIM1_FAST_INTERRUPT_1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3617;"	d
INTC_FIM1_REG	.\Static_Code\IO_Map\MC56F82748.h	3369;"	d
INTC_FIVAH0	.\Static_Code\IO_Map\MC56F82748.h	3705;"	d
INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH	.\Static_Code\IO_Map\MC56F82748.h	3614;"	d
INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH_MASK	.\Static_Code\IO_Map\MC56F82748.h	3612;"	d
INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3613;"	d
INTC_FIVAH0_REG	.\Static_Code\IO_Map\MC56F82748.h	3368;"	d
INTC_FIVAH1	.\Static_Code\IO_Map\MC56F82748.h	3708;"	d
INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH	.\Static_Code\IO_Map\MC56F82748.h	3626;"	d
INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH_MASK	.\Static_Code\IO_Map\MC56F82748.h	3624;"	d
INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3625;"	d
INTC_FIVAH1_REG	.\Static_Code\IO_Map\MC56F82748.h	3371;"	d
INTC_FIVAL0	.\Static_Code\IO_Map\MC56F82748.h	3704;"	d
INTC_FIVAL0_FI_0_VECTOR_ADDRESS_LOW	.\Static_Code\IO_Map\MC56F82748.h	3610;"	d
INTC_FIVAL0_FI_0_VECTOR_ADDRESS_LOW_MASK	.\Static_Code\IO_Map\MC56F82748.h	3608;"	d
INTC_FIVAL0_FI_0_VECTOR_ADDRESS_LOW_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3609;"	d
INTC_FIVAL0_REG	.\Static_Code\IO_Map\MC56F82748.h	3367;"	d
INTC_FIVAL1	.\Static_Code\IO_Map\MC56F82748.h	3707;"	d
INTC_FIVAL1_FI_1_VECTOR_ADDRESS_LOW	.\Static_Code\IO_Map\MC56F82748.h	3622;"	d
INTC_FIVAL1_FI_1_VECTOR_ADDRESS_LOW_MASK	.\Static_Code\IO_Map\MC56F82748.h	3620;"	d
INTC_FIVAL1_FI_1_VECTOR_ADDRESS_LOW_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3621;"	d
INTC_FIVAL1_REG	.\Static_Code\IO_Map\MC56F82748.h	3370;"	d
INTC_IPR0	.\Static_Code\IO_Map\MC56F82748.h	3690;"	d
INTC_IPR0_BKPT	.\Static_Code\IO_Map\MC56F82748.h	3401;"	d
INTC_IPR0_BKPT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3399;"	d
INTC_IPR0_BKPT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3400;"	d
INTC_IPR0_BUS_ERR	.\Static_Code\IO_Map\MC56F82748.h	3413;"	d
INTC_IPR0_BUS_ERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3411;"	d
INTC_IPR0_BUS_ERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3412;"	d
INTC_IPR0_REG	.\Static_Code\IO_Map\MC56F82748.h	3353;"	d
INTC_IPR0_RX_REG	.\Static_Code\IO_Map\MC56F82748.h	3410;"	d
INTC_IPR0_RX_REG_MASK	.\Static_Code\IO_Map\MC56F82748.h	3408;"	d
INTC_IPR0_RX_REG_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3409;"	d
INTC_IPR0_STPCNT	.\Static_Code\IO_Map\MC56F82748.h	3398;"	d
INTC_IPR0_STPCNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3396;"	d
INTC_IPR0_STPCNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3397;"	d
INTC_IPR0_TRBUF	.\Static_Code\IO_Map\MC56F82748.h	3404;"	d
INTC_IPR0_TRBUF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3402;"	d
INTC_IPR0_TRBUF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3403;"	d
INTC_IPR0_TX_REG	.\Static_Code\IO_Map\MC56F82748.h	3407;"	d
INTC_IPR0_TX_REG_MASK	.\Static_Code\IO_Map\MC56F82748.h	3405;"	d
INTC_IPR0_TX_REG_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3406;"	d
INTC_IPR1	.\Static_Code\IO_Map\MC56F82748.h	3691;"	d
INTC_IPR10	.\Static_Code\IO_Map\MC56F82748.h	3699;"	d
INTC_IPR10_CMPA	.\Static_Code\IO_Map\MC56F82748.h	3566;"	d
INTC_IPR10_CMPA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3564;"	d
INTC_IPR10_CMPA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3565;"	d
INTC_IPR10_CMPB	.\Static_Code\IO_Map\MC56F82748.h	3563;"	d
INTC_IPR10_CMPB_MASK	.\Static_Code\IO_Map\MC56F82748.h	3561;"	d
INTC_IPR10_CMPB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3562;"	d
INTC_IPR10_CMPC	.\Static_Code\IO_Map\MC56F82748.h	3560;"	d
INTC_IPR10_CMPC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3558;"	d
INTC_IPR10_CMPC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3559;"	d
INTC_IPR10_CMPD	.\Static_Code\IO_Map\MC56F82748.h	3557;"	d
INTC_IPR10_CMPD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3555;"	d
INTC_IPR10_CMPD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3556;"	d
INTC_IPR10_FTFA_CC	.\Static_Code\IO_Map\MC56F82748.h	3554;"	d
INTC_IPR10_FTFA_CC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3552;"	d
INTC_IPR10_FTFA_CC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3553;"	d
INTC_IPR10_PIT0_ROLLOVR	.\Static_Code\IO_Map\MC56F82748.h	3572;"	d
INTC_IPR10_PIT0_ROLLOVR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3570;"	d
INTC_IPR10_PIT0_ROLLOVR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3571;"	d
INTC_IPR10_PIT1_ROLLOVR	.\Static_Code\IO_Map\MC56F82748.h	3569;"	d
INTC_IPR10_PIT1_ROLLOVR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3567;"	d
INTC_IPR10_PIT1_ROLLOVR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3568;"	d
INTC_IPR10_REG	.\Static_Code\IO_Map\MC56F82748.h	3362;"	d
INTC_IPR11	.\Static_Code\IO_Map\MC56F82748.h	3700;"	d
INTC_IPR11_GPIOD	.\Static_Code\IO_Map\MC56F82748.h	3582;"	d
INTC_IPR11_GPIOD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3580;"	d
INTC_IPR11_GPIOD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3581;"	d
INTC_IPR11_GPIOE	.\Static_Code\IO_Map\MC56F82748.h	3579;"	d
INTC_IPR11_GPIOE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3577;"	d
INTC_IPR11_GPIOE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3578;"	d
INTC_IPR11_GPIOF	.\Static_Code\IO_Map\MC56F82748.h	3576;"	d
INTC_IPR11_GPIOF_MASK	.\Static_Code\IO_Map\MC56F82748.h	3574;"	d
INTC_IPR11_GPIOF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3575;"	d
INTC_IPR11_REG	.\Static_Code\IO_Map\MC56F82748.h	3363;"	d
INTC_IPR12	.\Static_Code\IO_Map\MC56F82748.h	3701;"	d
INTC_IPR12_COP_INT	.\Static_Code\IO_Map\MC56F82748.h	3595;"	d
INTC_IPR12_COP_INT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3593;"	d
INTC_IPR12_COP_INT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3594;"	d
INTC_IPR12_EWM_INT	.\Static_Code\IO_Map\MC56F82748.h	3598;"	d
INTC_IPR12_EWM_INT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3596;"	d
INTC_IPR12_EWM_INT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3597;"	d
INTC_IPR12_GPIOA	.\Static_Code\IO_Map\MC56F82748.h	3592;"	d
INTC_IPR12_GPIOA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3590;"	d
INTC_IPR12_GPIOA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3591;"	d
INTC_IPR12_GPIOB	.\Static_Code\IO_Map\MC56F82748.h	3589;"	d
INTC_IPR12_GPIOB_MASK	.\Static_Code\IO_Map\MC56F82748.h	3587;"	d
INTC_IPR12_GPIOB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3588;"	d
INTC_IPR12_GPIOC	.\Static_Code\IO_Map\MC56F82748.h	3586;"	d
INTC_IPR12_GPIOC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3584;"	d
INTC_IPR12_GPIOC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3585;"	d
INTC_IPR12_REG	.\Static_Code\IO_Map\MC56F82748.h	3364;"	d
INTC_IPR1_LVI1	.\Static_Code\IO_Map\MC56F82748.h	3420;"	d
INTC_IPR1_LVI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3418;"	d
INTC_IPR1_LVI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3419;"	d
INTC_IPR1_OCCS	.\Static_Code\IO_Map\MC56F82748.h	3423;"	d
INTC_IPR1_OCCS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3421;"	d
INTC_IPR1_OCCS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3422;"	d
INTC_IPR1_REG	.\Static_Code\IO_Map\MC56F82748.h	3354;"	d
INTC_IPR1_XBARA	.\Static_Code\IO_Map\MC56F82748.h	3417;"	d
INTC_IPR1_XBARA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3415;"	d
INTC_IPR1_XBARA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3416;"	d
INTC_IPR2	.\Static_Code\IO_Map\MC56F82748.h	3692;"	d
INTC_IPR2_ADC_CC0	.\Static_Code\IO_Map\MC56F82748.h	3442;"	d
INTC_IPR2_ADC_CC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3440;"	d
INTC_IPR2_ADC_CC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3441;"	d
INTC_IPR2_ADC_CC1	.\Static_Code\IO_Map\MC56F82748.h	3439;"	d
INTC_IPR2_ADC_CC1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3437;"	d
INTC_IPR2_ADC_CC1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3438;"	d
INTC_IPR2_ADC_ERR	.\Static_Code\IO_Map\MC56F82748.h	3445;"	d
INTC_IPR2_ADC_ERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3443;"	d
INTC_IPR2_ADC_ERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3444;"	d
INTC_IPR2_REG	.\Static_Code\IO_Map\MC56F82748.h	3355;"	d
INTC_IPR2_TMRA_0	.\Static_Code\IO_Map\MC56F82748.h	3436;"	d
INTC_IPR2_TMRA_0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3434;"	d
INTC_IPR2_TMRA_0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3435;"	d
INTC_IPR2_TMRA_1	.\Static_Code\IO_Map\MC56F82748.h	3433;"	d
INTC_IPR2_TMRA_1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3431;"	d
INTC_IPR2_TMRA_1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3432;"	d
INTC_IPR2_TMRA_2	.\Static_Code\IO_Map\MC56F82748.h	3430;"	d
INTC_IPR2_TMRA_2_MASK	.\Static_Code\IO_Map\MC56F82748.h	3428;"	d
INTC_IPR2_TMRA_2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3429;"	d
INTC_IPR2_TMRA_3	.\Static_Code\IO_Map\MC56F82748.h	3427;"	d
INTC_IPR2_TMRA_3_MASK	.\Static_Code\IO_Map\MC56F82748.h	3425;"	d
INTC_IPR2_TMRA_3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3426;"	d
INTC_IPR3	.\Static_Code\IO_Map\MC56F82748.h	3693;"	d
INTC_IPR3_CAN_ERROR	.\Static_Code\IO_Map\MC56F82748.h	3461;"	d
INTC_IPR3_CAN_ERROR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3459;"	d
INTC_IPR3_CAN_ERROR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3460;"	d
INTC_IPR3_CAN_TX_WARN	.\Static_Code\IO_Map\MC56F82748.h	3464;"	d
INTC_IPR3_CAN_TX_WARN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3462;"	d
INTC_IPR3_CAN_TX_WARN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3463;"	d
INTC_IPR3_DMACH0	.\Static_Code\IO_Map\MC56F82748.h	3458;"	d
INTC_IPR3_DMACH0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3456;"	d
INTC_IPR3_DMACH0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3457;"	d
INTC_IPR3_DMACH1	.\Static_Code\IO_Map\MC56F82748.h	3455;"	d
INTC_IPR3_DMACH1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3453;"	d
INTC_IPR3_DMACH1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3454;"	d
INTC_IPR3_DMACH2	.\Static_Code\IO_Map\MC56F82748.h	3452;"	d
INTC_IPR3_DMACH2_MASK	.\Static_Code\IO_Map\MC56F82748.h	3450;"	d
INTC_IPR3_DMACH2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3451;"	d
INTC_IPR3_DMACH3	.\Static_Code\IO_Map\MC56F82748.h	3449;"	d
INTC_IPR3_DMACH3_MASK	.\Static_Code\IO_Map\MC56F82748.h	3447;"	d
INTC_IPR3_DMACH3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3448;"	d
INTC_IPR3_REG	.\Static_Code\IO_Map\MC56F82748.h	3356;"	d
INTC_IPR4	.\Static_Code\IO_Map\MC56F82748.h	3694;"	d
INTC_IPR4_CAN_RX_WARN	.\Static_Code\IO_Map\MC56F82748.h	3468;"	d
INTC_IPR4_CAN_RX_WARN_MASK	.\Static_Code\IO_Map\MC56F82748.h	3466;"	d
INTC_IPR4_CAN_RX_WARN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3467;"	d
INTC_IPR4_CAN_WAKEUP	.\Static_Code\IO_Map\MC56F82748.h	3471;"	d
INTC_IPR4_CAN_WAKEUP_MASK	.\Static_Code\IO_Map\MC56F82748.h	3469;"	d
INTC_IPR4_CAN_WAKEUP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3470;"	d
INTC_IPR4_QSCI1_RCV	.\Static_Code\IO_Map\MC56F82748.h	3477;"	d
INTC_IPR4_QSCI1_RCV_MASK	.\Static_Code\IO_Map\MC56F82748.h	3475;"	d
INTC_IPR4_QSCI1_RCV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3476;"	d
INTC_IPR4_QSCI1_RERR	.\Static_Code\IO_Map\MC56F82748.h	3474;"	d
INTC_IPR4_QSCI1_RERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3472;"	d
INTC_IPR4_QSCI1_RERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3473;"	d
INTC_IPR4_REG	.\Static_Code\IO_Map\MC56F82748.h	3357;"	d
INTC_IPR5	.\Static_Code\IO_Map\MC56F82748.h	3695;"	d
INTC_IPR5_QSCI0_RCV	.\Static_Code\IO_Map\MC56F82748.h	3490;"	d
INTC_IPR5_QSCI0_RCV_MASK	.\Static_Code\IO_Map\MC56F82748.h	3488;"	d
INTC_IPR5_QSCI0_RCV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3489;"	d
INTC_IPR5_QSCI0_RERR	.\Static_Code\IO_Map\MC56F82748.h	3487;"	d
INTC_IPR5_QSCI0_RERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3485;"	d
INTC_IPR5_QSCI0_RERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3486;"	d
INTC_IPR5_QSCI0_TDRE	.\Static_Code\IO_Map\MC56F82748.h	3496;"	d
INTC_IPR5_QSCI0_TDRE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3494;"	d
INTC_IPR5_QSCI0_TDRE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3495;"	d
INTC_IPR5_QSCI0_TIDLE	.\Static_Code\IO_Map\MC56F82748.h	3493;"	d
INTC_IPR5_QSCI0_TIDLE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3491;"	d
INTC_IPR5_QSCI0_TIDLE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3492;"	d
INTC_IPR5_QSCI1_TDRE	.\Static_Code\IO_Map\MC56F82748.h	3484;"	d
INTC_IPR5_QSCI1_TDRE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3482;"	d
INTC_IPR5_QSCI1_TDRE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3483;"	d
INTC_IPR5_QSCI1_TIDLE	.\Static_Code\IO_Map\MC56F82748.h	3481;"	d
INTC_IPR5_QSCI1_TIDLE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3479;"	d
INTC_IPR5_QSCI1_TIDLE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3480;"	d
INTC_IPR5_REG	.\Static_Code\IO_Map\MC56F82748.h	3358;"	d
INTC_IPR6	.\Static_Code\IO_Map\MC56F82748.h	3696;"	d
INTC_IPR6_IIC0	.\Static_Code\IO_Map\MC56F82748.h	3512;"	d
INTC_IPR6_IIC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3510;"	d
INTC_IPR6_IIC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3511;"	d
INTC_IPR6_QSPI0_RCV	.\Static_Code\IO_Map\MC56F82748.h	3509;"	d
INTC_IPR6_QSPI0_RCV_MASK	.\Static_Code\IO_Map\MC56F82748.h	3507;"	d
INTC_IPR6_QSPI0_RCV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3508;"	d
INTC_IPR6_QSPI0_XMIT	.\Static_Code\IO_Map\MC56F82748.h	3506;"	d
INTC_IPR6_QSPI0_XMIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3504;"	d
INTC_IPR6_QSPI0_XMIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3505;"	d
INTC_IPR6_QSPI1_RCV	.\Static_Code\IO_Map\MC56F82748.h	3503;"	d
INTC_IPR6_QSPI1_RCV_MASK	.\Static_Code\IO_Map\MC56F82748.h	3501;"	d
INTC_IPR6_QSPI1_RCV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3502;"	d
INTC_IPR6_QSPI1_XMIT	.\Static_Code\IO_Map\MC56F82748.h	3500;"	d
INTC_IPR6_QSPI1_XMIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3498;"	d
INTC_IPR6_QSPI1_XMIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3499;"	d
INTC_IPR6_REG	.\Static_Code\IO_Map\MC56F82748.h	3359;"	d
INTC_IPR8	.\Static_Code\IO_Map\MC56F82748.h	3697;"	d
INTC_IPR8_PWMA_CAP	.\Static_Code\IO_Map\MC56F82748.h	3525;"	d
INTC_IPR8_PWMA_CAP_MASK	.\Static_Code\IO_Map\MC56F82748.h	3523;"	d
INTC_IPR8_PWMA_CAP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3524;"	d
INTC_IPR8_PWMA_FAULT	.\Static_Code\IO_Map\MC56F82748.h	3516;"	d
INTC_IPR8_PWMA_FAULT_MASK	.\Static_Code\IO_Map\MC56F82748.h	3514;"	d
INTC_IPR8_PWMA_FAULT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3515;"	d
INTC_IPR8_PWMA_RELOAD3	.\Static_Code\IO_Map\MC56F82748.h	3522;"	d
INTC_IPR8_PWMA_RELOAD3_MASK	.\Static_Code\IO_Map\MC56F82748.h	3520;"	d
INTC_IPR8_PWMA_RELOAD3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3521;"	d
INTC_IPR8_PWMA_RERR	.\Static_Code\IO_Map\MC56F82748.h	3519;"	d
INTC_IPR8_PWMA_RERR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3517;"	d
INTC_IPR8_PWMA_RERR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3518;"	d
INTC_IPR8_REG	.\Static_Code\IO_Map\MC56F82748.h	3360;"	d
INTC_IPR9	.\Static_Code\IO_Map\MC56F82748.h	3698;"	d
INTC_IPR9_FTFA_RDCOL	.\Static_Code\IO_Map\MC56F82748.h	3550;"	d
INTC_IPR9_FTFA_RDCOL_MASK	.\Static_Code\IO_Map\MC56F82748.h	3548;"	d
INTC_IPR9_FTFA_RDCOL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3549;"	d
INTC_IPR9_PWMA_CMP0	.\Static_Code\IO_Map\MC56F82748.h	3547;"	d
INTC_IPR9_PWMA_CMP0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3545;"	d
INTC_IPR9_PWMA_CMP0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3546;"	d
INTC_IPR9_PWMA_CMP1	.\Static_Code\IO_Map\MC56F82748.h	3541;"	d
INTC_IPR9_PWMA_CMP1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3539;"	d
INTC_IPR9_PWMA_CMP1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3540;"	d
INTC_IPR9_PWMA_CMP2	.\Static_Code\IO_Map\MC56F82748.h	3535;"	d
INTC_IPR9_PWMA_CMP2_MASK	.\Static_Code\IO_Map\MC56F82748.h	3533;"	d
INTC_IPR9_PWMA_CMP2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3534;"	d
INTC_IPR9_PWMA_CMP3	.\Static_Code\IO_Map\MC56F82748.h	3529;"	d
INTC_IPR9_PWMA_CMP3_MASK	.\Static_Code\IO_Map\MC56F82748.h	3527;"	d
INTC_IPR9_PWMA_CMP3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3528;"	d
INTC_IPR9_PWMA_RELOAD0	.\Static_Code\IO_Map\MC56F82748.h	3544;"	d
INTC_IPR9_PWMA_RELOAD0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3542;"	d
INTC_IPR9_PWMA_RELOAD0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3543;"	d
INTC_IPR9_PWMA_RELOAD1	.\Static_Code\IO_Map\MC56F82748.h	3538;"	d
INTC_IPR9_PWMA_RELOAD1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3536;"	d
INTC_IPR9_PWMA_RELOAD1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3537;"	d
INTC_IPR9_PWMA_RELOAD2	.\Static_Code\IO_Map\MC56F82748.h	3532;"	d
INTC_IPR9_PWMA_RELOAD2_MASK	.\Static_Code\IO_Map\MC56F82748.h	3530;"	d
INTC_IPR9_PWMA_RELOAD2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3531;"	d
INTC_IPR9_REG	.\Static_Code\IO_Map\MC56F82748.h	3361;"	d
INTC_IRQP0	.\Static_Code\IO_Map\MC56F82748.h	3709;"	d
INTC_IRQP0_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3630;"	d
INTC_IRQP0_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3628;"	d
INTC_IRQP0_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3629;"	d
INTC_IRQP0_REG	.\Static_Code\IO_Map\MC56F82748.h	3372;"	d
INTC_IRQP1	.\Static_Code\IO_Map\MC56F82748.h	3710;"	d
INTC_IRQP1_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3634;"	d
INTC_IRQP1_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3632;"	d
INTC_IRQP1_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3633;"	d
INTC_IRQP1_REG	.\Static_Code\IO_Map\MC56F82748.h	3373;"	d
INTC_IRQP2	.\Static_Code\IO_Map\MC56F82748.h	3711;"	d
INTC_IRQP2_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3638;"	d
INTC_IRQP2_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3636;"	d
INTC_IRQP2_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3637;"	d
INTC_IRQP2_REG	.\Static_Code\IO_Map\MC56F82748.h	3374;"	d
INTC_IRQP3	.\Static_Code\IO_Map\MC56F82748.h	3712;"	d
INTC_IRQP3_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3642;"	d
INTC_IRQP3_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3640;"	d
INTC_IRQP3_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3641;"	d
INTC_IRQP3_REG	.\Static_Code\IO_Map\MC56F82748.h	3375;"	d
INTC_IRQP4	.\Static_Code\IO_Map\MC56F82748.h	3713;"	d
INTC_IRQP4_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3646;"	d
INTC_IRQP4_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3644;"	d
INTC_IRQP4_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3645;"	d
INTC_IRQP4_REG	.\Static_Code\IO_Map\MC56F82748.h	3376;"	d
INTC_IRQP5	.\Static_Code\IO_Map\MC56F82748.h	3714;"	d
INTC_IRQP5_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3650;"	d
INTC_IRQP5_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3648;"	d
INTC_IRQP5_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3649;"	d
INTC_IRQP5_REG	.\Static_Code\IO_Map\MC56F82748.h	3377;"	d
INTC_IRQP6	.\Static_Code\IO_Map\MC56F82748.h	3715;"	d
INTC_IRQP6_PENDING	.\Static_Code\IO_Map\MC56F82748.h	3654;"	d
INTC_IRQP6_PENDING_MASK	.\Static_Code\IO_Map\MC56F82748.h	3652;"	d
INTC_IRQP6_PENDING_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3653;"	d
INTC_IRQP6_REG	.\Static_Code\IO_Map\MC56F82748.h	3378;"	d
INTC_Init	.\Static_Code\Peripherals\INTC_Init.c	/^void INTC_Init(void) {$/;"	f
INTC_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct INTC_MemMap {$/;"	s
INTC_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *INTC_MemMapPtr;$/;"	t
INTC_PDD_EnableInterrupts	.\Static_Code\PDD\INTC_PDD.h	5031;"	d
INTC_PDD_GetFastInterruptAddress0	.\Static_Code\PDD\INTC_PDD.h	2714;"	d
INTC_PDD_GetFastInterruptAddress0High	.\Static_Code\PDD\INTC_PDD.h	2801;"	d
INTC_PDD_GetFastInterruptAddress0Low	.\Static_Code\PDD\INTC_PDD.h	2759;"	d
INTC_PDD_GetFastInterruptAddress1	.\Static_Code\PDD\INTC_PDD.h	2894;"	d
INTC_PDD_GetFastInterruptAddress1High	.\Static_Code\PDD\INTC_PDD.h	2981;"	d
INTC_PDD_GetFastInterruptAddress1Low	.\Static_Code\PDD\INTC_PDD.h	2939;"	d
INTC_PDD_GetFastInterruptNumber0	.\Static_Code\PDD\INTC_PDD.h	2666;"	d
INTC_PDD_GetFastInterruptNumber1	.\Static_Code\PDD\INTC_PDD.h	2846;"	d
INTC_PDD_GetInterruptSentToCoreFlag	.\Static_Code\PDD\INTC_PDD.h	4964;"	d
INTC_PDD_GetInterruptsEnabled	.\Static_Code\PDD\INTC_PDD.h	5053;"	d
INTC_PDD_GetPendingIrq10	.\Static_Code\PDD\INTC_PDD.h	3146;"	d
INTC_PDD_GetPendingIrq100	.\Static_Code\PDD\INTC_PDD.h	4766;"	d
INTC_PDD_GetPendingIrq101	.\Static_Code\PDD\INTC_PDD.h	4784;"	d
INTC_PDD_GetPendingIrq102	.\Static_Code\PDD\INTC_PDD.h	4802;"	d
INTC_PDD_GetPendingIrq103	.\Static_Code\PDD\INTC_PDD.h	4820;"	d
INTC_PDD_GetPendingIrq104	.\Static_Code\PDD\INTC_PDD.h	4838;"	d
INTC_PDD_GetPendingIrq105	.\Static_Code\PDD\INTC_PDD.h	4856;"	d
INTC_PDD_GetPendingIrq106	.\Static_Code\PDD\INTC_PDD.h	4874;"	d
INTC_PDD_GetPendingIrq107	.\Static_Code\PDD\INTC_PDD.h	4892;"	d
INTC_PDD_GetPendingIrq108	.\Static_Code\PDD\INTC_PDD.h	4910;"	d
INTC_PDD_GetPendingIrq109	.\Static_Code\PDD\INTC_PDD.h	4928;"	d
INTC_PDD_GetPendingIrq11	.\Static_Code\PDD\INTC_PDD.h	3164;"	d
INTC_PDD_GetPendingIrq110	.\Static_Code\PDD\INTC_PDD.h	4946;"	d
INTC_PDD_GetPendingIrq12	.\Static_Code\PDD\INTC_PDD.h	3182;"	d
INTC_PDD_GetPendingIrq13	.\Static_Code\PDD\INTC_PDD.h	3200;"	d
INTC_PDD_GetPendingIrq14	.\Static_Code\PDD\INTC_PDD.h	3218;"	d
INTC_PDD_GetPendingIrq15	.\Static_Code\PDD\INTC_PDD.h	3236;"	d
INTC_PDD_GetPendingIrq16	.\Static_Code\PDD\INTC_PDD.h	3254;"	d
INTC_PDD_GetPendingIrq17	.\Static_Code\PDD\INTC_PDD.h	3272;"	d
INTC_PDD_GetPendingIrq18	.\Static_Code\PDD\INTC_PDD.h	3290;"	d
INTC_PDD_GetPendingIrq19	.\Static_Code\PDD\INTC_PDD.h	3308;"	d
INTC_PDD_GetPendingIrq2	.\Static_Code\PDD\INTC_PDD.h	3002;"	d
INTC_PDD_GetPendingIrq20	.\Static_Code\PDD\INTC_PDD.h	3326;"	d
INTC_PDD_GetPendingIrq21	.\Static_Code\PDD\INTC_PDD.h	3344;"	d
INTC_PDD_GetPendingIrq22	.\Static_Code\PDD\INTC_PDD.h	3362;"	d
INTC_PDD_GetPendingIrq23	.\Static_Code\PDD\INTC_PDD.h	3380;"	d
INTC_PDD_GetPendingIrq24	.\Static_Code\PDD\INTC_PDD.h	3398;"	d
INTC_PDD_GetPendingIrq25	.\Static_Code\PDD\INTC_PDD.h	3416;"	d
INTC_PDD_GetPendingIrq26	.\Static_Code\PDD\INTC_PDD.h	3434;"	d
INTC_PDD_GetPendingIrq27	.\Static_Code\PDD\INTC_PDD.h	3452;"	d
INTC_PDD_GetPendingIrq28	.\Static_Code\PDD\INTC_PDD.h	3470;"	d
INTC_PDD_GetPendingIrq29	.\Static_Code\PDD\INTC_PDD.h	3488;"	d
INTC_PDD_GetPendingIrq3	.\Static_Code\PDD\INTC_PDD.h	3020;"	d
INTC_PDD_GetPendingIrq30	.\Static_Code\PDD\INTC_PDD.h	3506;"	d
INTC_PDD_GetPendingIrq31	.\Static_Code\PDD\INTC_PDD.h	3524;"	d
INTC_PDD_GetPendingIrq32	.\Static_Code\PDD\INTC_PDD.h	3542;"	d
INTC_PDD_GetPendingIrq33	.\Static_Code\PDD\INTC_PDD.h	3560;"	d
INTC_PDD_GetPendingIrq34	.\Static_Code\PDD\INTC_PDD.h	3578;"	d
INTC_PDD_GetPendingIrq35	.\Static_Code\PDD\INTC_PDD.h	3596;"	d
INTC_PDD_GetPendingIrq36	.\Static_Code\PDD\INTC_PDD.h	3614;"	d
INTC_PDD_GetPendingIrq37	.\Static_Code\PDD\INTC_PDD.h	3632;"	d
INTC_PDD_GetPendingIrq38	.\Static_Code\PDD\INTC_PDD.h	3650;"	d
INTC_PDD_GetPendingIrq39	.\Static_Code\PDD\INTC_PDD.h	3668;"	d
INTC_PDD_GetPendingIrq4	.\Static_Code\PDD\INTC_PDD.h	3038;"	d
INTC_PDD_GetPendingIrq40	.\Static_Code\PDD\INTC_PDD.h	3686;"	d
INTC_PDD_GetPendingIrq41	.\Static_Code\PDD\INTC_PDD.h	3704;"	d
INTC_PDD_GetPendingIrq42	.\Static_Code\PDD\INTC_PDD.h	3722;"	d
INTC_PDD_GetPendingIrq43	.\Static_Code\PDD\INTC_PDD.h	3740;"	d
INTC_PDD_GetPendingIrq44	.\Static_Code\PDD\INTC_PDD.h	3758;"	d
INTC_PDD_GetPendingIrq45	.\Static_Code\PDD\INTC_PDD.h	3776;"	d
INTC_PDD_GetPendingIrq46	.\Static_Code\PDD\INTC_PDD.h	3794;"	d
INTC_PDD_GetPendingIrq47	.\Static_Code\PDD\INTC_PDD.h	3812;"	d
INTC_PDD_GetPendingIrq48	.\Static_Code\PDD\INTC_PDD.h	3830;"	d
INTC_PDD_GetPendingIrq49	.\Static_Code\PDD\INTC_PDD.h	3848;"	d
INTC_PDD_GetPendingIrq5	.\Static_Code\PDD\INTC_PDD.h	3056;"	d
INTC_PDD_GetPendingIrq50	.\Static_Code\PDD\INTC_PDD.h	3866;"	d
INTC_PDD_GetPendingIrq51	.\Static_Code\PDD\INTC_PDD.h	3884;"	d
INTC_PDD_GetPendingIrq52	.\Static_Code\PDD\INTC_PDD.h	3902;"	d
INTC_PDD_GetPendingIrq53	.\Static_Code\PDD\INTC_PDD.h	3920;"	d
INTC_PDD_GetPendingIrq54	.\Static_Code\PDD\INTC_PDD.h	3938;"	d
INTC_PDD_GetPendingIrq55	.\Static_Code\PDD\INTC_PDD.h	3956;"	d
INTC_PDD_GetPendingIrq56	.\Static_Code\PDD\INTC_PDD.h	3974;"	d
INTC_PDD_GetPendingIrq57	.\Static_Code\PDD\INTC_PDD.h	3992;"	d
INTC_PDD_GetPendingIrq58	.\Static_Code\PDD\INTC_PDD.h	4010;"	d
INTC_PDD_GetPendingIrq59	.\Static_Code\PDD\INTC_PDD.h	4028;"	d
INTC_PDD_GetPendingIrq6	.\Static_Code\PDD\INTC_PDD.h	3074;"	d
INTC_PDD_GetPendingIrq60	.\Static_Code\PDD\INTC_PDD.h	4046;"	d
INTC_PDD_GetPendingIrq61	.\Static_Code\PDD\INTC_PDD.h	4064;"	d
INTC_PDD_GetPendingIrq62	.\Static_Code\PDD\INTC_PDD.h	4082;"	d
INTC_PDD_GetPendingIrq63	.\Static_Code\PDD\INTC_PDD.h	4100;"	d
INTC_PDD_GetPendingIrq64	.\Static_Code\PDD\INTC_PDD.h	4118;"	d
INTC_PDD_GetPendingIrq65	.\Static_Code\PDD\INTC_PDD.h	4136;"	d
INTC_PDD_GetPendingIrq66	.\Static_Code\PDD\INTC_PDD.h	4154;"	d
INTC_PDD_GetPendingIrq67	.\Static_Code\PDD\INTC_PDD.h	4172;"	d
INTC_PDD_GetPendingIrq68	.\Static_Code\PDD\INTC_PDD.h	4190;"	d
INTC_PDD_GetPendingIrq69	.\Static_Code\PDD\INTC_PDD.h	4208;"	d
INTC_PDD_GetPendingIrq7	.\Static_Code\PDD\INTC_PDD.h	3092;"	d
INTC_PDD_GetPendingIrq70	.\Static_Code\PDD\INTC_PDD.h	4226;"	d
INTC_PDD_GetPendingIrq71	.\Static_Code\PDD\INTC_PDD.h	4244;"	d
INTC_PDD_GetPendingIrq72	.\Static_Code\PDD\INTC_PDD.h	4262;"	d
INTC_PDD_GetPendingIrq73	.\Static_Code\PDD\INTC_PDD.h	4280;"	d
INTC_PDD_GetPendingIrq74	.\Static_Code\PDD\INTC_PDD.h	4298;"	d
INTC_PDD_GetPendingIrq75	.\Static_Code\PDD\INTC_PDD.h	4316;"	d
INTC_PDD_GetPendingIrq76	.\Static_Code\PDD\INTC_PDD.h	4334;"	d
INTC_PDD_GetPendingIrq77	.\Static_Code\PDD\INTC_PDD.h	4352;"	d
INTC_PDD_GetPendingIrq78	.\Static_Code\PDD\INTC_PDD.h	4370;"	d
INTC_PDD_GetPendingIrq79	.\Static_Code\PDD\INTC_PDD.h	4388;"	d
INTC_PDD_GetPendingIrq8	.\Static_Code\PDD\INTC_PDD.h	3110;"	d
INTC_PDD_GetPendingIrq80	.\Static_Code\PDD\INTC_PDD.h	4406;"	d
INTC_PDD_GetPendingIrq81	.\Static_Code\PDD\INTC_PDD.h	4424;"	d
INTC_PDD_GetPendingIrq82	.\Static_Code\PDD\INTC_PDD.h	4442;"	d
INTC_PDD_GetPendingIrq83	.\Static_Code\PDD\INTC_PDD.h	4460;"	d
INTC_PDD_GetPendingIrq84	.\Static_Code\PDD\INTC_PDD.h	4478;"	d
INTC_PDD_GetPendingIrq85	.\Static_Code\PDD\INTC_PDD.h	4496;"	d
INTC_PDD_GetPendingIrq86	.\Static_Code\PDD\INTC_PDD.h	4514;"	d
INTC_PDD_GetPendingIrq87	.\Static_Code\PDD\INTC_PDD.h	4532;"	d
INTC_PDD_GetPendingIrq88	.\Static_Code\PDD\INTC_PDD.h	4550;"	d
INTC_PDD_GetPendingIrq89	.\Static_Code\PDD\INTC_PDD.h	4568;"	d
INTC_PDD_GetPendingIrq9	.\Static_Code\PDD\INTC_PDD.h	3128;"	d
INTC_PDD_GetPendingIrq90	.\Static_Code\PDD\INTC_PDD.h	4586;"	d
INTC_PDD_GetPendingIrq91	.\Static_Code\PDD\INTC_PDD.h	4604;"	d
INTC_PDD_GetPendingIrq92	.\Static_Code\PDD\INTC_PDD.h	4622;"	d
INTC_PDD_GetPendingIrq93	.\Static_Code\PDD\INTC_PDD.h	4640;"	d
INTC_PDD_GetPendingIrq94	.\Static_Code\PDD\INTC_PDD.h	4658;"	d
INTC_PDD_GetPendingIrq95	.\Static_Code\PDD\INTC_PDD.h	4676;"	d
INTC_PDD_GetPendingIrq96	.\Static_Code\PDD\INTC_PDD.h	4694;"	d
INTC_PDD_GetPendingIrq97	.\Static_Code\PDD\INTC_PDD.h	4712;"	d
INTC_PDD_GetPendingIrq98	.\Static_Code\PDD\INTC_PDD.h	4730;"	d
INTC_PDD_GetPendingIrq99	.\Static_Code\PDD\INTC_PDD.h	4748;"	d
INTC_PDD_GetPrioritySentToCore	.\Static_Code\PDD\INTC_PDD.h	4986;"	d
INTC_PDD_GetPriorityVector10	.\Static_Code\PDD\INTC_PDD.h	2384;"	d
INTC_PDD_GetPriorityVector102	.\Static_Code\PDD\INTC_PDD.h	417;"	d
INTC_PDD_GetPriorityVector103	.\Static_Code\PDD\INTC_PDD.h	369;"	d
INTC_PDD_GetPriorityVector104	.\Static_Code\PDD\INTC_PDD.h	321;"	d
INTC_PDD_GetPriorityVector105	.\Static_Code\PDD\INTC_PDD.h	275;"	d
INTC_PDD_GetPriorityVector106	.\Static_Code\PDD\INTC_PDD.h	227;"	d
INTC_PDD_GetPriorityVector107	.\Static_Code\PDD\INTC_PDD.h	179;"	d
INTC_PDD_GetPriorityVector108	.\Static_Code\PDD\INTC_PDD.h	131;"	d
INTC_PDD_GetPriorityVector109	.\Static_Code\PDD\INTC_PDD.h	83;"	d
INTC_PDD_GetPriorityVector11	.\Static_Code\PDD\INTC_PDD.h	2334;"	d
INTC_PDD_GetPriorityVector18	.\Static_Code\PDD\INTC_PDD.h	2286;"	d
INTC_PDD_GetPriorityVector19	.\Static_Code\PDD\INTC_PDD.h	2238;"	d
INTC_PDD_GetPriorityVector20	.\Static_Code\PDD\INTC_PDD.h	2190;"	d
INTC_PDD_GetPriorityVector25	.\Static_Code\PDD\INTC_PDD.h	2142;"	d
INTC_PDD_GetPriorityVector26	.\Static_Code\PDD\INTC_PDD.h	2091;"	d
INTC_PDD_GetPriorityVector27	.\Static_Code\PDD\INTC_PDD.h	2040;"	d
INTC_PDD_GetPriorityVector28	.\Static_Code\PDD\INTC_PDD.h	1989;"	d
INTC_PDD_GetPriorityVector29	.\Static_Code\PDD\INTC_PDD.h	1938;"	d
INTC_PDD_GetPriorityVector30	.\Static_Code\PDD\INTC_PDD.h	1888;"	d
INTC_PDD_GetPriorityVector31	.\Static_Code\PDD\INTC_PDD.h	1838;"	d
INTC_PDD_GetPriorityVector33	.\Static_Code\PDD\INTC_PDD.h	1790;"	d
INTC_PDD_GetPriorityVector34	.\Static_Code\PDD\INTC_PDD.h	1741;"	d
INTC_PDD_GetPriorityVector35	.\Static_Code\PDD\INTC_PDD.h	1692;"	d
INTC_PDD_GetPriorityVector36	.\Static_Code\PDD\INTC_PDD.h	1643;"	d
INTC_PDD_GetPriorityVector39	.\Static_Code\PDD\INTC_PDD.h	6387;"	d
INTC_PDD_GetPriorityVector40	.\Static_Code\PDD\INTC_PDD.h	6339;"	d
INTC_PDD_GetPriorityVector41	.\Static_Code\PDD\INTC_PDD.h	6292;"	d
INTC_PDD_GetPriorityVector42	.\Static_Code\PDD\INTC_PDD.h	6243;"	d
INTC_PDD_GetPriorityVector47	.\Static_Code\PDD\INTC_PDD.h	6195;"	d
INTC_PDD_GetPriorityVector48	.\Static_Code\PDD\INTC_PDD.h	6146;"	d
INTC_PDD_GetPriorityVector49	.\Static_Code\PDD\INTC_PDD.h	6098;"	d
INTC_PDD_GetPriorityVector5	.\Static_Code\PDD\INTC_PDD.h	2579;"	d
INTC_PDD_GetPriorityVector50	.\Static_Code\PDD\INTC_PDD.h	6049;"	d
INTC_PDD_GetPriorityVector51	.\Static_Code\PDD\INTC_PDD.h	1594;"	d
INTC_PDD_GetPriorityVector52	.\Static_Code\PDD\INTC_PDD.h	1545;"	d
INTC_PDD_GetPriorityVector53	.\Static_Code\PDD\INTC_PDD.h	1495;"	d
INTC_PDD_GetPriorityVector54	.\Static_Code\PDD\INTC_PDD.h	1446;"	d
INTC_PDD_GetPriorityVector57	.\Static_Code\PDD\INTC_PDD.h	6534;"	d
INTC_PDD_GetPriorityVector58	.\Static_Code\PDD\INTC_PDD.h	6485;"	d
INTC_PDD_GetPriorityVector59	.\Static_Code\PDD\INTC_PDD.h	1396;"	d
INTC_PDD_GetPriorityVector6	.\Static_Code\PDD\INTC_PDD.h	2531;"	d
INTC_PDD_GetPriorityVector60	.\Static_Code\PDD\INTC_PDD.h	1347;"	d
INTC_PDD_GetPriorityVector62	.\Static_Code\PDD\INTC_PDD.h	1299;"	d
INTC_PDD_GetPriorityVector77	.\Static_Code\PDD\INTC_PDD.h	1245;"	d
INTC_PDD_GetPriorityVector78	.\Static_Code\PDD\INTC_PDD.h	1196;"	d
INTC_PDD_GetPriorityVector79	.\Static_Code\PDD\INTC_PDD.h	1148;"	d
INTC_PDD_GetPriorityVector8	.\Static_Code\PDD\INTC_PDD.h	2482;"	d
INTC_PDD_GetPriorityVector80	.\Static_Code\PDD\INTC_PDD.h	1099;"	d
INTC_PDD_GetPriorityVector81	.\Static_Code\PDD\INTC_PDD.h	1051;"	d
INTC_PDD_GetPriorityVector82	.\Static_Code\PDD\INTC_PDD.h	1002;"	d
INTC_PDD_GetPriorityVector83	.\Static_Code\PDD\INTC_PDD.h	953;"	d
INTC_PDD_GetPriorityVector84	.\Static_Code\PDD\INTC_PDD.h	904;"	d
INTC_PDD_GetPriorityVector85	.\Static_Code\PDD\INTC_PDD.h	855;"	d
INTC_PDD_GetPriorityVector86	.\Static_Code\PDD\INTC_PDD.h	806;"	d
INTC_PDD_GetPriorityVector87	.\Static_Code\PDD\INTC_PDD.h	757;"	d
INTC_PDD_GetPriorityVector88	.\Static_Code\PDD\INTC_PDD.h	708;"	d
INTC_PDD_GetPriorityVector89	.\Static_Code\PDD\INTC_PDD.h	662;"	d
INTC_PDD_GetPriorityVector9	.\Static_Code\PDD\INTC_PDD.h	2434;"	d
INTC_PDD_GetPriorityVector90	.\Static_Code\PDD\INTC_PDD.h	6437;"	d
INTC_PDD_GetPriorityVector91	.\Static_Code\PDD\INTC_PDD.h	5999;"	d
INTC_PDD_GetPriorityVector92	.\Static_Code\PDD\INTC_PDD.h	613;"	d
INTC_PDD_GetPriorityVector93	.\Static_Code\PDD\INTC_PDD.h	563;"	d
INTC_PDD_GetPriorityVector94	.\Static_Code\PDD\INTC_PDD.h	513;"	d
INTC_PDD_GetPriorityVector95	.\Static_Code\PDD\INTC_PDD.h	465;"	d
INTC_PDD_GetVectorAddressBus	.\Static_Code\PDD\INTC_PDD.h	5007;"	d
INTC_PDD_GetVectorBaseAddress	.\Static_Code\PDD\INTC_PDD.h	2621;"	d
INTC_PDD_H_	.\Static_Code\PDD\INTC_PDD.h	9;"	d
INTC_PDD_ReadControlReg	.\Static_Code\PDD\INTC_PDD.h	5951;"	d
INTC_PDD_ReadFastInterrupt0MatchReg	.\Static_Code\PDD\INTC_PDD.h	5589;"	d
INTC_PDD_ReadFastInterrupt0VectorAddressHighReg	.\Static_Code\PDD\INTC_PDD.h	5669;"	d
INTC_PDD_ReadFastInterrupt0VectorAddressLowReg	.\Static_Code\PDD\INTC_PDD.h	5629;"	d
INTC_PDD_ReadFastInterrupt1MatchReg	.\Static_Code\PDD\INTC_PDD.h	5707;"	d
INTC_PDD_ReadFastInterrupt1VectorAddressHighReg	.\Static_Code\PDD\INTC_PDD.h	5787;"	d
INTC_PDD_ReadFastInterrupt1VectorAddressLowReg	.\Static_Code\PDD\INTC_PDD.h	5747;"	d
INTC_PDD_ReadInterruptPriority0Reg	.\Static_Code\PDD\INTC_PDD.h	5095;"	d
INTC_PDD_ReadInterruptPriority10Reg	.\Static_Code\PDD\INTC_PDD.h	5437;"	d
INTC_PDD_ReadInterruptPriority11Reg	.\Static_Code\PDD\INTC_PDD.h	5475;"	d
INTC_PDD_ReadInterruptPriority12Reg	.\Static_Code\PDD\INTC_PDD.h	5513;"	d
INTC_PDD_ReadInterruptPriority1eg	.\Static_Code\PDD\INTC_PDD.h	5133;"	d
INTC_PDD_ReadInterruptPriority2Reg	.\Static_Code\PDD\INTC_PDD.h	5171;"	d
INTC_PDD_ReadInterruptPriority3Reg	.\Static_Code\PDD\INTC_PDD.h	5209;"	d
INTC_PDD_ReadInterruptPriority4Reg	.\Static_Code\PDD\INTC_PDD.h	5247;"	d
INTC_PDD_ReadInterruptPriority5Reg	.\Static_Code\PDD\INTC_PDD.h	5285;"	d
INTC_PDD_ReadInterruptPriority6Reg	.\Static_Code\PDD\INTC_PDD.h	5323;"	d
INTC_PDD_ReadInterruptPriority8Reg	.\Static_Code\PDD\INTC_PDD.h	5361;"	d
INTC_PDD_ReadInterruptPriority9Reg	.\Static_Code\PDD\INTC_PDD.h	5399;"	d
INTC_PDD_ReadIrqPending0Reg	.\Static_Code\PDD\INTC_PDD.h	5805;"	d
INTC_PDD_ReadIrqPending1Reg	.\Static_Code\PDD\INTC_PDD.h	5823;"	d
INTC_PDD_ReadIrqPending2Reg	.\Static_Code\PDD\INTC_PDD.h	5841;"	d
INTC_PDD_ReadIrqPending3Reg	.\Static_Code\PDD\INTC_PDD.h	5859;"	d
INTC_PDD_ReadIrqPending4Reg	.\Static_Code\PDD\INTC_PDD.h	5877;"	d
INTC_PDD_ReadIrqPending5Reg	.\Static_Code\PDD\INTC_PDD.h	5895;"	d
INTC_PDD_ReadIrqPending6Reg	.\Static_Code\PDD\INTC_PDD.h	5913;"	d
INTC_PDD_ReadVectorBaseAddressReg	.\Static_Code\PDD\INTC_PDD.h	5551;"	d
INTC_PDD_SetFastInterruptAddress0	.\Static_Code\PDD\INTC_PDD.h	2690;"	d
INTC_PDD_SetFastInterruptAddress0High	.\Static_Code\PDD\INTC_PDD.h	2779;"	d
INTC_PDD_SetFastInterruptAddress0Low	.\Static_Code\PDD\INTC_PDD.h	2741;"	d
INTC_PDD_SetFastInterruptAddress1	.\Static_Code\PDD\INTC_PDD.h	2870;"	d
INTC_PDD_SetFastInterruptAddress1High	.\Static_Code\PDD\INTC_PDD.h	2959;"	d
INTC_PDD_SetFastInterruptAddress1Low	.\Static_Code\PDD\INTC_PDD.h	2921;"	d
INTC_PDD_SetFastInterruptNumber0	.\Static_Code\PDD\INTC_PDD.h	2644;"	d
INTC_PDD_SetFastInterruptNumber1	.\Static_Code\PDD\INTC_PDD.h	2824;"	d
INTC_PDD_SetPriorityVector10	.\Static_Code\PDD\INTC_PDD.h	2359;"	d
INTC_PDD_SetPriorityVector102	.\Static_Code\PDD\INTC_PDD.h	393;"	d
INTC_PDD_SetPriorityVector103	.\Static_Code\PDD\INTC_PDD.h	345;"	d
INTC_PDD_SetPriorityVector104	.\Static_Code\PDD\INTC_PDD.h	297;"	d
INTC_PDD_SetPriorityVector105	.\Static_Code\PDD\INTC_PDD.h	251;"	d
INTC_PDD_SetPriorityVector106	.\Static_Code\PDD\INTC_PDD.h	203;"	d
INTC_PDD_SetPriorityVector107	.\Static_Code\PDD\INTC_PDD.h	155;"	d
INTC_PDD_SetPriorityVector108	.\Static_Code\PDD\INTC_PDD.h	107;"	d
INTC_PDD_SetPriorityVector109	.\Static_Code\PDD\INTC_PDD.h	59;"	d
INTC_PDD_SetPriorityVector11	.\Static_Code\PDD\INTC_PDD.h	2310;"	d
INTC_PDD_SetPriorityVector18	.\Static_Code\PDD\INTC_PDD.h	2262;"	d
INTC_PDD_SetPriorityVector19	.\Static_Code\PDD\INTC_PDD.h	2214;"	d
INTC_PDD_SetPriorityVector20	.\Static_Code\PDD\INTC_PDD.h	2165;"	d
INTC_PDD_SetPriorityVector25	.\Static_Code\PDD\INTC_PDD.h	2116;"	d
INTC_PDD_SetPriorityVector26	.\Static_Code\PDD\INTC_PDD.h	2065;"	d
INTC_PDD_SetPriorityVector27	.\Static_Code\PDD\INTC_PDD.h	2014;"	d
INTC_PDD_SetPriorityVector28	.\Static_Code\PDD\INTC_PDD.h	1963;"	d
INTC_PDD_SetPriorityVector29	.\Static_Code\PDD\INTC_PDD.h	1913;"	d
INTC_PDD_SetPriorityVector30	.\Static_Code\PDD\INTC_PDD.h	1863;"	d
INTC_PDD_SetPriorityVector31	.\Static_Code\PDD\INTC_PDD.h	1813;"	d
INTC_PDD_SetPriorityVector33	.\Static_Code\PDD\INTC_PDD.h	1765;"	d
INTC_PDD_SetPriorityVector34	.\Static_Code\PDD\INTC_PDD.h	1716;"	d
INTC_PDD_SetPriorityVector35	.\Static_Code\PDD\INTC_PDD.h	1667;"	d
INTC_PDD_SetPriorityVector36	.\Static_Code\PDD\INTC_PDD.h	1618;"	d
INTC_PDD_SetPriorityVector39	.\Static_Code\PDD\INTC_PDD.h	6363;"	d
INTC_PDD_SetPriorityVector40	.\Static_Code\PDD\INTC_PDD.h	6314;"	d
INTC_PDD_SetPriorityVector41	.\Static_Code\PDD\INTC_PDD.h	6267;"	d
INTC_PDD_SetPriorityVector42	.\Static_Code\PDD\INTC_PDD.h	6219;"	d
INTC_PDD_SetPriorityVector47	.\Static_Code\PDD\INTC_PDD.h	6170;"	d
INTC_PDD_SetPriorityVector48	.\Static_Code\PDD\INTC_PDD.h	6121;"	d
INTC_PDD_SetPriorityVector49	.\Static_Code\PDD\INTC_PDD.h	6073;"	d
INTC_PDD_SetPriorityVector5	.\Static_Code\PDD\INTC_PDD.h	2555;"	d
INTC_PDD_SetPriorityVector50	.\Static_Code\PDD\INTC_PDD.h	6024;"	d
INTC_PDD_SetPriorityVector51	.\Static_Code\PDD\INTC_PDD.h	1569;"	d
INTC_PDD_SetPriorityVector52	.\Static_Code\PDD\INTC_PDD.h	1520;"	d
INTC_PDD_SetPriorityVector53	.\Static_Code\PDD\INTC_PDD.h	1470;"	d
INTC_PDD_SetPriorityVector54	.\Static_Code\PDD\INTC_PDD.h	1421;"	d
INTC_PDD_SetPriorityVector57	.\Static_Code\PDD\INTC_PDD.h	6509;"	d
INTC_PDD_SetPriorityVector58	.\Static_Code\PDD\INTC_PDD.h	6461;"	d
INTC_PDD_SetPriorityVector59	.\Static_Code\PDD\INTC_PDD.h	1371;"	d
INTC_PDD_SetPriorityVector6	.\Static_Code\PDD\INTC_PDD.h	2506;"	d
INTC_PDD_SetPriorityVector60	.\Static_Code\PDD\INTC_PDD.h	1323;"	d
INTC_PDD_SetPriorityVector62	.\Static_Code\PDD\INTC_PDD.h	1272;"	d
INTC_PDD_SetPriorityVector77	.\Static_Code\PDD\INTC_PDD.h	1220;"	d
INTC_PDD_SetPriorityVector78	.\Static_Code\PDD\INTC_PDD.h	1172;"	d
INTC_PDD_SetPriorityVector79	.\Static_Code\PDD\INTC_PDD.h	1123;"	d
INTC_PDD_SetPriorityVector8	.\Static_Code\PDD\INTC_PDD.h	2458;"	d
INTC_PDD_SetPriorityVector80	.\Static_Code\PDD\INTC_PDD.h	1074;"	d
INTC_PDD_SetPriorityVector81	.\Static_Code\PDD\INTC_PDD.h	1026;"	d
INTC_PDD_SetPriorityVector82	.\Static_Code\PDD\INTC_PDD.h	977;"	d
INTC_PDD_SetPriorityVector83	.\Static_Code\PDD\INTC_PDD.h	928;"	d
INTC_PDD_SetPriorityVector84	.\Static_Code\PDD\INTC_PDD.h	879;"	d
INTC_PDD_SetPriorityVector85	.\Static_Code\PDD\INTC_PDD.h	830;"	d
INTC_PDD_SetPriorityVector86	.\Static_Code\PDD\INTC_PDD.h	781;"	d
INTC_PDD_SetPriorityVector87	.\Static_Code\PDD\INTC_PDD.h	732;"	d
INTC_PDD_SetPriorityVector88	.\Static_Code\PDD\INTC_PDD.h	684;"	d
INTC_PDD_SetPriorityVector89	.\Static_Code\PDD\INTC_PDD.h	637;"	d
INTC_PDD_SetPriorityVector9	.\Static_Code\PDD\INTC_PDD.h	2409;"	d
INTC_PDD_SetPriorityVector90	.\Static_Code\PDD\INTC_PDD.h	6412;"	d
INTC_PDD_SetPriorityVector91	.\Static_Code\PDD\INTC_PDD.h	5974;"	d
INTC_PDD_SetPriorityVector92	.\Static_Code\PDD\INTC_PDD.h	588;"	d
INTC_PDD_SetPriorityVector93	.\Static_Code\PDD\INTC_PDD.h	538;"	d
INTC_PDD_SetPriorityVector94	.\Static_Code\PDD\INTC_PDD.h	489;"	d
INTC_PDD_SetPriorityVector95	.\Static_Code\PDD\INTC_PDD.h	441;"	d
INTC_PDD_SetVectorBaseAddress	.\Static_Code\PDD\INTC_PDD.h	2599;"	d
INTC_PDD_WriteControlReg	.\Static_Code\PDD\INTC_PDD.h	5933;"	d
INTC_PDD_WriteFastInterrupt0MatchReg	.\Static_Code\PDD\INTC_PDD.h	5571;"	d
INTC_PDD_WriteFastInterrupt0VectorAddressHighReg	.\Static_Code\PDD\INTC_PDD.h	5649;"	d
INTC_PDD_WriteFastInterrupt0VectorAddressLowReg	.\Static_Code\PDD\INTC_PDD.h	5609;"	d
INTC_PDD_WriteFastInterrupt1MatchReg	.\Static_Code\PDD\INTC_PDD.h	5689;"	d
INTC_PDD_WriteFastInterrupt1VectorAddressHighReg	.\Static_Code\PDD\INTC_PDD.h	5767;"	d
INTC_PDD_WriteFastInterrupt1VectorAddressLowReg	.\Static_Code\PDD\INTC_PDD.h	5727;"	d
INTC_PDD_WriteInterruptPriority0Reg	.\Static_Code\PDD\INTC_PDD.h	5077;"	d
INTC_PDD_WriteInterruptPriority10Reg	.\Static_Code\PDD\INTC_PDD.h	5419;"	d
INTC_PDD_WriteInterruptPriority11Reg	.\Static_Code\PDD\INTC_PDD.h	5457;"	d
INTC_PDD_WriteInterruptPriority12Reg	.\Static_Code\PDD\INTC_PDD.h	5495;"	d
INTC_PDD_WriteInterruptPriority1Reg	.\Static_Code\PDD\INTC_PDD.h	5115;"	d
INTC_PDD_WriteInterruptPriority2Reg	.\Static_Code\PDD\INTC_PDD.h	5153;"	d
INTC_PDD_WriteInterruptPriority3Reg	.\Static_Code\PDD\INTC_PDD.h	5191;"	d
INTC_PDD_WriteInterruptPriority4Reg	.\Static_Code\PDD\INTC_PDD.h	5229;"	d
INTC_PDD_WriteInterruptPriority5Reg	.\Static_Code\PDD\INTC_PDD.h	5267;"	d
INTC_PDD_WriteInterruptPriority6Reg	.\Static_Code\PDD\INTC_PDD.h	5305;"	d
INTC_PDD_WriteInterruptPriority8Reg	.\Static_Code\PDD\INTC_PDD.h	5343;"	d
INTC_PDD_WriteInterruptPriority9Reg	.\Static_Code\PDD\INTC_PDD.h	5381;"	d
INTC_PDD_WriteVectorBaseAddressReg	.\Static_Code\PDD\INTC_PDD.h	5533;"	d
INTC_VBA	.\Static_Code\IO_Map\MC56F82748.h	3702;"	d
INTC_VBA_REG	.\Static_Code\IO_Map\MC56F82748.h	3365;"	d
INTC_VBA_VECTOR_BASE_ADDRESS	.\Static_Code\IO_Map\MC56F82748.h	3602;"	d
INTC_VBA_VECTOR_BASE_ADDRESS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3600;"	d
INTC_VBA_VECTOR_BASE_ADDRESS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3601;"	d
INTEN	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t INTEN;                                  \/**< Interrupt Enable Register, array offset: 0x13, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
INTVAL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t INTVAL;                                 \/**< COP Interrupt Value Register, offset: 0x3 *\/$/;"	m	struct:COP_MemMap
INT_ADC_CC0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_ADC_CC0                  = 30,               \/**< ADC Conversion Complete; any scan type except Converter B in non_simultaneous parallel scan mode *\/$/;"	e	enum:__anon46
INT_ADC_CC1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_ADC_CC1                  = 29,               \/**< ADC Conversion Complete; Converter B in non-simultaneous parallel scan mode *\/$/;"	e	enum:__anon46
INT_ADC_ERR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_ADC_ERR                  = 31,               \/**< ADC zero crossing; low limit; and high limit *\/$/;"	e	enum:__anon46
INT_BKPT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_BKPT                     = 7,                \/**< EOnCE Breakpoint Unit *\/$/;"	e	enum:__anon46
INT_BUS_ERR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_BUS_ERR                  = 11,               \/**< Bus Error Interrupt *\/$/;"	e	enum:__anon46
INT_CMPA	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_CMPA                     = 93,               \/**< Rising Edge; Falling Edge *\/$/;"	e	enum:__anon46
INT_CMPB	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_CMPB                     = 92,               \/**< Rising Edge; Falling Edge *\/$/;"	e	enum:__anon46
INT_CMPC	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_CMPC                     = 91,               \/**< Rising Edge; Falling Edge *\/$/;"	e	enum:__anon46
INT_CMPD	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_CMPD                     = 90,               \/**< Rising Edge; Falling Edge *\/$/;"	e	enum:__anon46
INT_COP_INT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_COP_INT                  = 108,              \/**< COP_Warning *\/$/;"	e	enum:__anon46
INT_COP_RESET	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_COP_RESET                = 1,                \/**< Reserved for COP Reset Overlay *\/$/;"	e	enum:__anon46
INT_DMA0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_DMA0                     = 36,               \/**< DMA 0 Service Req *\/$/;"	e	enum:__anon46
INT_DMA1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_DMA1                     = 35,               \/**< DMA 1 Service Req *\/$/;"	e	enum:__anon46
INT_DMA2	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_DMA2                     = 34,               \/**< DMA 2 Service Req *\/$/;"	e	enum:__anon46
INT_DMA3	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_DMA3                     = 33,               \/**< DMA 3 Service Req *\/$/;"	e	enum:__anon46
INT_ERROR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_ERROR                    = 39,               \/**< Error *\/$/;"	e	enum:__anon46
INT_EWM_INT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_EWM_INT                  = 109,              \/**< EWM_Indicate *\/$/;"	e	enum:__anon46
INT_EXT_MODE	.\Static_Code\System\PE_Const.h	23;"	d
INT_FTFA_CC	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_FTFA_CC                  = 89,               \/**< Command Complete *\/$/;"	e	enum:__anon46
INT_FTFA_RDCOL	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_FTFA_RDCOL               = 88,               \/**< Access Error *\/$/;"	e	enum:__anon46
INT_GPIOA	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_GPIOA                    = 107,              \/**< GPIO *\/$/;"	e	enum:__anon46
INT_GPIOB	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_GPIOB                    = 106,              \/**< GPIO *\/$/;"	e	enum:__anon46
INT_GPIOC	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_GPIOC                    = 105,              \/**< GPIO *\/$/;"	e	enum:__anon46
INT_GPIOD	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_GPIOD                    = 104,              \/**< GPIO *\/$/;"	e	enum:__anon46
INT_GPIOE	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_GPIOE                    = 103,              \/**< GPIO *\/$/;"	e	enum:__anon46
INT_GPIOF	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_GPIOF                    = 102,              \/**< GPIO *\/$/;"	e	enum:__anon46
INT_HW_RESET	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_HW_RESET                 = 0,                \/**< Reserved for Reset Overlay *\/$/;"	e	enum:__anon46
INT_IIC0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_IIC0                     = 62,               \/**< Complete 1-byte transfer (TCF); Match of received calling address (IAAS); Arbitration Lost (ARBL); SMBus Timeout (SLTF) Interrupts. Stop detect interrupt for which local enable is CR1[IICIE] and FLT[STOPIE]. *\/$/;"	e	enum:__anon46
INT_ILLEGAL_OP	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_ILLEGAL_OP               = 2,                \/**< Illegal Instruction *\/$/;"	e	enum:__anon46
INT_LVI1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_LVI1                     = 19,               \/**< Low Voltage Interrupt *\/$/;"	e	enum:__anon46
INT_MISALIGNED	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_MISALIGNED               = 5,                \/**< Misaligned Data Access *\/$/;"	e	enum:__anon46
INT_OCCS	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_OCCS                     = 20,               \/**< PLL Loss of Lock 0; PLL Loss of Lock 1; PLL Loss of Reference Clock *\/$/;"	e	enum:__anon46
INT_OVERFLOW	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_OVERFLOW                 = 4,                \/**< Hardware Stack Overflow *\/$/;"	e	enum:__anon46
INT_PIT0_ROLLOVR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_PIT0_ROLLOVR             = 95,               \/**< Roll Over *\/$/;"	e	enum:__anon46
INT_PIT1_ROLLOVR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_PIT1_ROLLOVR             = 94,               \/**< Roll Over *\/$/;"	e	enum:__anon46
INT_QSCI0_RCV	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI0_RCV                = 52,               \/**< Receive Data Register Full *\/$/;"	e	enum:__anon46
INT_QSCI0_RERR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI0_RERR               = 51,               \/**< Receiver Error *\/$/;"	e	enum:__anon46
INT_QSCI0_TDRE	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI0_TDRE               = 54,               \/**< Transmit Data Register Empty *\/$/;"	e	enum:__anon46
INT_QSCI0_TIDLE	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI0_TIDLE              = 53,               \/**< Transmitter Idle *\/$/;"	e	enum:__anon46
INT_QSCI1_RCV	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI1_RCV                = 48,               \/**< Receive Data Register Full *\/$/;"	e	enum:__anon46
INT_QSCI1_RERR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI1_RERR               = 47,               \/**< Receiver Error *\/$/;"	e	enum:__anon46
INT_QSCI1_TDRE	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI1_TDRE               = 50,               \/**< Transmit Data Register Empty *\/$/;"	e	enum:__anon46
INT_QSCI1_TIDLE	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSCI1_TIDLE              = 49,               \/**< Transmitter Idle *\/$/;"	e	enum:__anon46
INT_QSPI0_RCV	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSPI0_RCV                = 60,               \/**< Receiver Full *\/$/;"	e	enum:__anon46
INT_QSPI0_XMIT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSPI0_XMIT               = 59,               \/**< Transmitter Empty *\/$/;"	e	enum:__anon46
INT_QSPI1_RCV	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSPI1_RCV                = 58,               \/**< Receiver Full *\/$/;"	e	enum:__anon46
INT_QSPI1_XMIT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_QSPI1_XMIT               = 57,               \/**< Transmitter Empty *\/$/;"	e	enum:__anon46
INT_RX_REG	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_RX_REG                   = 10,               \/**< EOnCE Receive Register Full *\/$/;"	e	enum:__anon46
INT_RX_WARN	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_RX_WARN                  = 41,               \/**< Receive Warning *\/$/;"	e	enum:__anon46
INT_STPCNT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_STPCNT                   = 6,                \/**< EOnCE Step Counter Interrupt *\/$/;"	e	enum:__anon46
INT_SWI0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_SWI0                     = 17,               \/**< SW Interrupt 0 *\/$/;"	e	enum:__anon46
INT_SWI1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_SWI1                     = 16,               \/**< SW Interrupt 1 *\/$/;"	e	enum:__anon46
INT_SWI2	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_SWI2                     = 15,               \/**< SW Interrupt 2 *\/$/;"	e	enum:__anon46
INT_SWI3	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_SWI3                     = 3,                \/**< SW Interrupt 3 *\/$/;"	e	enum:__anon46
INT_SWILP	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_SWILP                    = 110               \/**< SWILP *\/$/;"	e	enum:__anon46
INT_TMRA_0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TMRA_0                   = 28,               \/**< Timer Compare; Timer Overflow; Input Edge Flag;Timer Compare Flag 1; Timer Compare Flag 2 *\/$/;"	e	enum:__anon46
INT_TMRA_1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TMRA_1                   = 27,               \/**< Timer Compare; Timer Overflow; Input Edge Flag;Timer Compare Flag 1; Timer Compare Flag 2 *\/$/;"	e	enum:__anon46
INT_TMRA_2	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TMRA_2                   = 26,               \/**< Timer Compare; Timer Overflow; Input Edge Flag;Timer Compare Flag 1; Timer Compare Flag 2 *\/$/;"	e	enum:__anon46
INT_TMRA_3	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TMRA_3                   = 25,               \/**< Timer Compare; Timer Overflow; Input Edge Flag;Timer Compare Flag 1; Timer Compare Flag 2 *\/$/;"	e	enum:__anon46
INT_TRBUF	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TRBUF                    = 8,                \/**< EOnCE Trace Buffer Interrupt *\/$/;"	e	enum:__anon46
INT_TX_REG	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TX_REG                   = 9,                \/**< EOnCE Transmit Register Empty *\/$/;"	e	enum:__anon46
INT_TX_WARN	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_TX_WARN                  = 40,               \/**< Transmit Warning *\/$/;"	e	enum:__anon46
INT_WAKEUP	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_WAKEUP                   = 42,               \/**< Wakeup *\/$/;"	e	enum:__anon46
INT_XBARA	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_XBARA                    = 18,               \/**< Crossbar Interrupt *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_CAP	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_CAP            = 80,               \/**< Logic Or'ed all Submodule 0-3 Input Captures *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_CMP0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_CMP0           = 87,               \/**< Submodule 0 Compare *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_CMP1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_CMP1           = 85,               \/**< Submodule 1 Compare *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_CMP2	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_CMP2           = 83,               \/**< Submodule 2 Compare *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_CMP3	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_CMP3           = 81,               \/**< Submodule 3 Compare *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_FAULT	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_FAULT          = 77,               \/**< Fault Condition *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_RELOAD0	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_RELOAD0        = 86,               \/**< Submodule 0 Reload *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_RELOAD0_ISR	.\Generated_Code\PWMA_Config.h	484;"	d
INT_eFlexPWMA_RELOAD1	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_RELOAD1        = 84,               \/**< Submodule 1 Reload *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_RELOAD2	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_RELOAD2        = 82,               \/**< Submodule 2 Reload *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_RELOAD3	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_RELOAD3        = 79,               \/**< Submodule 3 Reload *\/$/;"	e	enum:__anon46
INT_eFlexPWMA_RERR	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_eFlexPWMA_RERR           = 78,               \/**< Reload Error *\/$/;"	e	enum:__anon46
INT_reserved100	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved100              = 100,              \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved101	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved101              = 101,              \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved12	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved12               = 12,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved13	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved13               = 13,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved14	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved14               = 14,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved21	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved21               = 21,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved22	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved22               = 22,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved23	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved23               = 23,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved24	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved24               = 24,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved32	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved32               = 32,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved37	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved37               = 37,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved38	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved38               = 38,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved43	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved43               = 43,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved44	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved44               = 44,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved45	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved45               = 45,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved46	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved46               = 46,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved55	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved55               = 55,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved56	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved56               = 56,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved61	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved61               = 61,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved63	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved63               = 63,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved64	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved64               = 64,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved65	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved65               = 65,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved66	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved66               = 66,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved67	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved67               = 67,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved68	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved68               = 68,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved69	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved69               = 69,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved70	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved70               = 70,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved71	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved71               = 71,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved72	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved72               = 72,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved73	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved73               = 73,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved74	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved74               = 74,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved75	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved75               = 75,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved76	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved76               = 76,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved96	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved96               = 96,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved97	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved97               = 97,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved98	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved98               = 98,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
INT_reserved99	.\Static_Code\IO_Map\MC56F82748.h	/^  INT_reserved99               = 99,               \/**< Reserved interrupt *\/$/;"	e	enum:__anon46
IOSAHI	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IOSAHI;                                 \/**< I\/O Short Address Location Register, offset: 0x14 *\/$/;"	m	struct:SIM_MemMap
IOSALO	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IOSALO;                                 \/**< I\/O Short Address Location Register, offset: 0x15 *\/$/;"	m	struct:SIM_MemMap
IPOLR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPOLR;                                  \/**< GPIO Interrupt Polarity Register, offset: 0x6 *\/$/;"	m	struct:GPIO_MemMap
IPR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR;                                    \/**< GPIO Interrupt Pending Register, offset: 0x7 *\/$/;"	m	struct:GPIO_MemMap
IPR0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR0;                                   \/**< Interrupt Priority Register 0, offset: 0x0 *\/$/;"	m	struct:INTC_MemMap
IPR1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR1;                                   \/**< Interrupt Priority Register 1, offset: 0x1 *\/$/;"	m	struct:INTC_MemMap
IPR10	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR10;                                  \/**< Interrupt Priority Register 10, offset: 0xA *\/$/;"	m	struct:INTC_MemMap
IPR11	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR11;                                  \/**< Interrupt Priority Register 11, offset: 0xB *\/$/;"	m	struct:INTC_MemMap
IPR12	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR12;                                  \/**< Interrupt Priority Register 12, offset: 0xC *\/$/;"	m	struct:INTC_MemMap
IPR2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR2;                                   \/**< Interrupt Priority Register 2, offset: 0x2 *\/$/;"	m	struct:INTC_MemMap
IPR3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR3;                                   \/**< Interrupt Priority Register 3, offset: 0x3 *\/$/;"	m	struct:INTC_MemMap
IPR4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR4;                                   \/**< Interrupt Priority Register 4, offset: 0x4 *\/$/;"	m	struct:INTC_MemMap
IPR5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR5;                                   \/**< Interrupt Priority Register 5, offset: 0x5 *\/$/;"	m	struct:INTC_MemMap
IPR6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR6;                                   \/**< Interrupt Priority Register 6, offset: 0x6 *\/$/;"	m	struct:INTC_MemMap
IPR8	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR8;                                   \/**< Interrupt Priority Register 8, offset: 0x8 *\/$/;"	m	struct:INTC_MemMap
IPR9	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPR9;                                   \/**< Interrupt Priority Register 9, offset: 0x9 *\/$/;"	m	struct:INTC_MemMap
IPSn	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IPSn;                                   \/**< Internal Peripheral Select Register, offset: 0x22 *\/$/;"	m	struct:SIM_MemMap
IRQInterruptIndex	.\Static_Code\IO_Map\MC56F82748.h	/^} IRQInterruptIndex;$/;"	t	typeref:enum:__anon46
IRQP0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP0;                                  \/**< IRQ Pending Register 0, offset: 0x14 *\/$/;"	m	struct:INTC_MemMap
IRQP1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP1;                                  \/**< IRQ Pending Register 1, offset: 0x15 *\/$/;"	m	struct:INTC_MemMap
IRQP2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP2;                                  \/**< IRQ Pending Register 2, offset: 0x16 *\/$/;"	m	struct:INTC_MemMap
IRQP3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP3;                                  \/**< IRQ Pending Register 3, offset: 0x17 *\/$/;"	m	struct:INTC_MemMap
IRQP4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP4;                                  \/**< IRQ Pending Register 4, offset: 0x18 *\/$/;"	m	struct:INTC_MemMap
IRQP5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP5;                                  \/**< IRQ Pending Register 5, offset: 0x19 *\/$/;"	m	struct:INTC_MemMap
IRQP6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t IRQP6;                                  \/**< IRQ Pending Register 6, offset: 0x1A *\/$/;"	m	struct:INTC_MemMap
Index	.\Static_Code\System\PE_Types.h	/^        UWord16 Index    :1;$/;"	m	struct:__anon74
InputErrorK_1	.\Static_Code\System\PE_Types.h	/^   Word16 InputErrorK_1;$/;"	m	struct:__anon82
InputTransposeMode	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_TTransposeType InputTransposeMode; \/* Input transpose type *\/$/;"	m	struct:__anon13
Int16	.\Static_Code\System\PE_Types.h	/^typedef int            Int16;$/;"	t
Int32	.\Static_Code\System\PE_Types.h	/^typedef long           Int32;$/;"	t
Int8	.\Static_Code\System\PE_Types.h	/^typedef signed char    Int8;$/;"	t
IntegralGain	.\Static_Code\System\PE_Types.h	/^   Word16 IntegralGain;$/;"	m	struct:__anon82
IntegralGain	.\Static_Code\System\PE_Types.h	/^   Word16 IntegralGain;$/;"	m	struct:__anon83
IntegralGainScale	.\Static_Code\System\PE_Types.h	/^   Word16 IntegralGainScale;$/;"	m	struct:__anon82
IntegralGainScale	.\Static_Code\System\PE_Types.h	/^   Word16 IntegralGainScale;$/;"	m	struct:__anon83
IntegralPortionK_1	.\Static_Code\System\PE_Types.h	/^   Word16 IntegralPortionK_1;$/;"	m	struct:__anon82
IntegralPortionK_1	.\Static_Code\System\PE_Types.h	/^   Word16 IntegralPortionK_1;$/;"	m	struct:__anon83
LDD_ADC_CHANNEL_0_PIN	.\Generated_Code\PE_LDD.h	908;"	d
LDD_ADC_CHANNEL_10_PIN	.\Generated_Code\PE_LDD.h	918;"	d
LDD_ADC_CHANNEL_11_PIN	.\Generated_Code\PE_LDD.h	919;"	d
LDD_ADC_CHANNEL_12_PIN	.\Generated_Code\PE_LDD.h	920;"	d
LDD_ADC_CHANNEL_13_PIN	.\Generated_Code\PE_LDD.h	921;"	d
LDD_ADC_CHANNEL_14_PIN	.\Generated_Code\PE_LDD.h	922;"	d
LDD_ADC_CHANNEL_15_PIN	.\Generated_Code\PE_LDD.h	923;"	d
LDD_ADC_CHANNEL_16_PIN	.\Generated_Code\PE_LDD.h	924;"	d
LDD_ADC_CHANNEL_17_PIN	.\Generated_Code\PE_LDD.h	925;"	d
LDD_ADC_CHANNEL_18_PIN	.\Generated_Code\PE_LDD.h	926;"	d
LDD_ADC_CHANNEL_19_PIN	.\Generated_Code\PE_LDD.h	927;"	d
LDD_ADC_CHANNEL_1_PIN	.\Generated_Code\PE_LDD.h	909;"	d
LDD_ADC_CHANNEL_20_PIN	.\Generated_Code\PE_LDD.h	928;"	d
LDD_ADC_CHANNEL_21_PIN	.\Generated_Code\PE_LDD.h	929;"	d
LDD_ADC_CHANNEL_22_PIN	.\Generated_Code\PE_LDD.h	930;"	d
LDD_ADC_CHANNEL_23_PIN	.\Generated_Code\PE_LDD.h	931;"	d
LDD_ADC_CHANNEL_24_PIN	.\Generated_Code\PE_LDD.h	932;"	d
LDD_ADC_CHANNEL_25_PIN	.\Generated_Code\PE_LDD.h	933;"	d
LDD_ADC_CHANNEL_26_PIN	.\Generated_Code\PE_LDD.h	934;"	d
LDD_ADC_CHANNEL_27_PIN	.\Generated_Code\PE_LDD.h	935;"	d
LDD_ADC_CHANNEL_28_PIN	.\Generated_Code\PE_LDD.h	936;"	d
LDD_ADC_CHANNEL_29_PIN	.\Generated_Code\PE_LDD.h	937;"	d
LDD_ADC_CHANNEL_2_PIN	.\Generated_Code\PE_LDD.h	910;"	d
LDD_ADC_CHANNEL_30_PIN	.\Generated_Code\PE_LDD.h	938;"	d
LDD_ADC_CHANNEL_31_PIN	.\Generated_Code\PE_LDD.h	939;"	d
LDD_ADC_CHANNEL_3_PIN	.\Generated_Code\PE_LDD.h	911;"	d
LDD_ADC_CHANNEL_4_PIN	.\Generated_Code\PE_LDD.h	912;"	d
LDD_ADC_CHANNEL_5_PIN	.\Generated_Code\PE_LDD.h	913;"	d
LDD_ADC_CHANNEL_6_PIN	.\Generated_Code\PE_LDD.h	914;"	d
LDD_ADC_CHANNEL_7_PIN	.\Generated_Code\PE_LDD.h	915;"	d
LDD_ADC_CHANNEL_8_PIN	.\Generated_Code\PE_LDD.h	916;"	d
LDD_ADC_CHANNEL_9_PIN	.\Generated_Code\PE_LDD.h	917;"	d
LDD_ADC_HIGH_VOLT_REF_1_PIN	.\Generated_Code\PE_LDD.h	946;"	d
LDD_ADC_HIGH_VOLT_REF_PIN	.\Generated_Code\PE_LDD.h	944;"	d
LDD_ADC_LOW_VOLT_REF_1_PIN	.\Generated_Code\PE_LDD.h	945;"	d
LDD_ADC_LOW_VOLT_REF_PIN	.\Generated_Code\PE_LDD.h	943;"	d
LDD_ADC_ON_HIGH_LIMIT	.\Generated_Code\PE_LDD.h	948;"	d
LDD_ADC_ON_LOW_LIMIT	.\Generated_Code\PE_LDD.h	949;"	d
LDD_ADC_ON_MEASUREMENT_COMPLETE	.\Generated_Code\PE_LDD.h	951;"	d
LDD_ADC_ON_ZERO_CROSSING	.\Generated_Code\PE_LDD.h	950;"	d
LDD_ADC_TPinMask	.\Generated_Code\PE_LDD.h	/^} LDD_ADC_TPinMask;$/;"	t	typeref:struct:__anon42
LDD_ADC_TRIGGER_PIN	.\Generated_Code\PE_LDD.h	941;"	d
LDD_ADC_TSample	.\Generated_Code\PE_LDD.h	/^} LDD_ADC_TSample;$/;"	t	typeref:struct:__anon44
LDD_ADC_TZeroCrossingMode	.\Generated_Code\PE_LDD.h	/^} LDD_ADC_TZeroCrossingMode;$/;"	t	typeref:enum:__anon43
LDD_ADC_ZERO_CROSSING_ANY_CHANGE	.\Generated_Code\PE_LDD.h	/^  LDD_ADC_ZERO_CROSSING_ANY_CHANGE           = 0x03U \/*!< Zero crossing any change *\/$/;"	e	enum:__anon43
LDD_ADC_ZERO_CROSSING_DISABLED	.\Generated_Code\PE_LDD.h	/^  LDD_ADC_ZERO_CROSSING_DISABLED             = 0x00U, \/*!< Zero crossing disabled *\/$/;"	e	enum:__anon43
LDD_ADC_ZERO_CROSSING_NEGATIVE_TO_POSITIVE	.\Generated_Code\PE_LDD.h	/^  LDD_ADC_ZERO_CROSSING_NEGATIVE_TO_POSITIVE = 0x02U, \/*!< Zero crossing from negative to positive *\/$/;"	e	enum:__anon43
LDD_ADC_ZERO_CROSSING_POSITIVE_TO_NEGATIVE	.\Generated_Code\PE_LDD.h	/^  LDD_ADC_ZERO_CROSSING_POSITIVE_TO_NEGATIVE = 0x01U, \/*!< Zero crossing from positive to negative *\/$/;"	e	enum:__anon43
LDD_ANALOGCOMP_BOTH_EDGES	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_BOTH_EDGES = 0x06U$/;"	e	enum:__anon15
LDD_ANALOGCOMP_BOTH_EDGES_MODE	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_BOTH_EDGES_MODE = 0x18U$/;"	e	enum:__anon16
LDD_ANALOGCOMP_FALLING_EDGE	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_FALLING_EDGE = 0x02U,$/;"	e	enum:__anon15
LDD_ANALOGCOMP_FALLING_EDGE_MODE	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_FALLING_EDGE_MODE = 0x08U,$/;"	e	enum:__anon16
LDD_ANALOGCOMP_INPUT_0	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_0 = 0x00U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_1	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_1 = 0x01U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_2	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_2 = 0x02U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_3	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_3 = 0x03U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_4	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_4 = 0x04U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_5	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_5 = 0x05U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_6	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_6 = 0x06U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_7	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_7 = 0x07U,$/;"	e	enum:__anon14
LDD_ANALOGCOMP_INPUT_DISABLED	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_INPUT_DISABLED = 0x08U$/;"	e	enum:__anon14
LDD_ANALOGCOMP_NEGATIVE_INPUT_0_MASK	.\Generated_Code\PE_LDD.h	350;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_1_MASK	.\Generated_Code\PE_LDD.h	351;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_2_MASK	.\Generated_Code\PE_LDD.h	352;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_3_MASK	.\Generated_Code\PE_LDD.h	353;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_4_MASK	.\Generated_Code\PE_LDD.h	354;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_5_MASK	.\Generated_Code\PE_LDD.h	355;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_6_MASK	.\Generated_Code\PE_LDD.h	356;"	d
LDD_ANALOGCOMP_NEGATIVE_INPUT_7_MASK	.\Generated_Code\PE_LDD.h	357;"	d
LDD_ANALOGCOMP_NO_EDGE	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_NO_EDGE = 0x00U,$/;"	e	enum:__anon15
LDD_ANALOGCOMP_ON_COMPARE	.\Generated_Code\PE_LDD.h	337;"	d
LDD_ANALOGCOMP_OUTPUT_PIN_MASK	.\Generated_Code\PE_LDD.h	360;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_0_MASK	.\Generated_Code\PE_LDD.h	340;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_1_MASK	.\Generated_Code\PE_LDD.h	341;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_2_MASK	.\Generated_Code\PE_LDD.h	342;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_3_MASK	.\Generated_Code\PE_LDD.h	343;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_4_MASK	.\Generated_Code\PE_LDD.h	344;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_5_MASK	.\Generated_Code\PE_LDD.h	345;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_6_MASK	.\Generated_Code\PE_LDD.h	346;"	d
LDD_ANALOGCOMP_POSITIVE_INPUT_7_MASK	.\Generated_Code\PE_LDD.h	347;"	d
LDD_ANALOGCOMP_RISING_EDGE	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_RISING_EDGE = 0x04U,$/;"	e	enum:__anon15
LDD_ANALOGCOMP_RISING_EDGE_MODE	.\Generated_Code\PE_LDD.h	/^  LDD_ANALOGCOMP_RISING_EDGE_MODE = 0x10U,$/;"	e	enum:__anon16
LDD_ANALOGCOMP_WINDOWSAMPLE_PIN_MASK	.\Generated_Code\PE_LDD.h	363;"	d
LDD_AnalogComp_TComparatorInput	.\Generated_Code\PE_LDD.h	/^} LDD_AnalogComp_TComparatorInput;     \/* Type specifying comparator input number *\/$/;"	t	typeref:enum:__anon14
LDD_AnalogComp_TComparatorMode	.\Generated_Code\PE_LDD.h	/^} LDD_AnalogComp_TComparatorMode;      \/* Type specifying requested comparator mode *\/$/;"	t	typeref:enum:__anon16
LDD_AnalogComp_TCompareStatus	.\Generated_Code\PE_LDD.h	/^} LDD_AnalogComp_TCompareStatus;       \/* Type specifying current comparator output status *\/$/;"	t	typeref:enum:__anon15
LDD_AnalogComp_TOutputValue	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_AnalogComp_TOutputValue; \/* Type specifying comparator output value *\/$/;"	t
LDD_BITSIO_PIN_0	.\Generated_Code\PE_LDD.h	794;"	d
LDD_BITSIO_PIN_1	.\Generated_Code\PE_LDD.h	795;"	d
LDD_BITSIO_PIN_10	.\Generated_Code\PE_LDD.h	804;"	d
LDD_BITSIO_PIN_11	.\Generated_Code\PE_LDD.h	805;"	d
LDD_BITSIO_PIN_12	.\Generated_Code\PE_LDD.h	806;"	d
LDD_BITSIO_PIN_13	.\Generated_Code\PE_LDD.h	807;"	d
LDD_BITSIO_PIN_14	.\Generated_Code\PE_LDD.h	808;"	d
LDD_BITSIO_PIN_15	.\Generated_Code\PE_LDD.h	809;"	d
LDD_BITSIO_PIN_2	.\Generated_Code\PE_LDD.h	796;"	d
LDD_BITSIO_PIN_3	.\Generated_Code\PE_LDD.h	797;"	d
LDD_BITSIO_PIN_4	.\Generated_Code\PE_LDD.h	798;"	d
LDD_BITSIO_PIN_5	.\Generated_Code\PE_LDD.h	799;"	d
LDD_BITSIO_PIN_6	.\Generated_Code\PE_LDD.h	800;"	d
LDD_BITSIO_PIN_7	.\Generated_Code\PE_LDD.h	801;"	d
LDD_BITSIO_PIN_8	.\Generated_Code\PE_LDD.h	802;"	d
LDD_BITSIO_PIN_9	.\Generated_Code\PE_LDD.h	803;"	d
LDD_CAN_ACK_ERROR	.\Generated_Code\PE_LDD.h	830;"	d
LDD_CAN_BIT0_ERROR	.\Generated_Code\PE_LDD.h	828;"	d
LDD_CAN_BIT1_ERROR	.\Generated_Code\PE_LDD.h	829;"	d
LDD_CAN_CRC_ERROR	.\Generated_Code\PE_LDD.h	831;"	d
LDD_CAN_DATA_FRAME	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_DATA_FRAME,                  \/* Data frame type received or transmitted *\/$/;"	e	enum:__anon39
LDD_CAN_FILTER_CLOSED	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_FILTER_CLOSED     = 0x03U    \/* Filter closed - all frames are rejected *\/$/;"	e	enum:__anon38
LDD_CAN_FORM_ERROR	.\Generated_Code\PE_LDD.h	832;"	d
LDD_CAN_FOUR_8Bit_FILTERS	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_FOUR_8Bit_FILTERS = 0x02U,   \/* Four 8-bit - Four partial 8-bit Standard IDs per ID Filter Table element *\/$/;"	e	enum:__anon38
LDD_CAN_FREEZE_MODE	.\Generated_Code\PE_LDD.h	839;"	d
LDD_CAN_IDAcceptanceFilterMode	.\Generated_Code\PE_LDD.h	/^} LDD_CAN_IDAcceptanceFilterMode;$/;"	t	typeref:enum:__anon38
LDD_CAN_MB_RX_BUSY	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_MB_RX_BUSY,                  \/* Receive buffer is busy *\/$/;"	e	enum:__anon37
LDD_CAN_MB_RX_EMPTY	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_MB_RX_EMPTY,                 \/* Receive buffer is empty *\/$/;"	e	enum:__anon37
LDD_CAN_MB_RX_FULL	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_MB_RX_FULL,                  \/* Receive buffer is full *\/$/;"	e	enum:__anon37
LDD_CAN_MB_RX_NOT_ACTIVE	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_MB_RX_NOT_ACTIVE,            \/* Receive buffer is not active *\/ $/;"	e	enum:__anon37
LDD_CAN_MB_RX_OVERRUN	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_MB_RX_OVERRUN,               \/* Receive buffer is overrun *\/$/;"	e	enum:__anon37
LDD_CAN_MB_RX_RANSWER	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_MB_RX_RANSWER                \/* Receive buffer is ranswer *\/$/;"	e	enum:__anon37
LDD_CAN_MESSAGE_ID_EXT	.\Generated_Code\PE_LDD.h	836;"	d
LDD_CAN_ONE_32Bit_FILTER	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_ONE_32Bit_FILTER  = 0x00U,   \/* One 32-bit - One full ID (standard and extended) per ID Filter Table element*\/$/;"	e	enum:__anon38
LDD_CAN_ON_BUSOFF	.\Generated_Code\PE_LDD.h	822;"	d
LDD_CAN_ON_ERROR	.\Generated_Code\PE_LDD.h	825;"	d
LDD_CAN_ON_FREE_TXBUFFER	.\Generated_Code\PE_LDD.h	821;"	d
LDD_CAN_ON_FULL_RXBUFFER	.\Generated_Code\PE_LDD.h	820;"	d
LDD_CAN_ON_RXWARNING	.\Generated_Code\PE_LDD.h	824;"	d
LDD_CAN_ON_TXWARNING	.\Generated_Code\PE_LDD.h	823;"	d
LDD_CAN_ON_WAKEUP	.\Generated_Code\PE_LDD.h	826;"	d
LDD_CAN_REMOTE_FRAME	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_REMOTE_FRAME,                \/* Remote frame type  *\/$/;"	e	enum:__anon39
LDD_CAN_RESPONSE_FRAME	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_RESPONSE_FRAME               \/* Response frame type - Tx buffer send data after receiving remote frame with the same ID *\/$/;"	e	enum:__anon39
LDD_CAN_RUN_MODE	.\Generated_Code\PE_LDD.h	838;"	d
LDD_CAN_RX_OVERRUN_ERROR	.\Generated_Code\PE_LDD.h	834;"	d
LDD_CAN_RX_PIN	.\Generated_Code\PE_LDD.h	817;"	d
LDD_CAN_SLEEP_MODE	.\Generated_Code\PE_LDD.h	840;"	d
LDD_CAN_STUFFING_ERROR	.\Generated_Code\PE_LDD.h	833;"	d
LDD_CAN_TAccCode	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_CAN_TAccCode;     \/* Type specifying the acceptance code variable *\/$/;"	t
LDD_CAN_TAccMask	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_CAN_TAccMask;     \/* Type specifying the acceptance mask variable *\/$/;"	t
LDD_CAN_TBufferMask	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_CAN_TBufferMask;  \/* Type specifying the message buffer mask variable *\/$/;"	t
LDD_CAN_TElementIndex	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_CAN_TElementIndex; \/* Type specifying the filter table mask element index *\/$/;"	t
LDD_CAN_TErrorCounter	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_CAN_TErrorCounter; \/* Type specifying the error counter variable *\/$/;"	t
LDD_CAN_TErrorMask	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_CAN_TErrorMask;   \/* Type specifying the error mask variable *\/$/;"	t
LDD_CAN_TFrame	.\Generated_Code\PE_LDD.h	/^} LDD_CAN_TFrame;$/;"	t	typeref:struct:__anon41
LDD_CAN_TFrameType	.\Generated_Code\PE_LDD.h	/^} LDD_CAN_TFrameType;$/;"	t	typeref:enum:__anon39
LDD_CAN_TIDHitFilterIndex	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_CAN_TIDHitFilterIndex; \/* Type specifying the Rx FIFO hit filter index variable *\/ $/;"	t
LDD_CAN_TMBIndex	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_CAN_TMBIndex;      \/* CAN message buffer index *\/$/;"	t
LDD_CAN_TMessageID	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_CAN_TMessageID;   \/* Type specifying the ID mask variable *\/$/;"	t
LDD_CAN_TRunModeMask	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_CAN_TRunModeMask;  \/* Type specifying the run mode variable *\/ $/;"	t
LDD_CAN_TRxBufferState	.\Generated_Code\PE_LDD.h	/^} LDD_CAN_TRxBufferState;$/;"	t	typeref:enum:__anon37
LDD_CAN_TStats	.\Generated_Code\PE_LDD.h	/^} LDD_CAN_TStats;$/;"	t	typeref:struct:__anon40
LDD_CAN_TWO_16Bit_FILTERS	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_TWO_16Bit_FILTERS = 0x01U,   \/* Two 16-bit - Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element *\/$/;"	e	enum:__anon38
LDD_CAN_TX_PIN	.\Generated_Code\PE_LDD.h	818;"	d
LDD_CAPTURE_ON_CAPTURE	.\Generated_Code\PE_LDD.h	185;"	d
LDD_CAPTURE_ON_OVERRUN	.\Generated_Code\PE_LDD.h	186;"	d
LDD_CRC_16	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_16,$/;"	e	enum:__anon12
LDD_CRC_16_POLY_LOW	.\Generated_Code\PE_LDD.h	289;"	d
LDD_CRC_16_SEED_LOW	.\Generated_Code\PE_LDD.h	288;"	d
LDD_CRC_32	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_32,$/;"	e	enum:__anon12
LDD_CRC_32_POLY_HIGH	.\Generated_Code\PE_LDD.h	293;"	d
LDD_CRC_32_POLY_LOW	.\Generated_Code\PE_LDD.h	292;"	d
LDD_CRC_32_SEED_HIGH	.\Generated_Code\PE_LDD.h	291;"	d
LDD_CRC_32_SEED_LOW	.\Generated_Code\PE_LDD.h	290;"	d
LDD_CRC_BITS	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_BITS = 1,$/;"	e	enum:__anon11
LDD_CRC_BITS_AND_BYTES	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_BITS_AND_BYTES = 2,$/;"	e	enum:__anon11
LDD_CRC_BYTES	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_BYTES = 3$/;"	e	enum:__anon11
LDD_CRC_CCITT	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_CCITT,$/;"	e	enum:__anon12
LDD_CRC_CCITT_POLY_LOW	.\Generated_Code\PE_LDD.h	295;"	d
LDD_CRC_CCITT_SEED_LOW	.\Generated_Code\PE_LDD.h	294;"	d
LDD_CRC_DNP	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_DNP,$/;"	e	enum:__anon12
LDD_CRC_DNP_POLY_LOW	.\Generated_Code\PE_LDD.h	301;"	d
LDD_CRC_DNP_SEED_LOW	.\Generated_Code\PE_LDD.h	300;"	d
LDD_CRC_KERMIT	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_KERMIT,$/;"	e	enum:__anon12
LDD_CRC_KERMIT_POLY_LOW	.\Generated_Code\PE_LDD.h	299;"	d
LDD_CRC_KERMIT_SEED_LOW	.\Generated_Code\PE_LDD.h	298;"	d
LDD_CRC_MODBUS_16	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_MODBUS_16,$/;"	e	enum:__anon12
LDD_CRC_MODBUS_16_POLY_LOW	.\Generated_Code\PE_LDD.h	297;"	d
LDD_CRC_MODBUS_16_SEED_LOW	.\Generated_Code\PE_LDD.h	296;"	d
LDD_CRC_NO_TRANSPOSE	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_NO_TRANSPOSE = 0,$/;"	e	enum:__anon11
LDD_CRC_TCRCStandard	.\Generated_Code\PE_LDD.h	/^} LDD_CRC_TCRCStandard;$/;"	t	typeref:enum:__anon12
LDD_CRC_TTransposeType	.\Generated_Code\PE_LDD.h	/^} LDD_CRC_TTransposeType;$/;"	t	typeref:enum:__anon11
LDD_CRC_TUserCRCStandard	.\Generated_Code\PE_LDD.h	/^} LDD_CRC_TUserCRCStandard;$/;"	t	typeref:struct:__anon13
LDD_CRC_USER	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_USER$/;"	e	enum:__anon12
LDD_DAC_BUFFER_NORMAL_MODE	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_NORMAL_MODE          = 0x00U, \/* Normal (cyclic) mode *\/$/;"	e	enum:__anon28
LDD_DAC_BUFFER_SCAN_MODE	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_SCAN_MODE            = 0x02U \/* One-time scan mode *\/$/;"	e	enum:__anon28
LDD_DAC_BUFFER_SWING_MODE	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_SWING_MODE           = 0x01U, \/* Swing mode  *\/$/;"	e	enum:__anon28
LDD_DAC_BUFFER_WATERMARK_L0	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_WATERMARK_L0         = 0x00U,$/;"	e	enum:__anon29
LDD_DAC_BUFFER_WATERMARK_L2	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_WATERMARK_L2         = 0x01U,$/;"	e	enum:__anon29
LDD_DAC_BUFFER_WATERMARK_L4	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_WATERMARK_L4         = 0x02U,$/;"	e	enum:__anon29
LDD_DAC_BUFFER_WATERMARK_L6	.\Generated_Code\PE_LDD.h	/^  LDD_DAC_BUFFER_WATERMARK_L6         = 0x03U$/;"	e	enum:__anon29
LDD_DAC_ON_BUFFER_END	.\Generated_Code\PE_LDD.h	603;"	d
LDD_DAC_ON_BUFFER_START	.\Generated_Code\PE_LDD.h	604;"	d
LDD_DAC_ON_BUFFER_WATERMARK	.\Generated_Code\PE_LDD.h	605;"	d
LDD_DAC_ON_COMPLETE	.\Generated_Code\PE_LDD.h	606;"	d
LDD_DAC_ON_ERROR	.\Generated_Code\PE_LDD.h	607;"	d
LDD_DAC_OUTPUT_PIN_0	.\Generated_Code\PE_LDD.h	598;"	d
LDD_DAC_STATUS_FIFO_EMPTY	.\Generated_Code\PE_LDD.h	601;"	d
LDD_DAC_STATUS_FIFO_FULL	.\Generated_Code\PE_LDD.h	602;"	d
LDD_DAC_SYNC_PIN	.\Generated_Code\PE_LDD.h	599;"	d
LDD_DAC_TBufferMode	.\Generated_Code\PE_LDD.h	/^} LDD_DAC_TBufferMode;$/;"	t	typeref:enum:__anon28
LDD_DAC_TBufferWatermark	.\Generated_Code\PE_LDD.h	/^} LDD_DAC_TBufferWatermark;$/;"	t	typeref:enum:__anon29
LDD_DAC_TData	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_DAC_TData;        \/* The DAC data variable type *\/$/;"	t
LDD_DAC_TDataPtr	.\Generated_Code\PE_LDD.h	/^typedef void* LDD_DAC_TDataPtr;        \/* Type specifying the pointer to the DAC data variable *\/$/;"	t
LDD_DAC_TStatus	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_DAC_TStatus;      \/* The status of the DAC module variable type *\/$/;"	t
LDD_DAC_TWaveformSettings	.\Generated_Code\PE_LDD.h	/^} LDD_DAC_TWaveformSettings;$/;"	t	typeref:struct:__anon30
LDD_DMA_CHANNEL_0_MASK	.\Generated_Code\PE_LDD.h	655;"	d
LDD_DMA_CHANNEL_10_MASK	.\Generated_Code\PE_LDD.h	665;"	d
LDD_DMA_CHANNEL_11_MASK	.\Generated_Code\PE_LDD.h	666;"	d
LDD_DMA_CHANNEL_12_MASK	.\Generated_Code\PE_LDD.h	667;"	d
LDD_DMA_CHANNEL_13_MASK	.\Generated_Code\PE_LDD.h	668;"	d
LDD_DMA_CHANNEL_14_MASK	.\Generated_Code\PE_LDD.h	669;"	d
LDD_DMA_CHANNEL_15_MASK	.\Generated_Code\PE_LDD.h	670;"	d
LDD_DMA_CHANNEL_1_MASK	.\Generated_Code\PE_LDD.h	656;"	d
LDD_DMA_CHANNEL_2_MASK	.\Generated_Code\PE_LDD.h	657;"	d
LDD_DMA_CHANNEL_3_MASK	.\Generated_Code\PE_LDD.h	658;"	d
LDD_DMA_CHANNEL_4_MASK	.\Generated_Code\PE_LDD.h	659;"	d
LDD_DMA_CHANNEL_5_MASK	.\Generated_Code\PE_LDD.h	660;"	d
LDD_DMA_CHANNEL_6_MASK	.\Generated_Code\PE_LDD.h	661;"	d
LDD_DMA_CHANNEL_7_MASK	.\Generated_Code\PE_LDD.h	662;"	d
LDD_DMA_CHANNEL_8_MASK	.\Generated_Code\PE_LDD.h	663;"	d
LDD_DMA_CHANNEL_9_MASK	.\Generated_Code\PE_LDD.h	664;"	d
LDD_DMA_CHANNEL_PRIORITY_ERROR	.\Generated_Code\PE_LDD.h	647;"	d
LDD_DMA_CONFIGURATION_ERROR	.\Generated_Code\PE_LDD.h	642;"	d
LDD_DMA_COUNT_ERROR	.\Generated_Code\PE_LDD.h	652;"	d
LDD_DMA_DESTINATION_ADDRESS_ERROR	.\Generated_Code\PE_LDD.h	650;"	d
LDD_DMA_DESTINATION_BUS_ERROR	.\Generated_Code\PE_LDD.h	644;"	d
LDD_DMA_DESTINATION_OFFSET_ERROR	.\Generated_Code\PE_LDD.h	651;"	d
LDD_DMA_ON_COMPLETE	.\Generated_Code\PE_LDD.h	639;"	d
LDD_DMA_ON_ERROR	.\Generated_Code\PE_LDD.h	640;"	d
LDD_DMA_SCATTER_GATHER_ERROR	.\Generated_Code\PE_LDD.h	653;"	d
LDD_DMA_SOURCE_ADDRESS_ERROR	.\Generated_Code\PE_LDD.h	648;"	d
LDD_DMA_SOURCE_BUS_ERROR	.\Generated_Code\PE_LDD.h	643;"	d
LDD_DMA_SOURCE_OFFSET_ERROR	.\Generated_Code\PE_LDD.h	649;"	d
LDD_DMA_TData	.\Generated_Code\PE_LDD.h	/^typedef void     LDD_DMA_TData;$/;"	t
LDD_DMA_TErrorFlags	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_DMA_TErrorFlags;  \/* DMA controller error flags. See the DMA_LDD component's header file for detail description of allowed values. *\/$/;"	t
LDD_DMA_TRANSFER_BUSY	.\Generated_Code\PE_LDD.h	/^  LDD_DMA_TRANSFER_BUSY,               \/* Channel is active, request is serviced. *\/$/;"	e	enum:__anon31
LDD_DMA_TRANSFER_ERROR	.\Generated_Code\PE_LDD.h	/^  LDD_DMA_TRANSFER_ERROR               \/* Error detected. *\/$/;"	e	enum:__anon31
LDD_DMA_TRANSFER_IDLE	.\Generated_Code\PE_LDD.h	/^  LDD_DMA_TRANSFER_IDLE,               \/* Channel is idle, no request is serviced nor transfer completed. *\/$/;"	e	enum:__anon31
LDD_DMA_TRequestCount	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_DMA_TRequestCount;$/;"	t
LDD_DMA_TTransactionCount	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_DMA_TTransactionCount;$/;"	t
LDD_DMA_TTransactionSize	.\Generated_Code\PE_LDD.h	/^typedef uint8_t  LDD_DMA_TTransactionSize; \/* Type specifying the transfer size parameter used by the DMA component's methods. *\/$/;"	t
LDD_DMA_TTransferDataSize	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_DMA_TTransferDataSize;$/;"	t
LDD_DMA_TTransferState	.\Generated_Code\PE_LDD.h	/^} LDD_DMA_TTransferState;$/;"	t	typeref:enum:__anon31
LDD_EVENTCNTR_ON_END	.\Generated_Code\PE_LDD.h	207;"	d
LDD_FLASH_ACCESS_ERROR	.\Generated_Code\PE_LDD.h	697;"	d
LDD_FLASH_ERASE	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_ERASE,                     \/* Erase operation *\/$/;"	e	enum:__anon33
LDD_FLASH_ERASE_ALL_FLASH_BLOCKS	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_ERASE_ALL_FLASH_BLOCKS    = 0x44u \/* Erase all flash memory blocks *\/$/;"	e	enum:__anon32
LDD_FLASH_ERASE_BLOCK	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_ERASE_BLOCK,               \/* Erase block operation *\/$/;"	e	enum:__anon33
LDD_FLASH_ERASE_FLASH_BLOCK	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_ERASE_FLASH_BLOCK         = 0x08u, \/* Erase flash memory block *\/$/;"	e	enum:__anon32
LDD_FLASH_ERASE_SECTOR	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_ERASE_SECTOR              = 0x09u, \/* Erase sector *\/$/;"	e	enum:__anon32
LDD_FLASH_ERASE_VERIFICATION_ERROR	.\Generated_Code\PE_LDD.h	699;"	d
LDD_FLASH_FAILED	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_FAILED                     \/* Operation has failed *\/$/;"	e	enum:__anon34
LDD_FLASH_IDLE	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_IDLE,                      \/* No operation in progress *\/$/;"	e	enum:__anon34
LDD_FLASH_MULTIPLE_WRITE_ERROR	.\Generated_Code\PE_LDD.h	700;"	d
LDD_FLASH_NO_OPERATION	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_NO_OPERATION,              \/* No operation - initial state *\/$/;"	e	enum:__anon33
LDD_FLASH_ON_ERROR	.\Generated_Code\PE_LDD.h	694;"	d
LDD_FLASH_ON_OPERATION_COMPLETE	.\Generated_Code\PE_LDD.h	693;"	d
LDD_FLASH_PROTECTION_VIOLATION	.\Generated_Code\PE_LDD.h	698;"	d
LDD_FLASH_READ	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_READ,                      \/* Read operation *\/$/;"	e	enum:__anon33
LDD_FLASH_READ_1S_BLOCK	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_READ_1S_BLOCK             = 0x00u, \/* Checks if an entire program flash or data flash logical block has been erased to the specified margin level *\/$/;"	e	enum:__anon32
LDD_FLASH_READ_1S_SECTION	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_READ_1S_SECTION           = 0x01u, \/* Checks if a section of program flash or data flash memory is erased to the specified read margin level *\/$/;"	e	enum:__anon32
LDD_FLASH_READ_COLLISION_ERROR	.\Generated_Code\PE_LDD.h	696;"	d
LDD_FLASH_RUNNING	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_RUNNING,                   \/* Operation is in progress *\/$/;"	e	enum:__anon34
LDD_FLASH_START	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_START,                     \/* Start of the operation, no operation steps have been done yet *\/$/;"	e	enum:__anon34
LDD_FLASH_STOP	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_STOP,                      \/* The operation has been stopped *\/$/;"	e	enum:__anon34
LDD_FLASH_STOP_REQ	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_STOP_REQ,                  \/* The operation is in the STOP request mode *\/$/;"	e	enum:__anon34
LDD_FLASH_TAddress	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_FLASH_TAddress;   \/* Type specifying the Address parameter used by the FLASH component's methods *\/$/;"	t
LDD_FLASH_TCommand	.\Generated_Code\PE_LDD.h	/^} LDD_FLASH_TCommand;$/;"	t	typeref:enum:__anon32
LDD_FLASH_TDataSize	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_FLASH_TDataSize;  \/* Type specifying the Size parameter used by the FLASH component's methods *\/$/;"	t
LDD_FLASH_TErasableUnitSize	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_FLASH_TErasableUnitSize; \/* Type specifying the Size output parameter of the GetErasableUnitSize method (pointer to a variable of this type is passed to the method) *\/$/;"	t
LDD_FLASH_TErrorFlags	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_FLASH_TErrorFlags; \/* Type specifying FLASH component's error flags bit field *\/$/;"	t
LDD_FLASH_TErrorStatus	.\Generated_Code\PE_LDD.h	/^} LDD_FLASH_TErrorStatus;$/;"	t	typeref:struct:__anon35
LDD_FLASH_TOperationStatus	.\Generated_Code\PE_LDD.h	/^} LDD_FLASH_TOperationStatus;$/;"	t	typeref:enum:__anon34
LDD_FLASH_TOperationType	.\Generated_Code\PE_LDD.h	/^} LDD_FLASH_TOperationType;$/;"	t	typeref:enum:__anon33
LDD_FLASH_VERIFY_ERASED_BLOCK	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_VERIFY_ERASED_BLOCK        \/* Verify erased block operation *\/$/;"	e	enum:__anon33
LDD_FLASH_WRITE	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_WRITE,                     \/* Write operation *\/$/;"	e	enum:__anon33
LDD_FLASH_WRITE_BYTE	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_WRITE_BYTE                = 0x04u, \/* Program byte *\/$/;"	e	enum:__anon32
LDD_FLASH_WRITE_LONG_WORD	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_WRITE_LONG_WORD           = 0x06u, \/* Program long word *\/$/;"	e	enum:__anon32
LDD_FLASH_WRITE_PHRASE	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_WRITE_PHRASE              = 0x07u, \/* Program phrase *\/$/;"	e	enum:__anon32
LDD_FLASH_WRITE_WORD	.\Generated_Code\PE_LDD.h	/^  LDD_FLASH_WRITE_WORD                = 0x05u, \/* Program word *\/$/;"	e	enum:__anon32
LDD_FREECNTR_ON_INTERRUPT	.\Generated_Code\PE_LDD.h	214;"	d
LDD_FlexRAM_AS_EEPROM	.\Generated_Code\PE_LDD.h	/^  LDD_FlexRAM_AS_EEPROM                \/*!< FlexRAM area as EEPROM operations. *\/$/;"	e	enum:__anon5
LDD_FlexRAM_AS_RAM	.\Generated_Code\PE_LDD.h	/^  LDD_FlexRAM_AS_RAM,                  \/*!< FlexRAM area as traditional RAM operation. *\/ $/;"	e	enum:__anon5
LDD_GPIO_BOTH	.\Generated_Code\PE_LDD.h	/^  LDD_GPIO_BOTH     = 0x05U            \/*!< Event on rising and falling edge *\/$/;"	e	enum:__anon36
LDD_GPIO_DISABLED	.\Generated_Code\PE_LDD.h	/^  LDD_GPIO_DISABLED = 0x00U,           \/*!< Event doesn't invoke *\/$/;"	e	enum:__anon36
LDD_GPIO_FALLING	.\Generated_Code\PE_LDD.h	/^  LDD_GPIO_FALLING  = 0x03U,           \/*!< Event on falling edge *\/$/;"	e	enum:__anon36
LDD_GPIO_HIGH	.\Generated_Code\PE_LDD.h	/^  LDD_GPIO_HIGH     = 0x02U,           \/*!< Event when logic one *\/$/;"	e	enum:__anon36
LDD_GPIO_LOW	.\Generated_Code\PE_LDD.h	/^  LDD_GPIO_LOW      = 0x01U,           \/*!< Event when logic zero *\/$/;"	e	enum:__anon36
LDD_GPIO_ON_PORT_EVENT	.\Generated_Code\PE_LDD.h	775;"	d
LDD_GPIO_PIN_0	.\Generated_Code\PE_LDD.h	758;"	d
LDD_GPIO_PIN_1	.\Generated_Code\PE_LDD.h	759;"	d
LDD_GPIO_PIN_10	.\Generated_Code\PE_LDD.h	768;"	d
LDD_GPIO_PIN_11	.\Generated_Code\PE_LDD.h	769;"	d
LDD_GPIO_PIN_12	.\Generated_Code\PE_LDD.h	770;"	d
LDD_GPIO_PIN_13	.\Generated_Code\PE_LDD.h	771;"	d
LDD_GPIO_PIN_14	.\Generated_Code\PE_LDD.h	772;"	d
LDD_GPIO_PIN_15	.\Generated_Code\PE_LDD.h	773;"	d
LDD_GPIO_PIN_2	.\Generated_Code\PE_LDD.h	760;"	d
LDD_GPIO_PIN_3	.\Generated_Code\PE_LDD.h	761;"	d
LDD_GPIO_PIN_4	.\Generated_Code\PE_LDD.h	762;"	d
LDD_GPIO_PIN_5	.\Generated_Code\PE_LDD.h	763;"	d
LDD_GPIO_PIN_6	.\Generated_Code\PE_LDD.h	764;"	d
LDD_GPIO_PIN_7	.\Generated_Code\PE_LDD.h	765;"	d
LDD_GPIO_PIN_8	.\Generated_Code\PE_LDD.h	766;"	d
LDD_GPIO_PIN_9	.\Generated_Code\PE_LDD.h	767;"	d
LDD_GPIO_RISING	.\Generated_Code\PE_LDD.h	/^  LDD_GPIO_RISING   = 0x04U,           \/*!< Event on rising edge *\/$/;"	e	enum:__anon36
LDD_GPIO_TBitField	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_GPIO_TBitField;   \/*!< Abstract type specifying the bit field within the port. *\/$/;"	t
LDD_GPIO_TEventCondition	.\Generated_Code\PE_LDD.h	/^} LDD_GPIO_TEventCondition;$/;"	t	typeref:enum:__anon36
LDD_I2C_ACK_BYTE	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_ACK_BYTE,$/;"	e	enum:__anon24
LDD_I2C_ADDRTYPE_10BITS	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_ADDRTYPE_10BITS,$/;"	e	enum:__anon21
LDD_I2C_ADDRTYPE_7BITS	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_ADDRTYPE_7BITS,$/;"	e	enum:__anon21
LDD_I2C_ADDRTYPE_GENERAL_CALL	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_ADDRTYPE_GENERAL_CALL$/;"	e	enum:__anon21
LDD_I2C_ARBIT_LOST	.\Generated_Code\PE_LDD.h	480;"	d
LDD_I2C_BUSY	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_BUSY,$/;"	e	enum:__anon23
LDD_I2C_IDLE	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_IDLE$/;"	e	enum:__anon23
LDD_I2C_MASTER_NACK	.\Generated_Code\PE_LDD.h	481;"	d
LDD_I2C_NACK_BYTE	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_NACK_BYTE$/;"	e	enum:__anon24
LDD_I2C_NO_SEND_STOP	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_NO_SEND_STOP,$/;"	e	enum:__anon22
LDD_I2C_ON_BUS_START_DETECTED	.\Generated_Code\PE_LDD.h	475;"	d
LDD_I2C_ON_BUS_STOP_DETECTED	.\Generated_Code\PE_LDD.h	476;"	d
LDD_I2C_ON_ERROR	.\Generated_Code\PE_LDD.h	469;"	d
LDD_I2C_ON_MASTER_BLOCK_RECEIVED	.\Generated_Code\PE_LDD.h	464;"	d
LDD_I2C_ON_MASTER_BLOCK_SENT	.\Generated_Code\PE_LDD.h	463;"	d
LDD_I2C_ON_MASTER_BYTE_RECEIVED	.\Generated_Code\PE_LDD.h	473;"	d
LDD_I2C_ON_SLAVE_BLOCK_RECEIVED	.\Generated_Code\PE_LDD.h	466;"	d
LDD_I2C_ON_SLAVE_BLOCK_SENT	.\Generated_Code\PE_LDD.h	465;"	d
LDD_I2C_ON_SLAVE_BYTE_RECEIVED	.\Generated_Code\PE_LDD.h	474;"	d
LDD_I2C_ON_SLAVE_GENERAL_CALL_ADDR	.\Generated_Code\PE_LDD.h	472;"	d
LDD_I2C_ON_SLAVE_RX_REQUEST	.\Generated_Code\PE_LDD.h	468;"	d
LDD_I2C_ON_SLAVE_SM_BUS_ALERT_RESPONSE	.\Generated_Code\PE_LDD.h	471;"	d
LDD_I2C_ON_SLAVE_SM_BUS_CALL_ADDR	.\Generated_Code\PE_LDD.h	470;"	d
LDD_I2C_ON_SLAVE_TX_REQUEST	.\Generated_Code\PE_LDD.h	467;"	d
LDD_I2C_SCL_LOW_TIMEOUT	.\Generated_Code\PE_LDD.h	482;"	d
LDD_I2C_SCL_PIN	.\Generated_Code\PE_LDD.h	461;"	d
LDD_I2C_SDA_LOW_TIMEOUT	.\Generated_Code\PE_LDD.h	483;"	d
LDD_I2C_SDA_PIN	.\Generated_Code\PE_LDD.h	460;"	d
LDD_I2C_SEND_STOP	.\Generated_Code\PE_LDD.h	/^  LDD_I2C_SEND_STOP$/;"	e	enum:__anon22
LDD_I2C_SLAVE_NACK	.\Generated_Code\PE_LDD.h	484;"	d
LDD_I2C_SLAVE_RX_OVERRUN	.\Generated_Code\PE_LDD.h	479;"	d
LDD_I2C_SLAVE_TX_UNDERRUN	.\Generated_Code\PE_LDD.h	478;"	d
LDD_I2C_TAckType	.\Generated_Code\PE_LDD.h	/^} LDD_I2C_TAckType;$/;"	t	typeref:enum:__anon24
LDD_I2C_TAddr	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_I2C_TAddr;        \/* Type specifying the address variable *\/$/;"	t
LDD_I2C_TAddrType	.\Generated_Code\PE_LDD.h	/^} LDD_I2C_TAddrType;$/;"	t	typeref:enum:__anon21
LDD_I2C_TBusState	.\Generated_Code\PE_LDD.h	/^} LDD_I2C_TBusState;$/;"	t	typeref:enum:__anon23
LDD_I2C_TErrorMask	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_I2C_TErrorMask;   \/* Type specifying the error mask type. *\/$/;"	t
LDD_I2C_TMode	.\Generated_Code\PE_LDD.h	/^typedef bool LDD_I2C_TMode;            \/* Type specifynng the Actual operating mode *\/$/;"	t
LDD_I2C_TSendStop	.\Generated_Code\PE_LDD.h	/^} LDD_I2C_TSendStop;$/;"	t	typeref:enum:__anon22
LDD_I2C_TSize	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_I2C_TSize;        \/* Type specifying the length of the data or buffer. *\/$/;"	t
LDD_I2C_TStats	.\Generated_Code\PE_LDD.h	/^} LDD_I2C_TStats;$/;"	t	typeref:struct:__anon25
LDD_PPG_ON_END	.\Generated_Code\PE_LDD.h	221;"	d
LDD_PPG_Tfloat	.\Generated_Code\PE_LDD.h	/^typedef float LDD_PPG_Tfloat;          \/* Float type *\/$/;"	t
LDD_PS_Tfloat	.\Generated_Code\PE_LDD.h	/^typedef float LDD_PS_Tfloat;           \/* Float type *\/$/;"	t
LDD_PULSEACCUMULATOR_ON_COMPARE1	.\Generated_Code\PE_LDD.h	239;"	d
LDD_PULSEACCUMULATOR_ON_COMPARE2	.\Generated_Code\PE_LDD.h	240;"	d
LDD_PULSEACCUMULATOR_ON_EDGE	.\Generated_Code\PE_LDD.h	241;"	d
LDD_PULSEACCUMULATOR_ON_END	.\Generated_Code\PE_LDD.h	238;"	d
LDD_PULSEACCUMULATOR_ON_OVERRUN	.\Generated_Code\PE_LDD.h	237;"	d
LDD_PULSESTREAM_ON_END	.\Generated_Code\PE_LDD.h	248;"	d
LDD_PWM_ON_END	.\Generated_Code\PE_LDD.h	230;"	d
LDD_RealTime_Tfloat	.\Generated_Code\PE_LDD.h	/^typedef float LDD_RealTime_Tfloat;     \/* Float type *\/$/;"	t
LDD_SERIAL_CTS_PIN	.\Generated_Code\PE_LDD.h	399;"	d
LDD_SERIAL_FRAMING_ERROR	.\Generated_Code\PE_LDD.h	410;"	d
LDD_SERIAL_NOISE_ERROR	.\Generated_Code\PE_LDD.h	411;"	d
LDD_SERIAL_ON_BLOCK_RECEIVED	.\Generated_Code\PE_LDD.h	402;"	d
LDD_SERIAL_ON_BLOCK_SENT	.\Generated_Code\PE_LDD.h	403;"	d
LDD_SERIAL_ON_BREAK	.\Generated_Code\PE_LDD.h	404;"	d
LDD_SERIAL_ON_ERROR	.\Generated_Code\PE_LDD.h	406;"	d
LDD_SERIAL_ON_TXCOMPLETE	.\Generated_Code\PE_LDD.h	405;"	d
LDD_SERIAL_PARITY_ERROR	.\Generated_Code\PE_LDD.h	409;"	d
LDD_SERIAL_PARITY_EVEN	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_PARITY_EVEN,$/;"	e	enum:__anon17
LDD_SERIAL_PARITY_MARK	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_PARITY_MARK,$/;"	e	enum:__anon17
LDD_SERIAL_PARITY_NONE	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_PARITY_NONE,$/;"	e	enum:__anon17
LDD_SERIAL_PARITY_ODD	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_PARITY_ODD,$/;"	e	enum:__anon17
LDD_SERIAL_PARITY_SPACE	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_PARITY_SPACE$/;"	e	enum:__anon17
LDD_SERIAL_PARITY_UNDEF	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_PARITY_UNDEF,$/;"	e	enum:__anon17
LDD_SERIAL_RTS_PIN	.\Generated_Code\PE_LDD.h	400;"	d
LDD_SERIAL_RX_OVERRUN	.\Generated_Code\PE_LDD.h	408;"	d
LDD_SERIAL_RX_PIN	.\Generated_Code\PE_LDD.h	397;"	d
LDD_SERIAL_STOP_BIT_LEN_1	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_STOP_BIT_LEN_1,$/;"	e	enum:__anon18
LDD_SERIAL_STOP_BIT_LEN_1_5	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_STOP_BIT_LEN_1_5,$/;"	e	enum:__anon18
LDD_SERIAL_STOP_BIT_LEN_2	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_STOP_BIT_LEN_2$/;"	e	enum:__anon18
LDD_SERIAL_STOP_BIT_LEN_UNDEF	.\Generated_Code\PE_LDD.h	/^  LDD_SERIAL_STOP_BIT_LEN_UNDEF,$/;"	e	enum:__anon18
LDD_SERIAL_TBaudMode	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_SERIAL_TBaudMode;  \/* Type specifying the baud mode. *\/$/;"	t
LDD_SERIAL_TDataWidth	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_SERIAL_TDataWidth; \/* Bit length type. The number of bits transmitted by one character. *\/$/;"	t
LDD_SERIAL_TError	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_SERIAL_TError;    \/* Serial communication error type *\/$/;"	t
LDD_SERIAL_TLoopMode	.\Generated_Code\PE_LDD.h	/^} LDD_SERIAL_TLoopMode;$/;"	t	typeref:enum:__anon20
LDD_SERIAL_TParity	.\Generated_Code\PE_LDD.h	/^} LDD_SERIAL_TParity;$/;"	t	typeref:enum:__anon17
LDD_SERIAL_TSize	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_SERIAL_TSize;     \/* Type specifying the length of the data or buffer. *\/$/;"	t
LDD_SERIAL_TStats	.\Generated_Code\PE_LDD.h	/^} LDD_SERIAL_TStats;$/;"	t	typeref:struct:__anon19
LDD_SERIAL_TStopBitLen	.\Generated_Code\PE_LDD.h	/^} LDD_SERIAL_TStopBitLen;$/;"	t	typeref:enum:__anon18
LDD_SERIAL_TX_PIN	.\Generated_Code\PE_LDD.h	398;"	d
LDD_SPIMASTER_CLK_PIN	.\Generated_Code\PE_LDD.h	536;"	d
LDD_SPIMASTER_CSS_PIN	.\Generated_Code\PE_LDD.h	545;"	d
LDD_SPIMASTER_CS_0_PIN	.\Generated_Code\PE_LDD.h	537;"	d
LDD_SPIMASTER_CS_1_PIN	.\Generated_Code\PE_LDD.h	538;"	d
LDD_SPIMASTER_CS_2_PIN	.\Generated_Code\PE_LDD.h	539;"	d
LDD_SPIMASTER_CS_3_PIN	.\Generated_Code\PE_LDD.h	540;"	d
LDD_SPIMASTER_CS_4_PIN	.\Generated_Code\PE_LDD.h	541;"	d
LDD_SPIMASTER_CS_5_PIN	.\Generated_Code\PE_LDD.h	542;"	d
LDD_SPIMASTER_CS_6_PIN	.\Generated_Code\PE_LDD.h	543;"	d
LDD_SPIMASTER_CS_7_PIN	.\Generated_Code\PE_LDD.h	544;"	d
LDD_SPIMASTER_INPUT_PIN	.\Generated_Code\PE_LDD.h	534;"	d
LDD_SPIMASTER_ON_BLOCK_RECEIVED	.\Generated_Code\PE_LDD.h	547;"	d
LDD_SPIMASTER_ON_BLOCK_SENT	.\Generated_Code\PE_LDD.h	548;"	d
LDD_SPIMASTER_ON_ERROR	.\Generated_Code\PE_LDD.h	549;"	d
LDD_SPIMASTER_OUTPUT_PIN	.\Generated_Code\PE_LDD.h	535;"	d
LDD_SPIMASTER_PARITY_ERROR	.\Generated_Code\PE_LDD.h	552;"	d
LDD_SPIMASTER_RX_OVERFLOW	.\Generated_Code\PE_LDD.h	551;"	d
LDD_SPIMASTER_TError	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_SPIMASTER_TError; \/* Communication error type *\/$/;"	t
LDD_SPIMASTER_TStats	.\Generated_Code\PE_LDD.h	/^} LDD_SPIMASTER_TStats;$/;"	t	typeref:struct:__anon26
LDD_SPISLAVE_CLK_PIN	.\Generated_Code\PE_LDD.h	571;"	d
LDD_SPISLAVE_INPUT_PIN	.\Generated_Code\PE_LDD.h	569;"	d
LDD_SPISLAVE_ON_BLOCK_RECEIVED	.\Generated_Code\PE_LDD.h	574;"	d
LDD_SPISLAVE_ON_BLOCK_SENT	.\Generated_Code\PE_LDD.h	575;"	d
LDD_SPISLAVE_ON_ERROR	.\Generated_Code\PE_LDD.h	576;"	d
LDD_SPISLAVE_OUTPUT_PIN	.\Generated_Code\PE_LDD.h	570;"	d
LDD_SPISLAVE_PARITY_ERROR	.\Generated_Code\PE_LDD.h	580;"	d
LDD_SPISLAVE_RX_OVERFLOW	.\Generated_Code\PE_LDD.h	578;"	d
LDD_SPISLAVE_SS_PIN	.\Generated_Code\PE_LDD.h	572;"	d
LDD_SPISLAVE_TError	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_SPISLAVE_TError;  \/* Communication error type *\/$/;"	t
LDD_SPISLAVE_TStats	.\Generated_Code\PE_LDD.h	/^} LDD_SPISLAVE_TStats;$/;"	t	typeref:struct:__anon27
LDD_SPISLAVE_TX_UNDERFLOW	.\Generated_Code\PE_LDD.h	579;"	d
LDD_SetClockConfiguration	.\Generated_Code\PE_LDD.c	/^void LDD_SetClockConfiguration(LDD_TClockConfiguration ClockConfiguration)$/;"	f
LDD_TBackDoorKey	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_TBackDoorKey;      \/*!< Backdoor key type. *\/$/;"	t
LDD_TCallback	.\Generated_Code\PE_LDD.h	/^typedef void (* LDD_TCallback)(LDD_TCallbackParam *CallbackParam); \/*!< Callback type used for definition of callback functions. *\/$/;"	t
LDD_TCallbackParam	.\Generated_Code\PE_LDD.h	/^typedef void LDD_TCallbackParam;       \/*!< Pointer to this type specifies the user data to be passed as a callback parameter. *\/$/;"	t
LDD_TClockConfiguration	.\Generated_Code\PE_LDD.h	/^typedef uint8_t LDD_TClockConfiguration; \/*!< CPU clock configuration type. *\/$/;"	t
LDD_TData	.\Generated_Code\PE_LDD.h	/^typedef void LDD_TData;                \/*!< General pointer to data. *\/$/;"	t
LDD_TDeviceData	.\Generated_Code\PE_LDD.h	/^typedef void LDD_TDeviceData;          \/*!< Pointer to private device structure managed and used by HAL components. *\/$/;"	t
LDD_TDeviceDataPtr	.\Generated_Code\PE_LDD.h	/^typedef void* LDD_TDeviceDataPtr;      \/*!< Obsolete type for backward compatibility. *\/$/;"	t
LDD_TDriverOperationMode	.\Generated_Code\PE_LDD.h	/^} LDD_TDriverOperationMode;$/;"	t	typeref:enum:__anon4
LDD_TDriverState	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_TDriverState;     \/*!< Driver state type. *\/$/;"	t
LDD_TError	.\Generated_Code\PE_LDD.h	/^typedef uint16_t LDD_TError;           \/*!< Error type. *\/$/;"	t
LDD_TEventMask	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_TEventMask;       \/*!< Event mask type. *\/$/;"	t
LDD_TFlexRAMFunction	.\Generated_Code\PE_LDD.h	/^} LDD_TFlexRAMFunction;$/;"	t	typeref:enum:__anon5
LDD_TIMEDATE_ON_ALARM	.\Generated_Code\PE_LDD.h	265;"	d
LDD_TIMEDATE_ON_SECOND	.\Generated_Code\PE_LDD.h	266;"	d
LDD_TIMERINT_ON_INTERRUPT	.\Generated_Code\PE_LDD.h	193;"	d
LDD_TIMEROUT_ON_INTERRUPT	.\Generated_Code\PE_LDD.h	200;"	d
LDD_TIMERUNIT_ON_CHANNEL_0	.\Generated_Code\PE_LDD.h	149;"	d
LDD_TIMERUNIT_ON_CHANNEL_1	.\Generated_Code\PE_LDD.h	150;"	d
LDD_TIMERUNIT_ON_CHANNEL_2	.\Generated_Code\PE_LDD.h	151;"	d
LDD_TIMERUNIT_ON_CHANNEL_3	.\Generated_Code\PE_LDD.h	152;"	d
LDD_TIMERUNIT_ON_CHANNEL_4	.\Generated_Code\PE_LDD.h	153;"	d
LDD_TIMERUNIT_ON_CHANNEL_5	.\Generated_Code\PE_LDD.h	154;"	d
LDD_TIMERUNIT_ON_CHANNEL_6	.\Generated_Code\PE_LDD.h	155;"	d
LDD_TIMERUNIT_ON_CHANNEL_7	.\Generated_Code\PE_LDD.h	156;"	d
LDD_TIMERUNIT_ON_COUNTER_RESTART	.\Generated_Code\PE_LDD.h	157;"	d
LDD_TPinMask	.\Generated_Code\PE_LDD.h	/^typedef uint32_t LDD_TPinMask;         \/*!< Pin mask type. *\/$/;"	t
LDD_TUserData	.\Generated_Code\PE_LDD.h	/^typedef void LDD_TUserData;            \/*!< Pointer to this type specifies the user or RTOS specific data will be passed as an event or callback parameter. *\/$/;"	t
LDD_TimeDate_TDateRec	.\Generated_Code\PE_LDD.h	/^} LDD_TimeDate_TDateRec;$/;"	t	typeref:struct:__anon10
LDD_TimeDate_TTimeRec	.\Generated_Code\PE_LDD.h	/^} LDD_TimeDate_TTimeRec;$/;"	t	typeref:struct:__anon9
LDD_TimerUnit_TCounterDirection	.\Generated_Code\PE_LDD.h	/^} LDD_TimerUnit_TCounterDirection;$/;"	t	typeref:enum:__anon6
LDD_TimerUnit_TEdge	.\Generated_Code\PE_LDD.h	/^} LDD_TimerUnit_TEdge;$/;"	t	typeref:enum:__anon8
LDD_TimerUnit_TOutAction	.\Generated_Code\PE_LDD.h	/^} LDD_TimerUnit_TOutAction;$/;"	t	typeref:enum:__anon7
LDD_TimerUnit_Tfloat	.\Generated_Code\PE_LDD.h	/^typedef float LDD_TimerUnit_Tfloat;    \/* Float type *\/$/;"	t
LDD_ivIndex_INT_ADC_CC0	.\Generated_Code\PE_LDD.h	1013;"	d
LDD_ivIndex_INT_ADC_CC1	.\Generated_Code\PE_LDD.h	1012;"	d
LDD_ivIndex_INT_ADC_ERR	.\Generated_Code\PE_LDD.h	1014;"	d
LDD_ivIndex_INT_BKPT	.\Generated_Code\PE_LDD.h	990;"	d
LDD_ivIndex_INT_BUS_ERR	.\Generated_Code\PE_LDD.h	994;"	d
LDD_ivIndex_INT_CMPA	.\Generated_Code\PE_LDD.h	1076;"	d
LDD_ivIndex_INT_CMPB	.\Generated_Code\PE_LDD.h	1075;"	d
LDD_ivIndex_INT_CMPC	.\Generated_Code\PE_LDD.h	1074;"	d
LDD_ivIndex_INT_CMPD	.\Generated_Code\PE_LDD.h	1073;"	d
LDD_ivIndex_INT_COP_INT	.\Generated_Code\PE_LDD.h	1091;"	d
LDD_ivIndex_INT_COP_RESET	.\Generated_Code\PE_LDD.h	984;"	d
LDD_ivIndex_INT_DMA0	.\Generated_Code\PE_LDD.h	1019;"	d
LDD_ivIndex_INT_DMA1	.\Generated_Code\PE_LDD.h	1018;"	d
LDD_ivIndex_INT_DMA2	.\Generated_Code\PE_LDD.h	1017;"	d
LDD_ivIndex_INT_DMA3	.\Generated_Code\PE_LDD.h	1016;"	d
LDD_ivIndex_INT_ERROR	.\Generated_Code\PE_LDD.h	1022;"	d
LDD_ivIndex_INT_EWM_INT	.\Generated_Code\PE_LDD.h	1092;"	d
LDD_ivIndex_INT_FTFA_CC	.\Generated_Code\PE_LDD.h	1072;"	d
LDD_ivIndex_INT_FTFA_RDCOL	.\Generated_Code\PE_LDD.h	1071;"	d
LDD_ivIndex_INT_GPIOA	.\Generated_Code\PE_LDD.h	1090;"	d
LDD_ivIndex_INT_GPIOB	.\Generated_Code\PE_LDD.h	1089;"	d
LDD_ivIndex_INT_GPIOC	.\Generated_Code\PE_LDD.h	1088;"	d
LDD_ivIndex_INT_GPIOD	.\Generated_Code\PE_LDD.h	1087;"	d
LDD_ivIndex_INT_GPIOE	.\Generated_Code\PE_LDD.h	1086;"	d
LDD_ivIndex_INT_GPIOF	.\Generated_Code\PE_LDD.h	1085;"	d
LDD_ivIndex_INT_HW_RESET	.\Generated_Code\PE_LDD.h	983;"	d
LDD_ivIndex_INT_IIC0	.\Generated_Code\PE_LDD.h	1045;"	d
LDD_ivIndex_INT_ILLEGAL_OP	.\Generated_Code\PE_LDD.h	985;"	d
LDD_ivIndex_INT_LVI1	.\Generated_Code\PE_LDD.h	1002;"	d
LDD_ivIndex_INT_MISALIGNED	.\Generated_Code\PE_LDD.h	988;"	d
LDD_ivIndex_INT_OCCS	.\Generated_Code\PE_LDD.h	1003;"	d
LDD_ivIndex_INT_OVERFLOW	.\Generated_Code\PE_LDD.h	987;"	d
LDD_ivIndex_INT_PIT0_ROLLOVR	.\Generated_Code\PE_LDD.h	1078;"	d
LDD_ivIndex_INT_PIT1_ROLLOVR	.\Generated_Code\PE_LDD.h	1077;"	d
LDD_ivIndex_INT_QSCI0_RCV	.\Generated_Code\PE_LDD.h	1035;"	d
LDD_ivIndex_INT_QSCI0_RERR	.\Generated_Code\PE_LDD.h	1034;"	d
LDD_ivIndex_INT_QSCI0_TDRE	.\Generated_Code\PE_LDD.h	1037;"	d
LDD_ivIndex_INT_QSCI0_TIDLE	.\Generated_Code\PE_LDD.h	1036;"	d
LDD_ivIndex_INT_QSCI1_RCV	.\Generated_Code\PE_LDD.h	1031;"	d
LDD_ivIndex_INT_QSCI1_RERR	.\Generated_Code\PE_LDD.h	1030;"	d
LDD_ivIndex_INT_QSCI1_TDRE	.\Generated_Code\PE_LDD.h	1033;"	d
LDD_ivIndex_INT_QSCI1_TIDLE	.\Generated_Code\PE_LDD.h	1032;"	d
LDD_ivIndex_INT_QSPI0_RCV	.\Generated_Code\PE_LDD.h	1043;"	d
LDD_ivIndex_INT_QSPI0_XMIT	.\Generated_Code\PE_LDD.h	1042;"	d
LDD_ivIndex_INT_QSPI1_RCV	.\Generated_Code\PE_LDD.h	1041;"	d
LDD_ivIndex_INT_QSPI1_XMIT	.\Generated_Code\PE_LDD.h	1040;"	d
LDD_ivIndex_INT_RX_REG	.\Generated_Code\PE_LDD.h	993;"	d
LDD_ivIndex_INT_RX_WARN	.\Generated_Code\PE_LDD.h	1024;"	d
LDD_ivIndex_INT_STPCNT	.\Generated_Code\PE_LDD.h	989;"	d
LDD_ivIndex_INT_SWI0	.\Generated_Code\PE_LDD.h	1000;"	d
LDD_ivIndex_INT_SWI1	.\Generated_Code\PE_LDD.h	999;"	d
LDD_ivIndex_INT_SWI2	.\Generated_Code\PE_LDD.h	998;"	d
LDD_ivIndex_INT_SWI3	.\Generated_Code\PE_LDD.h	986;"	d
LDD_ivIndex_INT_SWILP	.\Generated_Code\PE_LDD.h	1093;"	d
LDD_ivIndex_INT_TMRA_0	.\Generated_Code\PE_LDD.h	1011;"	d
LDD_ivIndex_INT_TMRA_1	.\Generated_Code\PE_LDD.h	1010;"	d
LDD_ivIndex_INT_TMRA_2	.\Generated_Code\PE_LDD.h	1009;"	d
LDD_ivIndex_INT_TMRA_3	.\Generated_Code\PE_LDD.h	1008;"	d
LDD_ivIndex_INT_TRBUF	.\Generated_Code\PE_LDD.h	991;"	d
LDD_ivIndex_INT_TX_REG	.\Generated_Code\PE_LDD.h	992;"	d
LDD_ivIndex_INT_TX_WARN	.\Generated_Code\PE_LDD.h	1023;"	d
LDD_ivIndex_INT_WAKEUP	.\Generated_Code\PE_LDD.h	1025;"	d
LDD_ivIndex_INT_XBARA	.\Generated_Code\PE_LDD.h	1001;"	d
LDD_ivIndex_INT_eFlexPWMA_CAP	.\Generated_Code\PE_LDD.h	1063;"	d
LDD_ivIndex_INT_eFlexPWMA_CMP0	.\Generated_Code\PE_LDD.h	1070;"	d
LDD_ivIndex_INT_eFlexPWMA_CMP1	.\Generated_Code\PE_LDD.h	1068;"	d
LDD_ivIndex_INT_eFlexPWMA_CMP2	.\Generated_Code\PE_LDD.h	1066;"	d
LDD_ivIndex_INT_eFlexPWMA_CMP3	.\Generated_Code\PE_LDD.h	1064;"	d
LDD_ivIndex_INT_eFlexPWMA_FAULT	.\Generated_Code\PE_LDD.h	1060;"	d
LDD_ivIndex_INT_eFlexPWMA_RELOAD0	.\Generated_Code\PE_LDD.h	1069;"	d
LDD_ivIndex_INT_eFlexPWMA_RELOAD1	.\Generated_Code\PE_LDD.h	1067;"	d
LDD_ivIndex_INT_eFlexPWMA_RELOAD2	.\Generated_Code\PE_LDD.h	1065;"	d
LDD_ivIndex_INT_eFlexPWMA_RELOAD3	.\Generated_Code\PE_LDD.h	1062;"	d
LDD_ivIndex_INT_eFlexPWMA_RERR	.\Generated_Code\PE_LDD.h	1061;"	d
LDD_ivIndex_INT_reserved100	.\Generated_Code\PE_LDD.h	1083;"	d
LDD_ivIndex_INT_reserved101	.\Generated_Code\PE_LDD.h	1084;"	d
LDD_ivIndex_INT_reserved12	.\Generated_Code\PE_LDD.h	995;"	d
LDD_ivIndex_INT_reserved13	.\Generated_Code\PE_LDD.h	996;"	d
LDD_ivIndex_INT_reserved14	.\Generated_Code\PE_LDD.h	997;"	d
LDD_ivIndex_INT_reserved21	.\Generated_Code\PE_LDD.h	1004;"	d
LDD_ivIndex_INT_reserved22	.\Generated_Code\PE_LDD.h	1005;"	d
LDD_ivIndex_INT_reserved23	.\Generated_Code\PE_LDD.h	1006;"	d
LDD_ivIndex_INT_reserved24	.\Generated_Code\PE_LDD.h	1007;"	d
LDD_ivIndex_INT_reserved32	.\Generated_Code\PE_LDD.h	1015;"	d
LDD_ivIndex_INT_reserved37	.\Generated_Code\PE_LDD.h	1020;"	d
LDD_ivIndex_INT_reserved38	.\Generated_Code\PE_LDD.h	1021;"	d
LDD_ivIndex_INT_reserved43	.\Generated_Code\PE_LDD.h	1026;"	d
LDD_ivIndex_INT_reserved44	.\Generated_Code\PE_LDD.h	1027;"	d
LDD_ivIndex_INT_reserved45	.\Generated_Code\PE_LDD.h	1028;"	d
LDD_ivIndex_INT_reserved46	.\Generated_Code\PE_LDD.h	1029;"	d
LDD_ivIndex_INT_reserved55	.\Generated_Code\PE_LDD.h	1038;"	d
LDD_ivIndex_INT_reserved56	.\Generated_Code\PE_LDD.h	1039;"	d
LDD_ivIndex_INT_reserved61	.\Generated_Code\PE_LDD.h	1044;"	d
LDD_ivIndex_INT_reserved63	.\Generated_Code\PE_LDD.h	1046;"	d
LDD_ivIndex_INT_reserved64	.\Generated_Code\PE_LDD.h	1047;"	d
LDD_ivIndex_INT_reserved65	.\Generated_Code\PE_LDD.h	1048;"	d
LDD_ivIndex_INT_reserved66	.\Generated_Code\PE_LDD.h	1049;"	d
LDD_ivIndex_INT_reserved67	.\Generated_Code\PE_LDD.h	1050;"	d
LDD_ivIndex_INT_reserved68	.\Generated_Code\PE_LDD.h	1051;"	d
LDD_ivIndex_INT_reserved69	.\Generated_Code\PE_LDD.h	1052;"	d
LDD_ivIndex_INT_reserved70	.\Generated_Code\PE_LDD.h	1053;"	d
LDD_ivIndex_INT_reserved71	.\Generated_Code\PE_LDD.h	1054;"	d
LDD_ivIndex_INT_reserved72	.\Generated_Code\PE_LDD.h	1055;"	d
LDD_ivIndex_INT_reserved73	.\Generated_Code\PE_LDD.h	1056;"	d
LDD_ivIndex_INT_reserved74	.\Generated_Code\PE_LDD.h	1057;"	d
LDD_ivIndex_INT_reserved75	.\Generated_Code\PE_LDD.h	1058;"	d
LDD_ivIndex_INT_reserved76	.\Generated_Code\PE_LDD.h	1059;"	d
LDD_ivIndex_INT_reserved96	.\Generated_Code\PE_LDD.h	1079;"	d
LDD_ivIndex_INT_reserved97	.\Generated_Code\PE_LDD.h	1080;"	d
LDD_ivIndex_INT_reserved98	.\Generated_Code\PE_LDD.h	1081;"	d
LDD_ivIndex_INT_reserved99	.\Generated_Code\PE_LDD.h	1082;"	d
LIBS	.\FLASH_SDM\objects.mk	/^LIBS := -l${VALUE}$(MCUToolsBaseDirEnv)\/M56800E\\ Support\/runtime_56800E\/lib\/runtime\\ 56800E\\ smm.lib -l${VALUE}$(MCUToolsBaseDirEnv)\/M56800E\\ Support\/msl\/MSL_C\/DSP_56800E\/lib\/MSL\\ C\\ 56800E\\ smm.lib$/;"	m
LIBS_QUOTED	.\FLASH_SDM\objects.mk	/^LIBS_QUOTED := -l${VALUE}"$(MCUToolsBaseDirEnv)\/M56800E Support\/runtime_56800E\/lib\/runtime 56800E smm.lib" -l${VALUE}"$(MCUToolsBaseDirEnv)\/M56800E Support\/msl\/MSL_C\/DSP_56800E\/lib\/MSL C 56800E smm.lib"/;"	m
LOAD	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t LOAD;                                   \/**< Timer Channel Load Register, array offset: 0x3, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
LOLIM	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t LOLIM[16];                              \/**< ADC Low Limit Registers, array offset: 0x1E, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
LOLIMSTAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t LOLIMSTAT;                              \/**< ADC Low Limit Status Register, offset: 0xB *\/$/;"	m	struct:ADC_MemMap
LOLIMSTAT2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t LOLIMSTAT2;                             \/**< ADC Low Limit Status Register 2, offset: 0x5C *\/$/;"	m	struct:ADC_MemMap
LOLIM_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t LOLIM_2[4];                             \/**< ADC Low Limit Registers 2, array offset: 0x63, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
LOOPMODE_AUTO_ECHO	.\Generated_Code\PE_LDD.h	/^  LOOPMODE_AUTO_ECHO,$/;"	e	enum:__anon20
LOOPMODE_LOCAL_LOOPBACK	.\Generated_Code\PE_LDD.h	/^  LOOPMODE_LOCAL_LOOPBACK,$/;"	e	enum:__anon20
LOOPMODE_NORMAL	.\Generated_Code\PE_LDD.h	/^  LOOPMODE_NORMAL,$/;"	e	enum:__anon20
LOOPMODE_REMOTE_LOOPBACK	.\Generated_Code\PE_LDD.h	/^  LOOPMODE_REMOTE_LOOPBACK$/;"	e	enum:__anon20
LOOPMODE_UNDEF	.\Generated_Code\PE_LDD.h	/^  LOOPMODE_UNDEF,$/;"	e	enum:__anon20
LOW_SPEED	.\Static_Code\System\PE_Const.h	11;"	d
LSBpart	.\Static_Code\System\PE_Types.h	/^          UWord16 LSBpart;$/;"	m	struct:__anon67::__anon68
LSHID	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t LSHID;                                  \/**< Least Significant Half of JTAG ID, offset: 0x7 *\/$/;"	m	struct:SIM_MemMap
Lck0ChckCnt	.\Static_Code\System\CPU_Init.c	/^static uint32_t Lck0ChckCnt;               \/* LCK0 check counter *\/$/;"	v	file:
Length	.\Generated_Code\PE_LDD.h	/^  uint8_t  Length;                     \/* Message length *\/$/;"	m	struct:__anon41
LocPriority	.\Generated_Code\PE_LDD.h	/^  uint8_t  LocPriority;                \/* Local Priority Tx Buffers *\/$/;"	m	struct:__anon41
LowLimitValue	.\Generated_Code\PE_LDD.h	/^  uint16_t LowLimitValue;              \/*!< Low limit value *\/$/;"	m	struct:__anon44
M01	.\Static_Code\System\CPU_Init.h	/^    int16_t M01;                       \/* Shadow register M01. *\/$/;"	m	struct:__anon63
MASK	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MASK;                                   \/**< Mask Register, offset: 0xC1 *\/$/;"	m	struct:PWM_MemMap
MAXVAL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t MAXVAL;                                 \/**< Maximum Value Register, offset: 0x4 *\/$/;"	m	union:DAC_MemMap::__anon55
MAXVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t MAXVAL_FMT1;                            \/**< Maximum Value Register, offset: 0x4 *\/$/;"	m	union:DAC_MemMap::__anon55
MCM_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	3886;"	d
MCM_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	3888;"	d
MCM_CFADR	.\Static_Code\IO_Map\MC56F82748.h	3905;"	d
MCM_CFADR_ADDR	.\Static_Code\IO_Map\MC56F82748.h	3824;"	d
MCM_CFADR_ADDR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3822;"	d
MCM_CFADR_ADDR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3823;"	d
MCM_CFADR_REG	.\Static_Code\IO_Map\MC56F82748.h	3773;"	d
MCM_CFATR	.\Static_Code\IO_Map\MC56F82748.h	3906;"	d
MCM_CFATR_BUFFER_MASK	.\Static_Code\IO_Map\MC56F82748.h	3828;"	d
MCM_CFATR_BUFFER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3829;"	d
MCM_CFATR_DIR_MASK	.\Static_Code\IO_Map\MC56F82748.h	3833;"	d
MCM_CFATR_DIR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3834;"	d
MCM_CFATR_REG	.\Static_Code\IO_Map\MC56F82748.h	3774;"	d
MCM_CFATR_SIZE	.\Static_Code\IO_Map\MC56F82748.h	3832;"	d
MCM_CFATR_SIZE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3830;"	d
MCM_CFATR_SIZE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3831;"	d
MCM_CFATR_TYPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3826;"	d
MCM_CFATR_TYPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3827;"	d
MCM_CFDTR	.\Static_Code\IO_Map\MC56F82748.h	3910;"	d
MCM_CFDTR_DATA	.\Static_Code\IO_Map\MC56F82748.h	3848;"	d
MCM_CFDTR_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3846;"	d
MCM_CFDTR_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3847;"	d
MCM_CFDTR_REG	.\Static_Code\IO_Map\MC56F82748.h	3778;"	d
MCM_CFIER	.\Static_Code\IO_Map\MC56F82748.h	3908;"	d
MCM_CFIER_ECFEI_MASK	.\Static_Code\IO_Map\MC56F82748.h	3840;"	d
MCM_CFIER_ECFEI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3841;"	d
MCM_CFIER_REG	.\Static_Code\IO_Map\MC56F82748.h	3776;"	d
MCM_CFISR	.\Static_Code\IO_Map\MC56F82748.h	3909;"	d
MCM_CFISR_CFEI_MASK	.\Static_Code\IO_Map\MC56F82748.h	3843;"	d
MCM_CFISR_CFEI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3844;"	d
MCM_CFISR_REG	.\Static_Code\IO_Map\MC56F82748.h	3777;"	d
MCM_CFLOC	.\Static_Code\IO_Map\MC56F82748.h	3907;"	d
MCM_CFLOC_LOC	.\Static_Code\IO_Map\MC56F82748.h	3838;"	d
MCM_CFLOC_LOC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3836;"	d
MCM_CFLOC_LOC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3837;"	d
MCM_CFLOC_REG	.\Static_Code\IO_Map\MC56F82748.h	3775;"	d
MCM_CPCR	.\Static_Code\IO_Map\MC56F82748.h	3904;"	d
MCM_CPCR_FCSDIS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3819;"	d
MCM_CPCR_FCSDIS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3820;"	d
MCM_CPCR_IBDIS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3817;"	d
MCM_CPCR_IBDIS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3818;"	d
MCM_CPCR_INSDIS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3811;"	d
MCM_CPCR_INSDIS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3812;"	d
MCM_CPCR_RCDIS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3813;"	d
MCM_CPCR_RCDIS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3814;"	d
MCM_CPCR_REG	.\Static_Code\IO_Map\MC56F82748.h	3772;"	d
MCM_CPCR_SRDIS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3815;"	d
MCM_CPCR_SRDIS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3816;"	d
MCM_Init	.\Static_Code\Peripherals\MCM_Init.c	/^void MCM_Init(void) {$/;"	f
MCM_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct MCM_MemMap {$/;"	s
MCM_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *MCM_MemMapPtr;$/;"	t
MCM_PDD_32_BIT	.\Static_Code\PDD\MCM_PDD.h	67;"	d
MCM_PDD_64_BIT	.\Static_Code\PDD\MCM_PDD.h	68;"	d
MCM_PDD_CORE_FAULT_FLAG	.\Static_Code\PDD\MCM_PDD.h	44;"	d
MCM_PDD_CORE_FAULT_INTERRUPT	.\Static_Code\PDD\MCM_PDD.h	41;"	d
MCM_PDD_ClearCoreFaultFlag	.\Static_Code\PDD\MCM_PDD.h	644;"	d
MCM_PDD_ClearInterruptFlags	.\Static_Code\PDD\MCM_PDD.h	165;"	d
MCM_PDD_ClearResourceProtectionIllegalFlag	.\Static_Code\PDD\MCM_PDD.h	913;"	d
MCM_PDD_ClearResourceProtectionMisalignedFlag	.\Static_Code\PDD\MCM_PDD.h	968;"	d
MCM_PDD_DisableInterrupts	.\Static_Code\PDD\MCM_PDD.h	127;"	d
MCM_PDD_Enable56800EXInstructions	.\Static_Code\PDD\MCM_PDD.h	427;"	d
MCM_PDD_EnableCoreCoreReverseCarry	.\Static_Code\PDD\MCM_PDD.h	381;"	d
MCM_PDD_EnableCoreFaultInterrupt	.\Static_Code\PDD\MCM_PDD.h	586;"	d
MCM_PDD_EnableCoreInstructionBuffer	.\Static_Code\PDD\MCM_PDD.h	289;"	d
MCM_PDD_EnableCoreNewShadowRegion	.\Static_Code\PDD\MCM_PDD.h	335;"	d
MCM_PDD_EnableFlashMemoryControllerStall	.\Static_Code\PDD\MCM_PDD.h	243;"	d
MCM_PDD_EnableInterrupts	.\Static_Code\PDD\MCM_PDD.h	108;"	d
MCM_PDD_EnableResourceProtection	.\Static_Code\PDD\MCM_PDD.h	729;"	d
MCM_PDD_EnableResourceProtectionLock	.\Static_Code\PDD\MCM_PDD.h	685;"	d
MCM_PDD_FAULT_16_BIT	.\Static_Code\PDD\MCM_PDD.h	76;"	d
MCM_PDD_FAULT_32_BIT	.\Static_Code\PDD\MCM_PDD.h	77;"	d
MCM_PDD_FAULT_8_BIT	.\Static_Code\PDD\MCM_PDD.h	75;"	d
MCM_PDD_FAULT_BUFFERABLE	.\Static_Code\PDD\MCM_PDD.h	81;"	d
MCM_PDD_FAULT_DATA	.\Static_Code\PDD\MCM_PDD.h	85;"	d
MCM_PDD_FAULT_INSTRUCTION	.\Static_Code\PDD\MCM_PDD.h	84;"	d
MCM_PDD_FAULT_INSTRUCTION_BUS	.\Static_Code\PDD\MCM_PDD.h	88;"	d
MCM_PDD_FAULT_NON_BUFFERABLE	.\Static_Code\PDD\MCM_PDD.h	80;"	d
MCM_PDD_FAULT_OPERAND_A_BUS	.\Static_Code\PDD\MCM_PDD.h	89;"	d
MCM_PDD_FAULT_OPERAND_B_BUS	.\Static_Code\PDD\MCM_PDD.h	90;"	d
MCM_PDD_FAULT_READ	.\Static_Code\PDD\MCM_PDD.h	71;"	d
MCM_PDD_FAULT_WRITE	.\Static_Code\PDD\MCM_PDD.h	72;"	d
MCM_PDD_Get56800EXInstructionsEnabled	.\Static_Code\PDD\MCM_PDD.h	449;"	d
MCM_PDD_GetBusMasterConnectedMask	.\Static_Code\PDD\MCM_PDD.h	221;"	d
MCM_PDD_GetBusSlaveConnectedMask	.\Static_Code\PDD\MCM_PDD.h	202;"	d
MCM_PDD_GetCoreCoreReverseCarryEnabled	.\Static_Code\PDD\MCM_PDD.h	403;"	d
MCM_PDD_GetCoreFaultAddress	.\Static_Code\PDD\MCM_PDD.h	470;"	d
MCM_PDD_GetCoreFaultBuffer	.\Static_Code\PDD\MCM_PDD.h	527;"	d
MCM_PDD_GetCoreFaultData	.\Static_Code\PDD\MCM_PDD.h	663;"	d
MCM_PDD_GetCoreFaultDirection	.\Static_Code\PDD\MCM_PDD.h	489;"	d
MCM_PDD_GetCoreFaultFlag	.\Static_Code\PDD\MCM_PDD.h	626;"	d
MCM_PDD_GetCoreFaultInterruptEnabled	.\Static_Code\PDD\MCM_PDD.h	608;"	d
MCM_PDD_GetCoreFaultLocation	.\Static_Code\PDD\MCM_PDD.h	564;"	d
MCM_PDD_GetCoreFaultSize	.\Static_Code\PDD\MCM_PDD.h	507;"	d
MCM_PDD_GetCoreFaultType	.\Static_Code\PDD\MCM_PDD.h	546;"	d
MCM_PDD_GetCoreInstructionBufferEnabled	.\Static_Code\PDD\MCM_PDD.h	311;"	d
MCM_PDD_GetCoreNewShadowRegionEnabled	.\Static_Code\PDD\MCM_PDD.h	357;"	d
MCM_PDD_GetDatapathWidth	.\Static_Code\PDD\MCM_PDD.h	183;"	d
MCM_PDD_GetFlashMemoryControllerStallEnabled	.\Static_Code\PDD\MCM_PDD.h	265;"	d
MCM_PDD_GetInterruptFlags	.\Static_Code\PDD\MCM_PDD.h	145;"	d
MCM_PDD_GetOtherStackPointer	.\Static_Code\PDD\MCM_PDD.h	877;"	d
MCM_PDD_GetResourceProtectionEnabled	.\Static_Code\PDD\MCM_PDD.h	751;"	d
MCM_PDD_GetResourceProtectionIllegalFlag	.\Static_Code\PDD\MCM_PDD.h	895;"	d
MCM_PDD_GetResourceProtectionIllegalProgramCounter	.\Static_Code\PDD\MCM_PDD.h	932;"	d
MCM_PDD_GetResourceProtectionLockEnabled	.\Static_Code\PDD\MCM_PDD.h	707;"	d
MCM_PDD_GetResourceProtectionMisalignedFlag	.\Static_Code\PDD\MCM_PDD.h	950;"	d
MCM_PDD_GetResourceProtectionMisalignedProgramCounter	.\Static_Code\PDD\MCM_PDD.h	987;"	d
MCM_PDD_GetUserFlashBaseAddress	.\Static_Code\PDD\MCM_PDD.h	792;"	d
MCM_PDD_GetUserProgramRamBaseAddress	.\Static_Code\PDD\MCM_PDD.h	835;"	d
MCM_PDD_H_	.\Static_Code\PDD\MCM_PDD.h	9;"	d
MCM_PDD_MASTER_0	.\Static_Code\PDD\MCM_PDD.h	57;"	d
MCM_PDD_MASTER_1	.\Static_Code\PDD\MCM_PDD.h	58;"	d
MCM_PDD_MASTER_2	.\Static_Code\PDD\MCM_PDD.h	59;"	d
MCM_PDD_MASTER_3	.\Static_Code\PDD\MCM_PDD.h	60;"	d
MCM_PDD_MASTER_4	.\Static_Code\PDD\MCM_PDD.h	61;"	d
MCM_PDD_MASTER_5	.\Static_Code\PDD\MCM_PDD.h	62;"	d
MCM_PDD_MASTER_6	.\Static_Code\PDD\MCM_PDD.h	63;"	d
MCM_PDD_MASTER_7	.\Static_Code\PDD\MCM_PDD.h	64;"	d
MCM_PDD_ReadAxbsMasterConfigurationReg	.\Static_Code\PDD\MCM_PDD.h	1025;"	d
MCM_PDD_ReadAxbsSlaveConfigurationReg	.\Static_Code\PDD\MCM_PDD.h	1006;"	d
MCM_PDD_ReadCoreControlReg	.\Static_Code\PDD\MCM_PDD.h	1063;"	d
MCM_PDD_ReadCoreFaultAddressReg	.\Static_Code\PDD\MCM_PDD.h	1081;"	d
MCM_PDD_ReadCoreFaultAttributesReg	.\Static_Code\PDD\MCM_PDD.h	1099;"	d
MCM_PDD_ReadCoreFaultDataReg	.\Static_Code\PDD\MCM_PDD.h	1211;"	d
MCM_PDD_ReadCoreFaultInterruptEnableReg	.\Static_Code\PDD\MCM_PDD.h	1155;"	d
MCM_PDD_ReadCoreFaultInterruptStatusReg	.\Static_Code\PDD\MCM_PDD.h	1193;"	d
MCM_PDD_ReadCoreFaultLocationReg	.\Static_Code\PDD\MCM_PDD.h	1117;"	d
MCM_PDD_ReadMemoryProtectionIllegalPcReg	.\Static_Code\PDD\MCM_PDD.h	1403;"	d
MCM_PDD_ReadResourceProtectionControlReg	.\Static_Code\PDD\MCM_PDD.h	1249;"	d
MCM_PDD_ReadResourceProtectionMisalignedPcReg	.\Static_Code\PDD\MCM_PDD.h	1442;"	d
MCM_PDD_ReadResourceProtectionOtherStackPointerReg	.\Static_Code\PDD\MCM_PDD.h	1365;"	d
MCM_PDD_ReadUserFlashBaseAddressReg	.\Static_Code\PDD\MCM_PDD.h	1287;"	d
MCM_PDD_ReadUserProgramRamBaseAddressReg	.\Static_Code\PDD\MCM_PDD.h	1325;"	d
MCM_PDD_SLAVE_0	.\Static_Code\PDD\MCM_PDD.h	47;"	d
MCM_PDD_SLAVE_1	.\Static_Code\PDD\MCM_PDD.h	48;"	d
MCM_PDD_SLAVE_2	.\Static_Code\PDD\MCM_PDD.h	49;"	d
MCM_PDD_SLAVE_3	.\Static_Code\PDD\MCM_PDD.h	50;"	d
MCM_PDD_SLAVE_4	.\Static_Code\PDD\MCM_PDD.h	51;"	d
MCM_PDD_SLAVE_5	.\Static_Code\PDD\MCM_PDD.h	52;"	d
MCM_PDD_SLAVE_6	.\Static_Code\PDD\MCM_PDD.h	53;"	d
MCM_PDD_SLAVE_7	.\Static_Code\PDD\MCM_PDD.h	54;"	d
MCM_PDD_SetOtherStackPointer	.\Static_Code\PDD\MCM_PDD.h	855;"	d
MCM_PDD_SetUserFlashBaseAddress	.\Static_Code\PDD\MCM_PDD.h	771;"	d
MCM_PDD_SetUserProgramRamBaseAddress	.\Static_Code\PDD\MCM_PDD.h	813;"	d
MCM_PDD_WriteCoreControlReg	.\Static_Code\PDD\MCM_PDD.h	1045;"	d
MCM_PDD_WriteCoreFaultInterruptEnableReg	.\Static_Code\PDD\MCM_PDD.h	1137;"	d
MCM_PDD_WriteCoreFaultInterruptStatusReg	.\Static_Code\PDD\MCM_PDD.h	1175;"	d
MCM_PDD_WriteMemoryProtectionIllegalPcReg	.\Static_Code\PDD\MCM_PDD.h	1385;"	d
MCM_PDD_WriteResourceProtectionControlReg	.\Static_Code\PDD\MCM_PDD.h	1231;"	d
MCM_PDD_WriteResourceProtectionMisalignedPcReg	.\Static_Code\PDD\MCM_PDD.h	1423;"	d
MCM_PDD_WriteResourceProtectionOtherStackPointerReg	.\Static_Code\PDD\MCM_PDD.h	1345;"	d
MCM_PDD_WriteUserFlashBaseAddressReg	.\Static_Code\PDD\MCM_PDD.h	1269;"	d
MCM_PDD_WriteUserProgramRamBaseAddressReg	.\Static_Code\PDD\MCM_PDD.h	1307;"	d
MCM_PLAMC	.\Static_Code\IO_Map\MC56F82748.h	3903;"	d
MCM_PLAMC_AMC	.\Static_Code\IO_Map\MC56F82748.h	3809;"	d
MCM_PLAMC_AMC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3807;"	d
MCM_PLAMC_AMC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3808;"	d
MCM_PLAMC_REG	.\Static_Code\IO_Map\MC56F82748.h	3771;"	d
MCM_PLASC	.\Static_Code\IO_Map\MC56F82748.h	3902;"	d
MCM_PLASC_ASC	.\Static_Code\IO_Map\MC56F82748.h	3803;"	d
MCM_PLASC_ASC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3801;"	d
MCM_PLASC_ASC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3802;"	d
MCM_PLASC_DP64_MASK	.\Static_Code\IO_Map\MC56F82748.h	3804;"	d
MCM_PLASC_DP64_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3805;"	d
MCM_PLASC_REG	.\Static_Code\IO_Map\MC56F82748.h	3770;"	d
MCM_RPCR	.\Static_Code\IO_Map\MC56F82748.h	3911;"	d
MCM_RPCR_REG	.\Static_Code\IO_Map\MC56F82748.h	3779;"	d
MCM_RPCR_RL_MASK	.\Static_Code\IO_Map\MC56F82748.h	3852;"	d
MCM_RPCR_RL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3853;"	d
MCM_RPCR_RPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3850;"	d
MCM_RPCR_RPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3851;"	d
MCM_SRPIPC	.\Static_Code\IO_Map\MC56F82748.h	3915;"	d
MCM_SRPIPC_REG	.\Static_Code\IO_Map\MC56F82748.h	3783;"	d
MCM_SRPIPC_SRPIFPC	.\Static_Code\IO_Map\MC56F82748.h	3869;"	d
MCM_SRPIPC_SRPIFPC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3867;"	d
MCM_SRPIPC_SRPIFPC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3868;"	d
MCM_SRPIPC_SRPIFV_MASK	.\Static_Code\IO_Map\MC56F82748.h	3870;"	d
MCM_SRPIPC_SRPIFV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3871;"	d
MCM_SRPMPC	.\Static_Code\IO_Map\MC56F82748.h	3916;"	d
MCM_SRPMPC_REG	.\Static_Code\IO_Map\MC56F82748.h	3784;"	d
MCM_SRPMPC_SRPMFPC	.\Static_Code\IO_Map\MC56F82748.h	3875;"	d
MCM_SRPMPC_SRPMFPC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3873;"	d
MCM_SRPMPC_SRPMFPC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3874;"	d
MCM_SRPMPC_SRPMFV_MASK	.\Static_Code\IO_Map\MC56F82748.h	3876;"	d
MCM_SRPMPC_SRPMFV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3877;"	d
MCM_SRPOSP	.\Static_Code\IO_Map\MC56F82748.h	3914;"	d
MCM_SRPOSP_REG	.\Static_Code\IO_Map\MC56F82748.h	3782;"	d
MCM_SRPOSP_SRPOSP	.\Static_Code\IO_Map\MC56F82748.h	3865;"	d
MCM_SRPOSP_SRPOSP_MASK	.\Static_Code\IO_Map\MC56F82748.h	3863;"	d
MCM_SRPOSP_SRPOSP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3864;"	d
MCM_UFLASHBAR	.\Static_Code\IO_Map\MC56F82748.h	3912;"	d
MCM_UFLASHBAR_FBA	.\Static_Code\IO_Map\MC56F82748.h	3857;"	d
MCM_UFLASHBAR_FBA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3855;"	d
MCM_UFLASHBAR_FBA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3856;"	d
MCM_UFLASHBAR_REG	.\Static_Code\IO_Map\MC56F82748.h	3780;"	d
MCM_UPRAMBAR	.\Static_Code\IO_Map\MC56F82748.h	3913;"	d
MCM_UPRAMBAR_RBA	.\Static_Code\IO_Map\MC56F82748.h	3861;"	d
MCM_UPRAMBAR_RBA_MASK	.\Static_Code\IO_Map\MC56F82748.h	3859;"	d
MCM_UPRAMBAR_RBA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3860;"	d
MCM_UPRAMBAR_REG	.\Static_Code\IO_Map\MC56F82748.h	3781;"	d
MCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MCTRL;                                  \/**< Master Control Register, offset: 0xC4 *\/$/;"	m	struct:PWM_MemMap
MCTRL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MCTRL2;                                 \/**< Master Control 2 Register, offset: 0xC5 *\/$/;"	m	struct:PWM_MemMap
MCU_ACTIVE	.\Static_Code\IO_Map\MC56F82748.h	48;"	d
MCU_MC56F82748	.\Static_Code\IO_Map\MC56F82748.h	42;"	d
MCU_MEM_MAP_VERSION	.\Static_Code\IO_Map\MC56F82748.h	54;"	d
MCU_MEM_MAP_VERSION_MINOR	.\Static_Code\IO_Map\MC56F82748.h	56;"	d
MC_PWM_ALL_SIGNALS	.\Static_Code\System\PE_Types.h	847;"	d
MC_PWM_NO_SIGNALS	.\Static_Code\System\PE_Types.h	846;"	d
MC_PWM_SIGNAL_0	.\Static_Code\System\PE_Types.h	840;"	d
MC_PWM_SIGNAL_1	.\Static_Code\System\PE_Types.h	841;"	d
MC_PWM_SIGNAL_2	.\Static_Code\System\PE_Types.h	842;"	d
MC_PWM_SIGNAL_3	.\Static_Code\System\PE_Types.h	843;"	d
MC_PWM_SIGNAL_4	.\Static_Code\System\PE_Types.h	844;"	d
MC_PWM_SIGNAL_5	.\Static_Code\System\PE_Types.h	845;"	d
MINVAL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t MINVAL;                                 \/**< Minimum Value Register, offset: 0x3 *\/$/;"	m	union:DAC_MemMap::__anon54
MINVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t MINVAL_FMT1;                            \/**< Minimum Value Register, offset: 0x3 *\/$/;"	m	union:DAC_MemMap::__anon54
MISC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MISC;                                   \/**< MSCAN Miscellaneous Register, offset: 0xD *\/$/;"	m	struct:CAN_MemMap
MISC0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MISC0;                                  \/**< Miscellaneous Register 0, offset: 0x23 *\/$/;"	m	struct:SIM_MemMap
MOD	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MOD;                                    \/**< PIT Modulo Register, offset: 0x1 *\/$/;"	m	struct:PIT_MemMap
MSBpart	.\Static_Code\System\PE_Types.h	/^          Word16 MSBpart;$/;"	m	struct:__anon67::__anon68
MSCAN_PDD_H_	.\Static_Code\PDD\MSCAN_PDD.h	9;"	d
MSHID	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MSHID;                                  \/**< Most Significant Half of JTAG ID, offset: 0x6 *\/$/;"	m	struct:SIM_MemMap
MUXCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t MUXCR;                                  \/**< MUX Control Register, offset: 0x5 *\/$/;"	m	struct:CMP_MemMap
MasterNacks	.\Generated_Code\PE_LDD.h	/^  uint32_t MasterNacks;                \/* Number of no acknowledges. *\/$/;"	m	struct:__anon25
MasterReceivedChars	.\Generated_Code\PE_LDD.h	/^  uint32_t MasterReceivedChars;        \/* Number of master received characters. *\/$/;"	m	struct:__anon25
MasterSentChars	.\Generated_Code\PE_LDD.h	/^  uint32_t MasterSentChars;            \/* Number of master transmitted characters. *\/$/;"	m	struct:__anon25
MessageID	.\Generated_Code\PE_LDD.h	/^  LDD_CAN_TMessageID MessageID;        \/* Message ID *\/$/;"	m	struct:__anon41
Min	.\Generated_Code\PE_LDD.h	/^  uint16_t Min;                        \/* Minutes (0 - 59) *\/$/;"	m	struct:__anon9
Month	.\Generated_Code\PE_LDD.h	/^  uint16_t Month;                      \/* Months (1 - 12) *\/$/;"	m	struct:__anon10
N	.\Static_Code\System\CPU_Init.h	/^    int32_t N;                         \/* Shadow register N. *\/$/;"	m	struct:__anon63
N3	.\Static_Code\System\CPU_Init.h	/^    int16_t N3;                        \/* Shadow register N3. *\/$/;"	m	struct:__anon63
NL_MODE	.\Project_Settings\Startup_Code\56F83x_init.asm	/^NL_MODE                                                          EQU  $8000$/;"	d
NULL	.\Static_Code\System\PE_Types.h	24;"	d
NUMBER_OF_PLL_CHECKS	.\Generated_Code\CPU_Config.h	172;"	d
NVMOPT2H	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t NVMOPT2H;                               \/**< Non-Volatile Memory Option Register 2 (High), offset: 0x2C *\/$/;"	m	struct:SIM_MemMap
NVMOPT2L	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t NVMOPT2L;                               \/**< Non-Volatile Memory Option Register 2 (Low), offset: 0x2D *\/$/;"	m	struct:SIM_MemMap
NegativePIDLimit	.\Static_Code\System\PE_Types.h	/^   Word16 NegativePIDLimit;$/;"	m	struct:__anon82
NegativePILimit	.\Static_Code\System\PE_Types.h	/^   Word16 NegativePILimit;$/;"	m	struct:__anon83
NoiseErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t NoiseErrors;                \/* Number of receiver noise errors *\/$/;"	m	struct:__anon19
OBJS	.\FLASH_SDM\sources.mk	/^OBJS := $/;"	m
OBJS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^OBJS_OS_FORMAT := $/;"	m
OBJS_QUOTED	.\FLASH_SDM\sources.mk	/^OBJS_QUOTED := $/;"	m
OBJ_SRCS	.\FLASH_SDM\sources.mk	/^OBJ_SRCS := $/;"	m
OBJ_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^OBJ_SRCS_OS_FORMAT := $/;"	m
OBJ_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^OBJ_SRCS_QUOTED := $/;"	m
OCCS_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	4089;"	d
OCCS_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	4091;"	d
OCCS_CLKCHKR	.\Static_Code\IO_Map\MC56F82748.h	4110;"	d
OCCS_CLKCHKR_CHK_ENA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4065;"	d
OCCS_CLKCHKR_CHK_ENA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4066;"	d
OCCS_CLKCHKR_REF_CNT	.\Static_Code\IO_Map\MC56F82748.h	4064;"	d
OCCS_CLKCHKR_REF_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4062;"	d
OCCS_CLKCHKR_REF_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4063;"	d
OCCS_CLKCHKR_REG	.\Static_Code\IO_Map\MC56F82748.h	3966;"	d
OCCS_CLKCHKT	.\Static_Code\IO_Map\MC56F82748.h	4111;"	d
OCCS_CLKCHKT_REG	.\Static_Code\IO_Map\MC56F82748.h	3967;"	d
OCCS_CLKCHKT_TARGET_CNT	.\Static_Code\IO_Map\MC56F82748.h	4070;"	d
OCCS_CLKCHKT_TARGET_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4068;"	d
OCCS_CLKCHKT_TARGET_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4069;"	d
OCCS_CTRL	.\Static_Code\IO_Map\MC56F82748.h	4105;"	d
OCCS_CTRL_LCKON_MASK	.\Static_Code\IO_Map\MC56F82748.h	3992;"	d
OCCS_CTRL_LCKON_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3993;"	d
OCCS_CTRL_LOCIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	3994;"	d
OCCS_CTRL_LOCIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3995;"	d
OCCS_CTRL_PLLIE0	.\Static_Code\IO_Map\MC56F82748.h	3998;"	d
OCCS_CTRL_PLLIE0_MASK	.\Static_Code\IO_Map\MC56F82748.h	3996;"	d
OCCS_CTRL_PLLIE0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3997;"	d
OCCS_CTRL_PLLIE1	.\Static_Code\IO_Map\MC56F82748.h	4001;"	d
OCCS_CTRL_PLLIE1_MASK	.\Static_Code\IO_Map\MC56F82748.h	3999;"	d
OCCS_CTRL_PLLIE1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4000;"	d
OCCS_CTRL_PLLPD_MASK	.\Static_Code\IO_Map\MC56F82748.h	3990;"	d
OCCS_CTRL_PLLPD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3991;"	d
OCCS_CTRL_PRECS	.\Static_Code\IO_Map\MC56F82748.h	3989;"	d
OCCS_CTRL_PRECS_MASK	.\Static_Code\IO_Map\MC56F82748.h	3987;"	d
OCCS_CTRL_PRECS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3988;"	d
OCCS_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	3961;"	d
OCCS_CTRL_ZSRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	3985;"	d
OCCS_CTRL_ZSRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	3986;"	d
OCCS_DIVBY	.\Static_Code\IO_Map\MC56F82748.h	4106;"	d
OCCS_DIVBY_COD	.\Static_Code\IO_Map\MC56F82748.h	4010;"	d
OCCS_DIVBY_COD_MASK	.\Static_Code\IO_Map\MC56F82748.h	4008;"	d
OCCS_DIVBY_COD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4009;"	d
OCCS_DIVBY_LORTP	.\Static_Code\IO_Map\MC56F82748.h	4013;"	d
OCCS_DIVBY_LORTP_MASK	.\Static_Code\IO_Map\MC56F82748.h	4011;"	d
OCCS_DIVBY_LORTP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4012;"	d
OCCS_DIVBY_PLLDB	.\Static_Code\IO_Map\MC56F82748.h	4005;"	d
OCCS_DIVBY_PLLDB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4003;"	d
OCCS_DIVBY_PLLDB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4004;"	d
OCCS_DIVBY_PWM_DIV2_MASK	.\Static_Code\IO_Map\MC56F82748.h	4006;"	d
OCCS_DIVBY_PWM_DIV2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4007;"	d
OCCS_DIVBY_REG	.\Static_Code\IO_Map\MC56F82748.h	3962;"	d
OCCS_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct OCCS_MemMap {$/;"	s
OCCS_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *OCCS_MemMapPtr;$/;"	t
OCCS_OSCTL1	.\Static_Code\IO_Map\MC56F82748.h	4108;"	d
OCCS_OSCTL1_CLK_MODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4040;"	d
OCCS_OSCTL1_CLK_MODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4041;"	d
OCCS_OSCTL1_COHL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4042;"	d
OCCS_OSCTL1_COHL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4043;"	d
OCCS_OSCTL1_EXT_SEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4038;"	d
OCCS_OSCTL1_EXT_SEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4039;"	d
OCCS_OSCTL1_FREQ_TRIM8M	.\Static_Code\IO_Map\MC56F82748.h	4037;"	d
OCCS_OSCTL1_FREQ_TRIM8M_MASK	.\Static_Code\IO_Map\MC56F82748.h	4035;"	d
OCCS_OSCTL1_FREQ_TRIM8M_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4036;"	d
OCCS_OSCTL1_REG	.\Static_Code\IO_Map\MC56F82748.h	3964;"	d
OCCS_OSCTL1_ROPD_MASK	.\Static_Code\IO_Map\MC56F82748.h	4046;"	d
OCCS_OSCTL1_ROPD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4047;"	d
OCCS_OSCTL1_ROSB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4044;"	d
OCCS_OSCTL1_ROSB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4045;"	d
OCCS_OSCTL2	.\Static_Code\IO_Map\MC56F82748.h	4109;"	d
OCCS_OSCTL2_COPD_MASK	.\Static_Code\IO_Map\MC56F82748.h	4057;"	d
OCCS_OSCTL2_COPD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4058;"	d
OCCS_OSCTL2_FREQ_TRIM200K	.\Static_Code\IO_Map\MC56F82748.h	4051;"	d
OCCS_OSCTL2_FREQ_TRIM200K_MASK	.\Static_Code\IO_Map\MC56F82748.h	4049;"	d
OCCS_OSCTL2_FREQ_TRIM200K_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4050;"	d
OCCS_OSCTL2_MON_ENABLE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4052;"	d
OCCS_OSCTL2_MON_ENABLE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4053;"	d
OCCS_OSCTL2_REG	.\Static_Code\IO_Map\MC56F82748.h	3965;"	d
OCCS_OSCTL2_ROPD200K_MASK	.\Static_Code\IO_Map\MC56F82748.h	4059;"	d
OCCS_OSCTL2_ROPD200K_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4060;"	d
OCCS_OSCTL2_TEMP_TRIM8M	.\Static_Code\IO_Map\MC56F82748.h	4056;"	d
OCCS_OSCTL2_TEMP_TRIM8M_MASK	.\Static_Code\IO_Map\MC56F82748.h	4054;"	d
OCCS_OSCTL2_TEMP_TRIM8M_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4055;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_1	.\Static_Code\PDD\OCCS_PDD.h	50;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_128	.\Static_Code\PDD\OCCS_PDD.h	57;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_16	.\Static_Code\PDD\OCCS_PDD.h	54;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_2	.\Static_Code\PDD\OCCS_PDD.h	51;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_256	.\Static_Code\PDD\OCCS_PDD.h	58;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_32	.\Static_Code\PDD\OCCS_PDD.h	55;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_4	.\Static_Code\PDD\OCCS_PDD.h	52;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_64	.\Static_Code\PDD\OCCS_PDD.h	56;"	d
OCCS_PDD_CLOCK_OUTPUT_DIVIDER_8	.\Static_Code\PDD\OCCS_PDD.h	53;"	d
OCCS_PDD_CLOCK_SOURCE_MASTER_OSCILLATOR	.\Static_Code\PDD\OCCS_PDD.h	46;"	d
OCCS_PDD_CLOCK_SOURCE_PLL_DIV2	.\Static_Code\PDD\OCCS_PDD.h	47;"	d
OCCS_PDD_ClearInterruptFlags	.\Static_Code\PDD\OCCS_PDD.h	145;"	d
OCCS_PDD_DisableLossOfReferenceClockInterrupt	.\Static_Code\PDD\OCCS_PDD.h	271;"	d
OCCS_PDD_EDGE_BOTH	.\Static_Code\PDD\OCCS_PDD.h	94;"	d
OCCS_PDD_EDGE_FALLING	.\Static_Code\PDD\OCCS_PDD.h	93;"	d
OCCS_PDD_EDGE_NONE	.\Static_Code\PDD\OCCS_PDD.h	91;"	d
OCCS_PDD_EDGE_RISING	.\Static_Code\PDD\OCCS_PDD.h	92;"	d
OCCS_PDD_EXTERNAL_CLOCK_CHECKING_BUSY	.\Static_Code\PDD\OCCS_PDD.h	88;"	d
OCCS_PDD_EXTERNAL_CLOCK_CHECKING_DONE	.\Static_Code\PDD\OCCS_PDD.h	87;"	d
OCCS_PDD_EXTERNAL_CLOCK_CLKIN	.\Static_Code\PDD\OCCS_PDD.h	84;"	d
OCCS_PDD_EXTERNAL_CLOCK_OSCILLATOR	.\Static_Code\PDD\OCCS_PDD.h	83;"	d
OCCS_PDD_EnableLockDetector	.\Static_Code\PDD\OCCS_PDD.h	293;"	d
OCCS_PDD_EnableLossOfReferenceClockInterrupt	.\Static_Code\PDD\OCCS_PDD.h	253;"	d
OCCS_PDD_EnablePll	.\Static_Code\PDD\OCCS_PDD.h	336;"	d
OCCS_PDD_EnableRosc200k	.\Static_Code\PDD\OCCS_PDD.h	993;"	d
OCCS_PDD_EnableRosc8M	.\Static_Code\PDD\OCCS_PDD.h	722;"	d
OCCS_PDD_EnableRosc8MStandby	.\Static_Code\PDD\OCCS_PDD.h	771;"	d
OCCS_PDD_EnableXosc	.\Static_Code\PDD\OCCS_PDD.h	1041;"	d
OCCS_PDD_EnableXoscMonitor	.\Static_Code\PDD\OCCS_PDD.h	1136;"	d
OCCS_PDD_GetClockOutputDivider	.\Static_Code\PDD\OCCS_PDD.h	538;"	d
OCCS_PDD_GetClockSource	.\Static_Code\PDD\OCCS_PDD.h	449;"	d
OCCS_PDD_GetExternalClockCheckReference	.\Static_Code\PDD\OCCS_PDD.h	1282;"	d
OCCS_PDD_GetExternalClockCheckStatus	.\Static_Code\PDD\OCCS_PDD.h	1264;"	d
OCCS_PDD_GetExternalClockCheckTarget	.\Static_Code\PDD\OCCS_PDD.h	1300;"	d
OCCS_PDD_GetExternalClockSource	.\Static_Code\PDD\OCCS_PDD.h	926;"	d
OCCS_PDD_GetFrequencyProtection	.\Static_Code\PDD\OCCS_PDD.h	1345;"	d
OCCS_PDD_GetInterruptEgdePll0	.\Static_Code\PDD\OCCS_PDD.h	233;"	d
OCCS_PDD_GetInterruptEgdePll1	.\Static_Code\PDD\OCCS_PDD.h	188;"	d
OCCS_PDD_GetInterruptFlags	.\Static_Code\PDD\OCCS_PDD.h	122;"	d
OCCS_PDD_GetLockDetectorEnabled	.\Static_Code\PDD\OCCS_PDD.h	315;"	d
OCCS_PDD_GetLossOfReferenceClockTripPoint	.\Static_Code\PDD\OCCS_PDD.h	492;"	d
OCCS_PDD_GetOscillatorProtection	.\Static_Code\PDD\OCCS_PDD.h	1391;"	d
OCCS_PDD_GetPllEnabled	.\Static_Code\PDD\OCCS_PDD.h	358;"	d
OCCS_PDD_GetPllMultiplier	.\Static_Code\PDD\OCCS_PDD.h	628;"	d
OCCS_PDD_GetPllMultiplierRaw	.\Static_Code\PDD\OCCS_PDD.h	670;"	d
OCCS_PDD_GetPllProtection	.\Static_Code\PDD\OCCS_PDD.h	1437;"	d
OCCS_PDD_GetPrescalerClockSource	.\Static_Code\PDD\OCCS_PDD.h	404;"	d
OCCS_PDD_GetPwmNanoEdgeClockSource	.\Static_Code\PDD\OCCS_PDD.h	582;"	d
OCCS_PDD_GetRosc200kEnabled	.\Static_Code\PDD\OCCS_PDD.h	1015;"	d
OCCS_PDD_GetRosc200kFrequencyTrim	.\Static_Code\PDD\OCCS_PDD.h	1203;"	d
OCCS_PDD_GetRosc8MEnabled	.\Static_Code\PDD\OCCS_PDD.h	744;"	d
OCCS_PDD_GetRosc8MFrequencyTrim	.\Static_Code\PDD\OCCS_PDD.h	968;"	d
OCCS_PDD_GetRosc8MStandbyEnabled	.\Static_Code\PDD\OCCS_PDD.h	793;"	d
OCCS_PDD_GetRosc8MTemperatureTrim	.\Static_Code\PDD\OCCS_PDD.h	1109;"	d
OCCS_PDD_GetStatusFlags	.\Static_Code\PDD\OCCS_PDD.h	688;"	d
OCCS_PDD_GetXoscEnabled	.\Static_Code\PDD\OCCS_PDD.h	1063;"	d
OCCS_PDD_GetXoscMode	.\Static_Code\PDD\OCCS_PDD.h	881;"	d
OCCS_PDD_GetXoscMonitorEnabled	.\Static_Code\PDD\OCCS_PDD.h	1161;"	d
OCCS_PDD_GetXoscPowerMode	.\Static_Code\PDD\OCCS_PDD.h	837;"	d
OCCS_PDD_H_	.\Static_Code\PDD\OCCS_PDD.h	9;"	d
OCCS_PDD_LOSS_OF_CLOCK_FLAG	.\Static_Code\PDD\OCCS_PDD.h	43;"	d
OCCS_PDD_MASTER_OSCILLATOR	.\Static_Code\PDD\OCCS_PDD.h	70;"	d
OCCS_PDD_OSCILLATOR_POWER_HIGH	.\Static_Code\PDD\OCCS_PDD.h	75;"	d
OCCS_PDD_OSCILLATOR_POWER_LOW	.\Static_Code\PDD\OCCS_PDD.h	76;"	d
OCCS_PDD_PLL_DIV2	.\Static_Code\PDD\OCCS_PDD.h	71;"	d
OCCS_PDD_PLL_LOCK0	.\Static_Code\PDD\OCCS_PDD.h	68;"	d
OCCS_PDD_PLL_LOCK0_FLAG	.\Static_Code\PDD\OCCS_PDD.h	42;"	d
OCCS_PDD_PLL_LOCK1	.\Static_Code\PDD\OCCS_PDD.h	67;"	d
OCCS_PDD_PLL_LOCK1_FLAG	.\Static_Code\PDD\OCCS_PDD.h	41;"	d
OCCS_PDD_PLL_POWER_DOWN	.\Static_Code\PDD\OCCS_PDD.h	69;"	d
OCCS_PDD_PRESCALER_SOURCE_EXTERNAL_REFERENCE	.\Static_Code\PDD\OCCS_PDD.h	98;"	d
OCCS_PDD_PRESCALER_SOURCE_ROSC_200K	.\Static_Code\PDD\OCCS_PDD.h	99;"	d
OCCS_PDD_PRESCALER_SOURCE_ROSC_8M	.\Static_Code\PDD\OCCS_PDD.h	97;"	d
OCCS_PDD_PROTECTION_DISABLE	.\Static_Code\PDD\OCCS_PDD.h	102;"	d
OCCS_PDD_PROTECTION_DISABLE_LOCKED	.\Static_Code\PDD\OCCS_PDD.h	104;"	d
OCCS_PDD_PROTECTION_ENABLE	.\Static_Code\PDD\OCCS_PDD.h	103;"	d
OCCS_PDD_PROTECTION_ENABLE_LOCKED	.\Static_Code\PDD\OCCS_PDD.h	105;"	d
OCCS_PDD_PWM_PLL	.\Static_Code\PDD\OCCS_PDD.h	61;"	d
OCCS_PDD_PWM_PLL_DIV2	.\Static_Code\PDD\OCCS_PDD.h	62;"	d
OCCS_PDD_ReadControlReg	.\Static_Code\PDD\OCCS_PDD.h	1475;"	d
OCCS_PDD_ReadExternalClockCheckReferenceReg	.\Static_Code\PDD\OCCS_PDD.h	1665;"	d
OCCS_PDD_ReadExternalClockCheckTargetReg	.\Static_Code\PDD\OCCS_PDD.h	1703;"	d
OCCS_PDD_ReadOscillatorControl1Reg	.\Static_Code\PDD\OCCS_PDD.h	1589;"	d
OCCS_PDD_ReadOscillatorControl2Reg	.\Static_Code\PDD\OCCS_PDD.h	1627;"	d
OCCS_PDD_ReadPllControlReg	.\Static_Code\PDD\OCCS_PDD.h	1513;"	d
OCCS_PDD_ReadProtectionReg	.\Static_Code\PDD\OCCS_PDD.h	1741;"	d
OCCS_PDD_ReadStatusReg	.\Static_Code\PDD\OCCS_PDD.h	1551;"	d
OCCS_PDD_SYNCHRONIZATION_IN_PROGRESS	.\Static_Code\PDD\OCCS_PDD.h	72;"	d
OCCS_PDD_SetClockOutputDivider	.\Static_Code\PDD\OCCS_PDD.h	515;"	d
OCCS_PDD_SetClockSource	.\Static_Code\PDD\OCCS_PDD.h	426;"	d
OCCS_PDD_SetExternalClockSource	.\Static_Code\PDD\OCCS_PDD.h	903;"	d
OCCS_PDD_SetFrequencyProtection	.\Static_Code\PDD\OCCS_PDD.h	1323;"	d
OCCS_PDD_SetInterruptEgdePll0	.\Static_Code\PDD\OCCS_PDD.h	211;"	d
OCCS_PDD_SetInterruptEgdePll1	.\Static_Code\PDD\OCCS_PDD.h	166;"	d
OCCS_PDD_SetLossOfReferenceClockTripPoint	.\Static_Code\PDD\OCCS_PDD.h	470;"	d
OCCS_PDD_SetOscillatorProtection	.\Static_Code\PDD\OCCS_PDD.h	1368;"	d
OCCS_PDD_SetPllMultiplier	.\Static_Code\PDD\OCCS_PDD.h	604;"	d
OCCS_PDD_SetPllMultiplierRaw	.\Static_Code\PDD\OCCS_PDD.h	648;"	d
OCCS_PDD_SetPllProtection	.\Static_Code\PDD\OCCS_PDD.h	1414;"	d
OCCS_PDD_SetPrescalerClockSource	.\Static_Code\PDD\OCCS_PDD.h	381;"	d
OCCS_PDD_SetPwmNanoEdgeClockSource	.\Static_Code\PDD\OCCS_PDD.h	559;"	d
OCCS_PDD_SetRosc200kFrequencyTrim	.\Static_Code\PDD\OCCS_PDD.h	1181;"	d
OCCS_PDD_SetRosc8MFrequencyTrim	.\Static_Code\PDD\OCCS_PDD.h	946;"	d
OCCS_PDD_SetRosc8MTemperatureTrim	.\Static_Code\PDD\OCCS_PDD.h	1087;"	d
OCCS_PDD_SetXoscClockMode	.\Static_Code\PDD\OCCS_PDD.h	858;"	d
OCCS_PDD_SetXoscPowerMode	.\Static_Code\PDD\OCCS_PDD.h	814;"	d
OCCS_PDD_StartExternalClockCheck	.\Static_Code\PDD\OCCS_PDD.h	1224;"	d
OCCS_PDD_StopExternalClockCheck	.\Static_Code\PDD\OCCS_PDD.h	1242;"	d
OCCS_PDD_WriteControlReg	.\Static_Code\PDD\OCCS_PDD.h	1457;"	d
OCCS_PDD_WriteExternalClockCheckReferenceReg	.\Static_Code\PDD\OCCS_PDD.h	1647;"	d
OCCS_PDD_WriteExternalClockCheckTargetReg	.\Static_Code\PDD\OCCS_PDD.h	1685;"	d
OCCS_PDD_WriteOscillatorControl1Reg	.\Static_Code\PDD\OCCS_PDD.h	1571;"	d
OCCS_PDD_WriteOscillatorControl2Reg	.\Static_Code\PDD\OCCS_PDD.h	1609;"	d
OCCS_PDD_WritePllControlReg	.\Static_Code\PDD\OCCS_PDD.h	1495;"	d
OCCS_PDD_WriteProtectionReg	.\Static_Code\PDD\OCCS_PDD.h	1723;"	d
OCCS_PDD_WriteStatusReg	.\Static_Code\PDD\OCCS_PDD.h	1533;"	d
OCCS_PDD_XOSC_CLOCK_BYPASS	.\Static_Code\PDD\OCCS_PDD.h	80;"	d
OCCS_PDD_XOSC_CLOCK_ENABLE	.\Static_Code\PDD\OCCS_PDD.h	79;"	d
OCCS_PDD_XOSC_FAILURE	.\Static_Code\PDD\OCCS_PDD.h	65;"	d
OCCS_PDD_XOSC_STABLE	.\Static_Code\PDD\OCCS_PDD.h	66;"	d
OCCS_PROT	.\Static_Code\IO_Map\MC56F82748.h	4112;"	d
OCCS_PROT_FRQEP	.\Static_Code\IO_Map\MC56F82748.h	4080;"	d
OCCS_PROT_FRQEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	4078;"	d
OCCS_PROT_FRQEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4079;"	d
OCCS_PROT_OSCEP	.\Static_Code\IO_Map\MC56F82748.h	4077;"	d
OCCS_PROT_OSCEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	4075;"	d
OCCS_PROT_OSCEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4076;"	d
OCCS_PROT_PLLEP	.\Static_Code\IO_Map\MC56F82748.h	4074;"	d
OCCS_PROT_PLLEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	4072;"	d
OCCS_PROT_PLLEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4073;"	d
OCCS_PROT_REG	.\Static_Code\IO_Map\MC56F82748.h	3968;"	d
OCCS_STAT	.\Static_Code\IO_Map\MC56F82748.h	4107;"	d
OCCS_STAT_LCK0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4020;"	d
OCCS_STAT_LCK0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4021;"	d
OCCS_STAT_LCK1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4022;"	d
OCCS_STAT_LCK1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4023;"	d
OCCS_STAT_LOCI_MASK	.\Static_Code\IO_Map\MC56F82748.h	4028;"	d
OCCS_STAT_LOCI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4029;"	d
OCCS_STAT_LOLI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4030;"	d
OCCS_STAT_LOLI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4031;"	d
OCCS_STAT_LOLI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4032;"	d
OCCS_STAT_LOLI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4033;"	d
OCCS_STAT_MON_FAILURE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4026;"	d
OCCS_STAT_MON_FAILURE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4027;"	d
OCCS_STAT_OSC_OK_MASK	.\Static_Code\IO_Map\MC56F82748.h	4024;"	d
OCCS_STAT_OSC_OK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4025;"	d
OCCS_STAT_PLLPDN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4018;"	d
OCCS_STAT_PLLPDN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4019;"	d
OCCS_STAT_REG	.\Static_Code\IO_Map\MC56F82748.h	3963;"	d
OCCS_STAT_ZSRCS	.\Static_Code\IO_Map\MC56F82748.h	4017;"	d
OCCS_STAT_ZSRCS_MASK	.\Static_Code\IO_Map\MC56F82748.h	4015;"	d
OCCS_STAT_ZSRCS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4016;"	d
OCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t OCTRL;                                  \/**< Output Control Register, array offset: 0x11, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
OFFST	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t OFFST[16];                              \/**< ADC Offset Registers, array offset: 0x3E, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
OFFST_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t OFFST_2[4];                             \/**< ADC Offset Registers 2, array offset: 0x6B, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
OSCTL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t OSCTL1;                                 \/**< Oscillator Control Register 1, offset: 0x4 *\/$/;"	m	struct:OCCS_MemMap
OSCTL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t OSCTL2;                                 \/**< Oscillator Control Register 2, offset: 0x5 *\/$/;"	m	struct:OCCS_MemMap
OUTEN	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t OUTEN;                                  \/**< Output Enable Register, offset: 0xC0 *\/$/;"	m	struct:PWM_MemMap
OUTPUT_CLEAR	.\Generated_Code\PE_LDD.h	/^  OUTPUT_CLEAR,$/;"	e	enum:__anon7
OUTPUT_NONE	.\Generated_Code\PE_LDD.h	/^  OUTPUT_NONE,$/;"	e	enum:__anon7
OUTPUT_SET	.\Generated_Code\PE_LDD.h	/^  OUTPUT_SET$/;"	e	enum:__anon7
OUTPUT_TOGGLE	.\Generated_Code\PE_LDD.h	/^  OUTPUT_TOGGLE,$/;"	e	enum:__anon7
O_SRCS	.\FLASH_SDM\sources.mk	/^O_SRCS := $/;"	m
O_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^O_SRCS_OS_FORMAT := $/;"	m
O_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^O_SRCS_QUOTED := $/;"	m
OffsetValue	.\Generated_Code\PE_LDD.h	/^  uint16_t OffsetValue;                \/*!< Offset value *\/$/;"	m	struct:__anon44
OutputTransposeMode	.\Generated_Code\PE_LDD.h	/^  LDD_CRC_TTransposeType OutputTransposeMode; \/* Output transpose type *\/$/;"	m	struct:__anon13
OverrunErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t OverrunErrors;              \/* Number of receiver overrun errors *\/$/;"	m	struct:__anon19
PCE0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PCE0;                                   \/**< Peripheral Clock Enable Register 0, offset: 0xC *\/$/;"	m	struct:SIM_MemMap
PCE1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PCE1;                                   \/**< Peripheral Clock Enable Register 1, offset: 0xD *\/$/;"	m	struct:SIM_MemMap
PCE2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PCE2;                                   \/**< Peripheral Clock Enable Register 2, offset: 0xE *\/$/;"	m	struct:SIM_MemMap
PCE3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PCE3;                                   \/**< Peripheral Clock Enable Register 3, offset: 0xF *\/$/;"	m	struct:SIM_MemMap
PCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PCR;                                    \/**< Peripheral Clock Rate Register, offset: 0xB *\/$/;"	m	struct:SIM_MemMap
PDD_DISABLE	.\Static_Code\PDD\PDD_Types.h	37;"	d
PDD_ENABLE	.\Static_Code\PDD\PDD_Types.h	38;"	d
PDD_TBool	.\Static_Code\PDD\PDD_Types.h	/^typedef bool PDD_TBool;$/;"	t
PDD_TBool	.\Static_Code\PDD\PDD_Types.h	/^typedef uint16_t PDD_TBool;$/;"	t
PDD_TYPES_H_	.\Static_Code\PDD\PDD_Types.h	5;"	d
PER	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PER;                                    \/**< GPIO Peripheral Enable Register, offset: 0x3 *\/$/;"	m	struct:GPIO_MemMap
PE_BitIoLdd1_ClrVal	.\Generated_Code\BitIoLdd1.c	/^void PE_BitIoLdd1_ClrVal()$/;"	f
PE_BitIoLdd1_GetVal	.\Generated_Code\BitIoLdd1.c	/^bool PE_BitIoLdd1_GetVal()$/;"	f
PE_BitIoLdd1_PutVal	.\Generated_Code\BitIoLdd1.c	/^void PE_BitIoLdd1_PutVal(bool Val)$/;"	f
PE_BitIoLdd1_SetVal	.\Generated_Code\BitIoLdd1.c	/^void PE_BitIoLdd1_SetVal()$/;"	f
PE_CpuClockConfigurations	.\Generated_Code\PE_LDD.c	/^const TCpuClockConfiguration PE_CpuClockConfigurations[CPU_CLOCK_CONFIG_NUMBER] = {$/;"	v
PE_FillMemory	.\Generated_Code\PE_LDD.c	/^void PE_FillMemory(register void* SourceAddressPtr, register uint8_t c, register uint32_t len)$/;"	f
PE_LDD_COMPONENT_BitIoLdd1_ID	.\Generated_Code\PE_LDD.h	88;"	d
PE_LDD_COMPONENT_TU1_ID	.\Generated_Code\PE_LDD.h	87;"	d
PE_LDD_DRIVER_BUSY	.\Generated_Code\PE_LDD.h	70;"	d
PE_LDD_DRIVER_DISABLED_BY_USER	.\Generated_Code\PE_LDD.h	69;"	d
PE_LDD_DRIVER_DISABLED_IN_CLOCK_CONFIGURATION	.\Generated_Code\PE_LDD.h	68;"	d
PE_LDD_DeviceDataList	.\Generated_Code\PE_LDD.c	/^LDD_TDeviceData *PE_LDD_DeviceDataList[2] = {$/;"	v
PE_LDD_GetDeviceStructure	.\Generated_Code\PE_LDD.h	79;"	d
PE_LDD_RegisterDeviceStructure	.\Generated_Code\PE_LDD.h	73;"	d
PE_LDD_UnregisterDeviceStructure	.\Generated_Code\PE_LDD.h	76;"	d
PE_LDD_VERSION	.\Generated_Code\PE_LDD.h	65;"	d
PE_PeripheralUsed	.\Generated_Code\PE_LDD.c	/^bool PE_PeripheralUsed(uint32_t PrphBaseAddress)$/;"	f
PE_low_level_init	.\Static_Code\System\CPU_Init.c	/^void PE_low_level_init(void)$/;"	f
PEcfg_MC56F82748VLH_Internal_PFlash_SDM	.\Generated_Code\Cpu.h	87;"	d
PFAPR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t PFAPR;                                  \/**< Flash Access Protection Register, offset: 0x0 *\/$/;"	m	struct:FMC_MemMap
PFB0CR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t PFB0CR;                                 \/**< Flash Control Register, offset: 0x2 *\/$/;"	m	struct:FMC_MemMap
PIMAGE	.\Static_Code\System\PE_Types.h	/^typedef TIMAGE* PIMAGE ; \/* Pointer to image *\/$/;"	t
PIT0_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	4200;"	d
PIT0_CNTR	.\Static_Code\IO_Map\MC56F82748.h	4220;"	d
PIT0_CTRL	.\Static_Code\IO_Map\MC56F82748.h	4218;"	d
PIT0_Init	.\Static_Code\Peripherals\PIT0_Init.c	/^void PIT0_Init(void) {$/;"	f
PIT0_MOD	.\Static_Code\IO_Map\MC56F82748.h	4219;"	d
PIT1_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	4202;"	d
PIT1_CNTR	.\Static_Code\IO_Map\MC56F82748.h	4224;"	d
PIT1_CTRL	.\Static_Code\IO_Map\MC56F82748.h	4222;"	d
PIT1_Init	.\Static_Code\Peripherals\PIT1_Init.c	/^void PIT1_Init(void) {$/;"	f
PIT1_MOD	.\Static_Code\IO_Map\MC56F82748.h	4223;"	d
PIT_100k_OnInterrupt	.\Sources\Events.c	/^void PIT_100k_OnInterrupt(void)$/;"	f
PIT_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	4204;"	d
PIT_CNTR_COUNTER_VALUE	.\Static_Code\IO_Map\MC56F82748.h	4191;"	d
PIT_CNTR_COUNTER_VALUE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4189;"	d
PIT_CNTR_COUNTER_VALUE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4190;"	d
PIT_CNTR_REG	.\Static_Code\IO_Map\MC56F82748.h	4153;"	d
PIT_CTRL_CLKSEL	.\Static_Code\IO_Map\MC56F82748.h	4181;"	d
PIT_CTRL_CLKSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4179;"	d
PIT_CTRL_CLKSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4180;"	d
PIT_CTRL_CNT_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4170;"	d
PIT_CTRL_CNT_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4171;"	d
PIT_CTRL_PRESCALER	.\Static_Code\IO_Map\MC56F82748.h	4178;"	d
PIT_CTRL_PRESCALER_MASK	.\Static_Code\IO_Map\MC56F82748.h	4176;"	d
PIT_CTRL_PRESCALER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4177;"	d
PIT_CTRL_PRF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4174;"	d
PIT_CTRL_PRF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4175;"	d
PIT_CTRL_PRIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4172;"	d
PIT_CTRL_PRIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4173;"	d
PIT_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4151;"	d
PIT_CTRL_SLAVE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4182;"	d
PIT_CTRL_SLAVE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4183;"	d
PIT_MOD_MODULO_VALUE	.\Static_Code\IO_Map\MC56F82748.h	4187;"	d
PIT_MOD_MODULO_VALUE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4185;"	d
PIT_MOD_MODULO_VALUE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4186;"	d
PIT_MOD_REG	.\Static_Code\IO_Map\MC56F82748.h	4152;"	d
PIT_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct PIT_MemMap {$/;"	s
PIT_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *PIT_MemMapPtr;$/;"	t
PIT_PDD_ClearInterruptFlag	.\Static_Code\PDD\PIT_PDD.h	213;"	d
PIT_PDD_DIVIDE_1	.\Static_Code\PDD\PIT_PDD.h	41;"	d
PIT_PDD_DIVIDE_1024	.\Static_Code\PDD\PIT_PDD.h	51;"	d
PIT_PDD_DIVIDE_128	.\Static_Code\PDD\PIT_PDD.h	48;"	d
PIT_PDD_DIVIDE_16	.\Static_Code\PDD\PIT_PDD.h	45;"	d
PIT_PDD_DIVIDE_16384	.\Static_Code\PDD\PIT_PDD.h	55;"	d
PIT_PDD_DIVIDE_2	.\Static_Code\PDD\PIT_PDD.h	42;"	d
PIT_PDD_DIVIDE_2048	.\Static_Code\PDD\PIT_PDD.h	52;"	d
PIT_PDD_DIVIDE_256	.\Static_Code\PDD\PIT_PDD.h	49;"	d
PIT_PDD_DIVIDE_32	.\Static_Code\PDD\PIT_PDD.h	46;"	d
PIT_PDD_DIVIDE_32768	.\Static_Code\PDD\PIT_PDD.h	56;"	d
PIT_PDD_DIVIDE_4	.\Static_Code\PDD\PIT_PDD.h	43;"	d
PIT_PDD_DIVIDE_4096	.\Static_Code\PDD\PIT_PDD.h	53;"	d
PIT_PDD_DIVIDE_512	.\Static_Code\PDD\PIT_PDD.h	50;"	d
PIT_PDD_DIVIDE_64	.\Static_Code\PDD\PIT_PDD.h	47;"	d
PIT_PDD_DIVIDE_8	.\Static_Code\PDD\PIT_PDD.h	44;"	d
PIT_PDD_DIVIDE_8192	.\Static_Code\PDD\PIT_PDD.h	54;"	d
PIT_PDD_DisableInterrupt	.\Static_Code\PDD\PIT_PDD.h	152;"	d
PIT_PDD_EnableDevice	.\Static_Code\PDD\PIT_PDD.h	83;"	d
PIT_PDD_EnableInterrupt	.\Static_Code\PDD\PIT_PDD.h	130;"	d
PIT_PDD_EnableSlaveMode	.\Static_Code\PDD\PIT_PDD.h	286;"	d
PIT_PDD_GetEnableDeviceStatus	.\Static_Code\PDD\PIT_PDD.h	111;"	d
PIT_PDD_GetInterruptFlag	.\Static_Code\PDD\PIT_PDD.h	194;"	d
PIT_PDD_GetInterruptMask	.\Static_Code\PDD\PIT_PDD.h	175;"	d
PIT_PDD_H_	.\Static_Code\PDD\PIT_PDD.h	9;"	d
PIT_PDD_ReadControlReg	.\Static_Code\PDD\PIT_PDD.h	335;"	d
PIT_PDD_ReadCounterReg	.\Static_Code\PDD\PIT_PDD.h	394;"	d
PIT_PDD_ReadModuloReg	.\Static_Code\PDD\PIT_PDD.h	375;"	d
PIT_PDD_SOURCE_BUS_CLK	.\Static_Code\PDD\PIT_PDD.h	59;"	d
PIT_PDD_SOURCE_ROSC_200K	.\Static_Code\PDD\PIT_PDD.h	62;"	d
PIT_PDD_SOURCE_ROSC_8M	.\Static_Code\PDD\PIT_PDD.h	61;"	d
PIT_PDD_SOURCE_XTAL_OSC	.\Static_Code\PDD\PIT_PDD.h	60;"	d
PIT_PDD_SelectClockSource	.\Static_Code\PDD\PIT_PDD.h	260;"	d
PIT_PDD_SetPrescaler	.\Static_Code\PDD\PIT_PDD.h	233;"	d
PIT_PDD_WriteControlReg	.\Static_Code\PDD\PIT_PDD.h	316;"	d
PIT_PDD_WriteModuloReg	.\Static_Code\PDD\PIT_PDD.h	356;"	d
PLAMC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PLAMC;                                  \/**< Crossbar switch (AXBS) master configuration, offset: 0xA *\/$/;"	m	struct:MCM_MemMap
PLASC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PLASC;                                  \/**< Crossbar switch (AXBS) slave configuration, offset: 0x8 *\/$/;"	m	struct:MCM_MemMap
PMC_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	4314;"	d
PMC_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	4316;"	d
PMC_CTRL	.\Static_Code\IO_Map\MC56F82748.h	4330;"	d
PMC_CTRL_HV22IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4284;"	d
PMC_CTRL_HV22IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4285;"	d
PMC_CTRL_HV27IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4286;"	d
PMC_CTRL_HV27IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4287;"	d
PMC_CTRL_LV22IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4280;"	d
PMC_CTRL_LV22IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4281;"	d
PMC_CTRL_LV27IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4282;"	d
PMC_CTRL_LV27IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4283;"	d
PMC_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4262;"	d
PMC_CTRL_TRIM	.\Static_Code\IO_Map\MC56F82748.h	4292;"	d
PMC_CTRL_TRIM_MASK	.\Static_Code\IO_Map\MC56F82748.h	4290;"	d
PMC_CTRL_TRIM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4291;"	d
PMC_CTRL_VRBEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4288;"	d
PMC_CTRL_VRBEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4289;"	d
PMC_Init	.\Static_Code\Peripherals\PMC_Init.c	/^void PMC_Init(void) {$/;"	f
PMC_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct PMC_MemMap {$/;"	s
PMC_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *PMC_MemMapPtr;$/;"	t
PMC_PDD_2_2_V_HIGH_VOLTAGE_INTERRUPT	.\Static_Code\PDD\PMC_PDD.h	42;"	d
PMC_PDD_2_2_V_LOW_VOLTAGE_FLAG	.\Static_Code\PDD\PMC_PDD.h	54;"	d
PMC_PDD_2_2_V_LOW_VOLTAGE_INTERRUPT	.\Static_Code\PDD\PMC_PDD.h	44;"	d
PMC_PDD_2_7_V_HIGH_VOLTAGE_INTERRUPT	.\Static_Code\PDD\PMC_PDD.h	41;"	d
PMC_PDD_2_7_V_LOW_VOLTAGE_FLAG	.\Static_Code\PDD\PMC_PDD.h	53;"	d
PMC_PDD_2_7_V_LOW_VOLTAGE_INTERRUPT	.\Static_Code\PDD\PMC_PDD.h	43;"	d
PMC_PDD_2_7_V_SMALL_REGULATOR_FLAG	.\Static_Code\PDD\PMC_PDD.h	52;"	d
PMC_PDD_ClearInterruptFlags	.\Static_Code\PDD\PMC_PDD.h	137;"	d
PMC_PDD_DisableInterrupts	.\Static_Code\PDD\PMC_PDD.h	95;"	d
PMC_PDD_EnableInterrupts	.\Static_Code\PDD\PMC_PDD.h	74;"	d
PMC_PDD_EnableVoltageReferenceBuffer	.\Static_Code\PDD\PMC_PDD.h	233;"	d
PMC_PDD_GetBandgapTrim	.\Static_Code\PDD\PMC_PDD.h	209;"	d
PMC_PDD_GetInterruptFlags	.\Static_Code\PDD\PMC_PDD.h	114;"	d
PMC_PDD_GetStatusFlags	.\Static_Code\PDD\PMC_PDD.h	159;"	d
PMC_PDD_GetVoltageReferenceBufferEnabled	.\Static_Code\PDD\PMC_PDD.h	253;"	d
PMC_PDD_H_	.\Static_Code\PDD\PMC_PDD.h	9;"	d
PMC_PDD_LOW_VOLTAGE_FLAG	.\Static_Code\PDD\PMC_PDD.h	47;"	d
PMC_PDD_ReadControlReg	.\Static_Code\PDD\PMC_PDD.h	290;"	d
PMC_PDD_ReadStatusReg	.\Static_Code\PDD\PMC_PDD.h	327;"	d
PMC_PDD_STICKY_2_2_V_LOW_VOLTAGE_FLAG	.\Static_Code\PDD\PMC_PDD.h	49;"	d
PMC_PDD_STICKY_2_7_V_LOW_VOLTAGE_FLAG	.\Static_Code\PDD\PMC_PDD.h	48;"	d
PMC_PDD_SetBandgapTrim	.\Static_Code\PDD\PMC_PDD.h	187;"	d
PMC_PDD_WriteControlReg	.\Static_Code\PDD\PMC_PDD.h	272;"	d
PMC_PDD_WriteStatusReg	.\Static_Code\PDD\PMC_PDD.h	309;"	d
PMC_STS	.\Static_Code\IO_Map\MC56F82748.h	4331;"	d
PMC_STS_LV22F_MASK	.\Static_Code\IO_Map\MC56F82748.h	4294;"	d
PMC_STS_LV22F_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4295;"	d
PMC_STS_LV27F_MASK	.\Static_Code\IO_Map\MC56F82748.h	4296;"	d
PMC_STS_LV27F_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4297;"	d
PMC_STS_LVI_MASK	.\Static_Code\IO_Map\MC56F82748.h	4302;"	d
PMC_STS_LVI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4303;"	d
PMC_STS_REG	.\Static_Code\IO_Map\MC56F82748.h	4263;"	d
PMC_STS_SLV22F_MASK	.\Static_Code\IO_Map\MC56F82748.h	4298;"	d
PMC_STS_SLV22F_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4299;"	d
PMC_STS_SLV27F_MASK	.\Static_Code\IO_Map\MC56F82748.h	4300;"	d
PMC_STS_SLV27F_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4301;"	d
PMC_STS_SR27_MASK	.\Static_Code\IO_Map\MC56F82748.h	4304;"	d
PMC_STS_SR27_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4305;"	d
PPMODE	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PPMODE;                                 \/**< GPIO Push-Pull Mode Register, offset: 0x9 *\/$/;"	m	struct:GPIO_MemMap
PROT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PROT;                                   \/**< Protection Register, offset: 0x16 *\/$/;"	m	struct:SIM_MemMap
PROT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PROT;                                   \/**< Protection Register, offset: 0x8 *\/$/;"	m	struct:OCCS_MemMap
PSWR0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PSWR0;                                  \/**< Peripheral Software Reset Register 0, offset: 0x24 *\/$/;"	m	struct:SIM_MemMap
PSWR1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PSWR1;                                  \/**< Peripheral Software Reset Register 1, offset: 0x25 *\/$/;"	m	struct:SIM_MemMap
PSWR2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PSWR2;                                  \/**< Peripheral Software Reset Register 2, offset: 0x26 *\/$/;"	m	struct:SIM_MemMap
PSWR3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PSWR3;                                  \/**< Peripheral Software Reset Register 3, offset: 0x27 *\/$/;"	m	struct:SIM_MemMap
PUR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PUR;                                    \/**< GPIO Pull Resistor Enable Register, offset: 0x0 *\/$/;"	m	struct:GPIO_MemMap
PUS	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PUS;                                    \/**< GPIO Pull Resistor Type Select, offset: 0xC *\/$/;"	m	struct:GPIO_MemMap
PWMA_AUTOINIT	.\Generated_Code\PWMA_Config.h	482;"	d
PWMA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	4993;"	d
PWMA_CAPTCOMPA	.\Static_Code\IO_Map\MC56F82748.h	5222;"	d
PWMA_CAPTCOMPB	.\Static_Code\IO_Map\MC56F82748.h	5224;"	d
PWMA_CAPTCOMPX	.\Static_Code\IO_Map\MC56F82748.h	5226;"	d
PWMA_CAPTCTRLA	.\Static_Code\IO_Map\MC56F82748.h	5221;"	d
PWMA_CAPTCTRLB	.\Static_Code\IO_Map\MC56F82748.h	5223;"	d
PWMA_CAPTCTRLX	.\Static_Code\IO_Map\MC56F82748.h	5225;"	d
PWMA_CNT	.\Static_Code\IO_Map\MC56F82748.h	5197;"	d
PWMA_CTRL	.\Static_Code\IO_Map\MC56F82748.h	5200;"	d
PWMA_CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5199;"	d
PWMA_CVAL0	.\Static_Code\IO_Map\MC56F82748.h	5227;"	d
PWMA_CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	5228;"	d
PWMA_CVAL1	.\Static_Code\IO_Map\MC56F82748.h	5229;"	d
PWMA_CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	5230;"	d
PWMA_CVAL2	.\Static_Code\IO_Map\MC56F82748.h	5231;"	d
PWMA_CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	5232;"	d
PWMA_CVAL3	.\Static_Code\IO_Map\MC56F82748.h	5233;"	d
PWMA_CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	5234;"	d
PWMA_CVAL4	.\Static_Code\IO_Map\MC56F82748.h	5235;"	d
PWMA_CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	5236;"	d
PWMA_CVAL5	.\Static_Code\IO_Map\MC56F82748.h	5237;"	d
PWMA_CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	5238;"	d
PWMA_Config_H_	.\Generated_Code\PWMA_Config.h	370;"	d
PWMA_DEVICE	.\Generated_Code\PWMA.h	379;"	d
PWMA_DISMAP	.\Static_Code\IO_Map\MC56F82748.h	5218;"	d
PWMA_DMAEN	.\Static_Code\IO_Map\MC56F82748.h	5216;"	d
PWMA_DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	5219;"	d
PWMA_DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	5220;"	d
PWMA_DTSRCSEL	.\Static_Code\IO_Map\MC56F82748.h	5184;"	d
PWMA_DTSRCSEL_MASK	.\Generated_Code\PWMA_Config.h	445;"	d
PWMA_DTSRCSEL_VALUE	.\Generated_Code\PWMA_Config.h	444;"	d
PWMA_FCTRL	.\Static_Code\IO_Map\MC56F82748.h	5239;"	d
PWMA_FCTRL0	.\Static_Code\IO_Map\MC56F82748.h	5187;"	d
PWMA_FCTRL0_VALUE_1	.\Generated_Code\PWMA_Config.h	380;"	d
PWMA_FCTRL0_VALUE_2	.\Generated_Code\PWMA_Config.h	465;"	d
PWMA_FCTRL1	.\Static_Code\IO_Map\MC56F82748.h	5191;"	d
PWMA_FCTRL1_VALUE_1	.\Generated_Code\PWMA_Config.h	382;"	d
PWMA_FCTRL1_VALUE_2	.\Generated_Code\PWMA_Config.h	467;"	d
PWMA_FFILT	.\Static_Code\IO_Map\MC56F82748.h	5241;"	d
PWMA_FFILT0	.\Static_Code\IO_Map\MC56F82748.h	5189;"	d
PWMA_FFILT0_MASK	.\Generated_Code\PWMA_Config.h	433;"	d
PWMA_FFILT0_VALUE	.\Generated_Code\PWMA_Config.h	432;"	d
PWMA_FFILT1	.\Static_Code\IO_Map\MC56F82748.h	5193;"	d
PWMA_FFILT1_MASK	.\Generated_Code\PWMA_Config.h	436;"	d
PWMA_FFILT1_VALUE	.\Generated_Code\PWMA_Config.h	435;"	d
PWMA_FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	5202;"	d
PWMA_FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	5204;"	d
PWMA_FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	5206;"	d
PWMA_FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	5208;"	d
PWMA_FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	5210;"	d
PWMA_FRCTRL	.\Static_Code\IO_Map\MC56F82748.h	5212;"	d
PWMA_FSTS	.\Static_Code\IO_Map\MC56F82748.h	5240;"	d
PWMA_FSTS0	.\Static_Code\IO_Map\MC56F82748.h	5188;"	d
PWMA_FSTS0_VALUE	.\Generated_Code\PWMA_Config.h	463;"	d
PWMA_FSTS1	.\Static_Code\IO_Map\MC56F82748.h	5192;"	d
PWMA_FSTS1_VALUE	.\Generated_Code\PWMA_Config.h	461;"	d
PWMA_FTST	.\Static_Code\IO_Map\MC56F82748.h	5242;"	d
PWMA_FTST0	.\Static_Code\IO_Map\MC56F82748.h	5190;"	d
PWMA_FTST0_VALUE	.\Generated_Code\PWMA_Config.h	478;"	d
PWMA_FTST1	.\Static_Code\IO_Map\MC56F82748.h	5194;"	d
PWMA_FTST1_VALUE	.\Generated_Code\PWMA_Config.h	480;"	d
PWMA_H_	.\Generated_Code\PWMA.h	370;"	d
PWMA_INIT	.\Static_Code\IO_Map\MC56F82748.h	5198;"	d
PWMA_INTEN	.\Static_Code\IO_Map\MC56F82748.h	5215;"	d
PWMA_Init	.\Generated_Code\PWMA.h	377;"	d
PWMA_Init	.\Static_Code\Peripherals\PWMA_Init.c	/^void PWMA_Init(void) {$/;"	f
PWMA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5182;"	d
PWMA_MASK_MASK	.\Generated_Code\PWMA_Config.h	439;"	d
PWMA_MASK_VALUE	.\Generated_Code\PWMA_Config.h	438;"	d
PWMA_MCTRL	.\Static_Code\IO_Map\MC56F82748.h	5185;"	d
PWMA_MCTRL2	.\Static_Code\IO_Map\MC56F82748.h	5186;"	d
PWMA_MCTRL2_VALUE	.\Generated_Code\PWMA_Config.h	447;"	d
PWMA_MCTRL_MASK_1	.\Generated_Code\PWMA_Config.h	376;"	d
PWMA_MCTRL_MASK_2	.\Generated_Code\PWMA_Config.h	459;"	d
PWMA_MCTRL_MASK_3	.\Generated_Code\PWMA_Config.h	470;"	d
PWMA_MCTRL_VALUE_1	.\Generated_Code\PWMA_Config.h	375;"	d
PWMA_MCTRL_VALUE_2	.\Generated_Code\PWMA_Config.h	458;"	d
PWMA_MCTRL_VALUE_3	.\Generated_Code\PWMA_Config.h	469;"	d
PWMA_OCTRL	.\Static_Code\IO_Map\MC56F82748.h	5213;"	d
PWMA_OUTEN	.\Static_Code\IO_Map\MC56F82748.h	5181;"	d
PWMA_OUTEN_MASK	.\Generated_Code\PWMA_Config.h	450;"	d
PWMA_OUTEN_VALUE	.\Generated_Code\PWMA_Config.h	449;"	d
PWMA_SM0CAPTCOMPA	.\Static_Code\IO_Map\MC56F82748.h	5035;"	d
PWMA_SM0CAPTCOMPA_VALUE	.\Generated_Code\PWMA_Config.h	426;"	d
PWMA_SM0CAPTCOMPB	.\Static_Code\IO_Map\MC56F82748.h	5037;"	d
PWMA_SM0CAPTCOMPB_VALUE	.\Generated_Code\PWMA_Config.h	428;"	d
PWMA_SM0CAPTCOMPX	.\Static_Code\IO_Map\MC56F82748.h	5039;"	d
PWMA_SM0CAPTCOMPX_VALUE	.\Generated_Code\PWMA_Config.h	430;"	d
PWMA_SM0CAPTCTRLA	.\Static_Code\IO_Map\MC56F82748.h	5034;"	d
PWMA_SM0CAPTCTRLA_VALUE	.\Generated_Code\PWMA_Config.h	452;"	d
PWMA_SM0CAPTCTRLB	.\Static_Code\IO_Map\MC56F82748.h	5036;"	d
PWMA_SM0CAPTCTRLB_VALUE	.\Generated_Code\PWMA_Config.h	454;"	d
PWMA_SM0CAPTCTRLX	.\Static_Code\IO_Map\MC56F82748.h	5038;"	d
PWMA_SM0CAPTCTRLX_VALUE	.\Generated_Code\PWMA_Config.h	456;"	d
PWMA_SM0CNT	.\Static_Code\IO_Map\MC56F82748.h	5009;"	d
PWMA_SM0CTRL	.\Static_Code\IO_Map\MC56F82748.h	5012;"	d
PWMA_SM0CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5011;"	d
PWMA_SM0CTRL2_VALUE	.\Generated_Code\PWMA_Config.h	388;"	d
PWMA_SM0CTRL_VALUE	.\Generated_Code\PWMA_Config.h	390;"	d
PWMA_SM0CVAL0	.\Static_Code\IO_Map\MC56F82748.h	5040;"	d
PWMA_SM0CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	5041;"	d
PWMA_SM0CVAL1	.\Static_Code\IO_Map\MC56F82748.h	5042;"	d
PWMA_SM0CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	5043;"	d
PWMA_SM0CVAL2	.\Static_Code\IO_Map\MC56F82748.h	5044;"	d
PWMA_SM0CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	5045;"	d
PWMA_SM0CVAL3	.\Static_Code\IO_Map\MC56F82748.h	5046;"	d
PWMA_SM0CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	5047;"	d
PWMA_SM0CVAL4	.\Static_Code\IO_Map\MC56F82748.h	5048;"	d
PWMA_SM0CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	5049;"	d
PWMA_SM0CVAL5	.\Static_Code\IO_Map\MC56F82748.h	5050;"	d
PWMA_SM0CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	5051;"	d
PWMA_SM0DISMAP0	.\Static_Code\IO_Map\MC56F82748.h	5030;"	d
PWMA_SM0DISMAP0_VALUE	.\Generated_Code\PWMA_Config.h	418;"	d
PWMA_SM0DISMAP1	.\Static_Code\IO_Map\MC56F82748.h	5031;"	d
PWMA_SM0DISMAP1_VALUE	.\Generated_Code\PWMA_Config.h	420;"	d
PWMA_SM0DMAEN	.\Static_Code\IO_Map\MC56F82748.h	5028;"	d
PWMA_SM0DMAEN_VALUE	.\Generated_Code\PWMA_Config.h	476;"	d
PWMA_SM0DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	5032;"	d
PWMA_SM0DTCNT0_VALUE	.\Generated_Code\PWMA_Config.h	422;"	d
PWMA_SM0DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	5033;"	d
PWMA_SM0DTCNT1_VALUE	.\Generated_Code\PWMA_Config.h	424;"	d
PWMA_SM0FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	5014;"	d
PWMA_SM0FRACVAL1_VALUE	.\Generated_Code\PWMA_Config.h	406;"	d
PWMA_SM0FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	5016;"	d
PWMA_SM0FRACVAL2_VALUE	.\Generated_Code\PWMA_Config.h	408;"	d
PWMA_SM0FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	5018;"	d
PWMA_SM0FRACVAL3_VALUE	.\Generated_Code\PWMA_Config.h	410;"	d
PWMA_SM0FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	5020;"	d
PWMA_SM0FRACVAL4_VALUE	.\Generated_Code\PWMA_Config.h	412;"	d
PWMA_SM0FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	5022;"	d
PWMA_SM0FRACVAL5_VALUE	.\Generated_Code\PWMA_Config.h	414;"	d
PWMA_SM0FRCTRL	.\Static_Code\IO_Map\MC56F82748.h	5024;"	d
PWMA_SM0FRCTRL_VALUE	.\Generated_Code\PWMA_Config.h	416;"	d
PWMA_SM0INIT	.\Static_Code\IO_Map\MC56F82748.h	5010;"	d
PWMA_SM0INIT_VALUE	.\Generated_Code\PWMA_Config.h	386;"	d
PWMA_SM0INTEN	.\Static_Code\IO_Map\MC56F82748.h	5027;"	d
PWMA_SM0INTEN_VALUE_1	.\Generated_Code\PWMA_Config.h	378;"	d
PWMA_SM0INTEN_VALUE_2	.\Generated_Code\PWMA_Config.h	474;"	d
PWMA_SM0OCTRL	.\Static_Code\IO_Map\MC56F82748.h	5025;"	d
PWMA_SM0OCTRL_VALUE	.\Generated_Code\PWMA_Config.h	384;"	d
PWMA_SM0STS	.\Static_Code\IO_Map\MC56F82748.h	5026;"	d
PWMA_SM0STS_VALUE	.\Generated_Code\PWMA_Config.h	472;"	d
PWMA_SM0TCTRL	.\Static_Code\IO_Map\MC56F82748.h	5029;"	d
PWMA_SM0TCTRL_VALUE	.\Generated_Code\PWMA_Config.h	392;"	d
PWMA_SM0VAL0	.\Static_Code\IO_Map\MC56F82748.h	5013;"	d
PWMA_SM0VAL0_VALUE	.\Generated_Code\PWMA_Config.h	394;"	d
PWMA_SM0VAL1	.\Static_Code\IO_Map\MC56F82748.h	5015;"	d
PWMA_SM0VAL1_VALUE	.\Generated_Code\PWMA_Config.h	396;"	d
PWMA_SM0VAL2	.\Static_Code\IO_Map\MC56F82748.h	5017;"	d
PWMA_SM0VAL2_VALUE	.\Generated_Code\PWMA_Config.h	398;"	d
PWMA_SM0VAL3	.\Static_Code\IO_Map\MC56F82748.h	5019;"	d
PWMA_SM0VAL3_VALUE	.\Generated_Code\PWMA_Config.h	400;"	d
PWMA_SM0VAL4	.\Static_Code\IO_Map\MC56F82748.h	5021;"	d
PWMA_SM0VAL4_VALUE	.\Generated_Code\PWMA_Config.h	402;"	d
PWMA_SM0VAL5	.\Static_Code\IO_Map\MC56F82748.h	5023;"	d
PWMA_SM0VAL5_VALUE	.\Generated_Code\PWMA_Config.h	404;"	d
PWMA_SM1CAPTCOMPA	.\Static_Code\IO_Map\MC56F82748.h	5078;"	d
PWMA_SM1CAPTCOMPB	.\Static_Code\IO_Map\MC56F82748.h	5080;"	d
PWMA_SM1CAPTCOMPX	.\Static_Code\IO_Map\MC56F82748.h	5082;"	d
PWMA_SM1CAPTCTRLA	.\Static_Code\IO_Map\MC56F82748.h	5077;"	d
PWMA_SM1CAPTCTRLB	.\Static_Code\IO_Map\MC56F82748.h	5079;"	d
PWMA_SM1CAPTCTRLX	.\Static_Code\IO_Map\MC56F82748.h	5081;"	d
PWMA_SM1CNT	.\Static_Code\IO_Map\MC56F82748.h	5052;"	d
PWMA_SM1CTRL	.\Static_Code\IO_Map\MC56F82748.h	5055;"	d
PWMA_SM1CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5054;"	d
PWMA_SM1CVAL0	.\Static_Code\IO_Map\MC56F82748.h	5083;"	d
PWMA_SM1CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	5084;"	d
PWMA_SM1CVAL1	.\Static_Code\IO_Map\MC56F82748.h	5085;"	d
PWMA_SM1CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	5086;"	d
PWMA_SM1CVAL2	.\Static_Code\IO_Map\MC56F82748.h	5087;"	d
PWMA_SM1CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	5088;"	d
PWMA_SM1CVAL3	.\Static_Code\IO_Map\MC56F82748.h	5089;"	d
PWMA_SM1CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	5090;"	d
PWMA_SM1CVAL4	.\Static_Code\IO_Map\MC56F82748.h	5091;"	d
PWMA_SM1CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	5092;"	d
PWMA_SM1CVAL5	.\Static_Code\IO_Map\MC56F82748.h	5093;"	d
PWMA_SM1CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	5094;"	d
PWMA_SM1DISMAP0	.\Static_Code\IO_Map\MC56F82748.h	5073;"	d
PWMA_SM1DISMAP1	.\Static_Code\IO_Map\MC56F82748.h	5074;"	d
PWMA_SM1DMAEN	.\Static_Code\IO_Map\MC56F82748.h	5071;"	d
PWMA_SM1DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	5075;"	d
PWMA_SM1DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	5076;"	d
PWMA_SM1FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	5057;"	d
PWMA_SM1FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	5059;"	d
PWMA_SM1FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	5061;"	d
PWMA_SM1FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	5063;"	d
PWMA_SM1FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	5065;"	d
PWMA_SM1FRCTRL	.\Static_Code\IO_Map\MC56F82748.h	5067;"	d
PWMA_SM1INIT	.\Static_Code\IO_Map\MC56F82748.h	5053;"	d
PWMA_SM1INTEN	.\Static_Code\IO_Map\MC56F82748.h	5070;"	d
PWMA_SM1OCTRL	.\Static_Code\IO_Map\MC56F82748.h	5068;"	d
PWMA_SM1STS	.\Static_Code\IO_Map\MC56F82748.h	5069;"	d
PWMA_SM1TCTRL	.\Static_Code\IO_Map\MC56F82748.h	5072;"	d
PWMA_SM1VAL0	.\Static_Code\IO_Map\MC56F82748.h	5056;"	d
PWMA_SM1VAL1	.\Static_Code\IO_Map\MC56F82748.h	5058;"	d
PWMA_SM1VAL2	.\Static_Code\IO_Map\MC56F82748.h	5060;"	d
PWMA_SM1VAL3	.\Static_Code\IO_Map\MC56F82748.h	5062;"	d
PWMA_SM1VAL4	.\Static_Code\IO_Map\MC56F82748.h	5064;"	d
PWMA_SM1VAL5	.\Static_Code\IO_Map\MC56F82748.h	5066;"	d
PWMA_SM2CAPTCOMPA	.\Static_Code\IO_Map\MC56F82748.h	5121;"	d
PWMA_SM2CAPTCOMPB	.\Static_Code\IO_Map\MC56F82748.h	5123;"	d
PWMA_SM2CAPTCOMPX	.\Static_Code\IO_Map\MC56F82748.h	5125;"	d
PWMA_SM2CAPTCTRLA	.\Static_Code\IO_Map\MC56F82748.h	5120;"	d
PWMA_SM2CAPTCTRLB	.\Static_Code\IO_Map\MC56F82748.h	5122;"	d
PWMA_SM2CAPTCTRLX	.\Static_Code\IO_Map\MC56F82748.h	5124;"	d
PWMA_SM2CNT	.\Static_Code\IO_Map\MC56F82748.h	5095;"	d
PWMA_SM2CTRL	.\Static_Code\IO_Map\MC56F82748.h	5098;"	d
PWMA_SM2CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5097;"	d
PWMA_SM2CVAL0	.\Static_Code\IO_Map\MC56F82748.h	5126;"	d
PWMA_SM2CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	5127;"	d
PWMA_SM2CVAL1	.\Static_Code\IO_Map\MC56F82748.h	5128;"	d
PWMA_SM2CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	5129;"	d
PWMA_SM2CVAL2	.\Static_Code\IO_Map\MC56F82748.h	5130;"	d
PWMA_SM2CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	5131;"	d
PWMA_SM2CVAL3	.\Static_Code\IO_Map\MC56F82748.h	5132;"	d
PWMA_SM2CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	5133;"	d
PWMA_SM2CVAL4	.\Static_Code\IO_Map\MC56F82748.h	5134;"	d
PWMA_SM2CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	5135;"	d
PWMA_SM2CVAL5	.\Static_Code\IO_Map\MC56F82748.h	5136;"	d
PWMA_SM2CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	5137;"	d
PWMA_SM2DISMAP0	.\Static_Code\IO_Map\MC56F82748.h	5116;"	d
PWMA_SM2DISMAP1	.\Static_Code\IO_Map\MC56F82748.h	5117;"	d
PWMA_SM2DMAEN	.\Static_Code\IO_Map\MC56F82748.h	5114;"	d
PWMA_SM2DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	5118;"	d
PWMA_SM2DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	5119;"	d
PWMA_SM2FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	5100;"	d
PWMA_SM2FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	5102;"	d
PWMA_SM2FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	5104;"	d
PWMA_SM2FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	5106;"	d
PWMA_SM2FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	5108;"	d
PWMA_SM2FRCTRL	.\Static_Code\IO_Map\MC56F82748.h	5110;"	d
PWMA_SM2INIT	.\Static_Code\IO_Map\MC56F82748.h	5096;"	d
PWMA_SM2INTEN	.\Static_Code\IO_Map\MC56F82748.h	5113;"	d
PWMA_SM2OCTRL	.\Static_Code\IO_Map\MC56F82748.h	5111;"	d
PWMA_SM2STS	.\Static_Code\IO_Map\MC56F82748.h	5112;"	d
PWMA_SM2TCTRL	.\Static_Code\IO_Map\MC56F82748.h	5115;"	d
PWMA_SM2VAL0	.\Static_Code\IO_Map\MC56F82748.h	5099;"	d
PWMA_SM2VAL1	.\Static_Code\IO_Map\MC56F82748.h	5101;"	d
PWMA_SM2VAL2	.\Static_Code\IO_Map\MC56F82748.h	5103;"	d
PWMA_SM2VAL3	.\Static_Code\IO_Map\MC56F82748.h	5105;"	d
PWMA_SM2VAL4	.\Static_Code\IO_Map\MC56F82748.h	5107;"	d
PWMA_SM2VAL5	.\Static_Code\IO_Map\MC56F82748.h	5109;"	d
PWMA_SM3CAPTCOMPA	.\Static_Code\IO_Map\MC56F82748.h	5164;"	d
PWMA_SM3CAPTCOMPB	.\Static_Code\IO_Map\MC56F82748.h	5166;"	d
PWMA_SM3CAPTCOMPX	.\Static_Code\IO_Map\MC56F82748.h	5168;"	d
PWMA_SM3CAPTCTRLA	.\Static_Code\IO_Map\MC56F82748.h	5163;"	d
PWMA_SM3CAPTCTRLB	.\Static_Code\IO_Map\MC56F82748.h	5165;"	d
PWMA_SM3CAPTCTRLX	.\Static_Code\IO_Map\MC56F82748.h	5167;"	d
PWMA_SM3CNT	.\Static_Code\IO_Map\MC56F82748.h	5138;"	d
PWMA_SM3CTRL	.\Static_Code\IO_Map\MC56F82748.h	5141;"	d
PWMA_SM3CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5140;"	d
PWMA_SM3CVAL0	.\Static_Code\IO_Map\MC56F82748.h	5169;"	d
PWMA_SM3CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	5170;"	d
PWMA_SM3CVAL1	.\Static_Code\IO_Map\MC56F82748.h	5171;"	d
PWMA_SM3CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	5172;"	d
PWMA_SM3CVAL2	.\Static_Code\IO_Map\MC56F82748.h	5173;"	d
PWMA_SM3CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	5174;"	d
PWMA_SM3CVAL3	.\Static_Code\IO_Map\MC56F82748.h	5175;"	d
PWMA_SM3CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	5176;"	d
PWMA_SM3CVAL4	.\Static_Code\IO_Map\MC56F82748.h	5177;"	d
PWMA_SM3CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	5178;"	d
PWMA_SM3CVAL5	.\Static_Code\IO_Map\MC56F82748.h	5179;"	d
PWMA_SM3CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	5180;"	d
PWMA_SM3DISMAP0	.\Static_Code\IO_Map\MC56F82748.h	5159;"	d
PWMA_SM3DISMAP1	.\Static_Code\IO_Map\MC56F82748.h	5160;"	d
PWMA_SM3DMAEN	.\Static_Code\IO_Map\MC56F82748.h	5157;"	d
PWMA_SM3DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	5161;"	d
PWMA_SM3DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	5162;"	d
PWMA_SM3FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	5143;"	d
PWMA_SM3FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	5145;"	d
PWMA_SM3FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	5147;"	d
PWMA_SM3FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	5149;"	d
PWMA_SM3FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	5151;"	d
PWMA_SM3FRCTRL	.\Static_Code\IO_Map\MC56F82748.h	5153;"	d
PWMA_SM3INIT	.\Static_Code\IO_Map\MC56F82748.h	5139;"	d
PWMA_SM3INTEN	.\Static_Code\IO_Map\MC56F82748.h	5156;"	d
PWMA_SM3OCTRL	.\Static_Code\IO_Map\MC56F82748.h	5154;"	d
PWMA_SM3STS	.\Static_Code\IO_Map\MC56F82748.h	5155;"	d
PWMA_SM3TCTRL	.\Static_Code\IO_Map\MC56F82748.h	5158;"	d
PWMA_SM3VAL0	.\Static_Code\IO_Map\MC56F82748.h	5142;"	d
PWMA_SM3VAL1	.\Static_Code\IO_Map\MC56F82748.h	5144;"	d
PWMA_SM3VAL2	.\Static_Code\IO_Map\MC56F82748.h	5146;"	d
PWMA_SM3VAL3	.\Static_Code\IO_Map\MC56F82748.h	5148;"	d
PWMA_SM3VAL4	.\Static_Code\IO_Map\MC56F82748.h	5150;"	d
PWMA_SM3VAL5	.\Static_Code\IO_Map\MC56F82748.h	5152;"	d
PWMA_STS	.\Static_Code\IO_Map\MC56F82748.h	5214;"	d
PWMA_SWCOUT	.\Static_Code\IO_Map\MC56F82748.h	5183;"	d
PWMA_SWCOUT_MASK	.\Generated_Code\PWMA_Config.h	442;"	d
PWMA_SWCOUT_VALUE	.\Generated_Code\PWMA_Config.h	441;"	d
PWMA_TCTRL	.\Static_Code\IO_Map\MC56F82748.h	5217;"	d
PWMA_VAL0	.\Static_Code\IO_Map\MC56F82748.h	5201;"	d
PWMA_VAL1	.\Static_Code\IO_Map\MC56F82748.h	5203;"	d
PWMA_VAL2	.\Static_Code\IO_Map\MC56F82748.h	5205;"	d
PWMA_VAL3	.\Static_Code\IO_Map\MC56F82748.h	5207;"	d
PWMA_VAL4	.\Static_Code\IO_Map\MC56F82748.h	5209;"	d
PWMA_VAL5	.\Static_Code\IO_Map\MC56F82748.h	5211;"	d
PWM_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	4995;"	d
PWM_CAPTCOMPA_EDGCMPA	.\Static_Code\IO_Map\MC56F82748.h	4751;"	d
PWM_CAPTCOMPA_EDGCMPA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4749;"	d
PWM_CAPTCOMPA_EDGCMPA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4750;"	d
PWM_CAPTCOMPA_EDGCNTA	.\Static_Code\IO_Map\MC56F82748.h	4754;"	d
PWM_CAPTCOMPA_EDGCNTA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4752;"	d
PWM_CAPTCOMPA_EDGCNTA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4753;"	d
PWM_CAPTCOMPA_REG	.\Static_Code\IO_Map\MC56F82748.h	4450;"	d
PWM_CAPTCOMPB_EDGCMPB	.\Static_Code\IO_Map\MC56F82748.h	4782;"	d
PWM_CAPTCOMPB_EDGCMPB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4780;"	d
PWM_CAPTCOMPB_EDGCMPB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4781;"	d
PWM_CAPTCOMPB_EDGCNTB	.\Static_Code\IO_Map\MC56F82748.h	4785;"	d
PWM_CAPTCOMPB_EDGCNTB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4783;"	d
PWM_CAPTCOMPB_EDGCNTB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4784;"	d
PWM_CAPTCOMPB_REG	.\Static_Code\IO_Map\MC56F82748.h	4452;"	d
PWM_CAPTCOMPX_EDGCMPX	.\Static_Code\IO_Map\MC56F82748.h	4813;"	d
PWM_CAPTCOMPX_EDGCMPX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4811;"	d
PWM_CAPTCOMPX_EDGCMPX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4812;"	d
PWM_CAPTCOMPX_EDGCNTX	.\Static_Code\IO_Map\MC56F82748.h	4816;"	d
PWM_CAPTCOMPX_EDGCNTX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4814;"	d
PWM_CAPTCOMPX_EDGCNTX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4815;"	d
PWM_CAPTCOMPX_REG	.\Static_Code\IO_Map\MC56F82748.h	4454;"	d
PWM_CAPTCTRLA_ARMA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4725;"	d
PWM_CAPTCTRLA_ARMA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4726;"	d
PWM_CAPTCTRLA_CA0CNT	.\Static_Code\IO_Map\MC56F82748.h	4744;"	d
PWM_CAPTCTRLA_CA0CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4742;"	d
PWM_CAPTCTRLA_CA0CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4743;"	d
PWM_CAPTCTRLA_CA1CNT	.\Static_Code\IO_Map\MC56F82748.h	4747;"	d
PWM_CAPTCTRLA_CA1CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4745;"	d
PWM_CAPTCTRLA_CA1CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4746;"	d
PWM_CAPTCTRLA_CFAWM	.\Static_Code\IO_Map\MC56F82748.h	4741;"	d
PWM_CAPTCTRLA_CFAWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	4739;"	d
PWM_CAPTCTRLA_CFAWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4740;"	d
PWM_CAPTCTRLA_EDGA0	.\Static_Code\IO_Map\MC56F82748.h	4731;"	d
PWM_CAPTCTRLA_EDGA0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4729;"	d
PWM_CAPTCTRLA_EDGA0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4730;"	d
PWM_CAPTCTRLA_EDGA1	.\Static_Code\IO_Map\MC56F82748.h	4734;"	d
PWM_CAPTCTRLA_EDGA1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4732;"	d
PWM_CAPTCTRLA_EDGA1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4733;"	d
PWM_CAPTCTRLA_EDGCNTA_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4737;"	d
PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4738;"	d
PWM_CAPTCTRLA_INP_SELA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4735;"	d
PWM_CAPTCTRLA_INP_SELA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4736;"	d
PWM_CAPTCTRLA_ONESHOTA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4727;"	d
PWM_CAPTCTRLA_ONESHOTA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4728;"	d
PWM_CAPTCTRLA_REG	.\Static_Code\IO_Map\MC56F82748.h	4449;"	d
PWM_CAPTCTRLB_ARMB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4756;"	d
PWM_CAPTCTRLB_ARMB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4757;"	d
PWM_CAPTCTRLB_CB0CNT	.\Static_Code\IO_Map\MC56F82748.h	4775;"	d
PWM_CAPTCTRLB_CB0CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4773;"	d
PWM_CAPTCTRLB_CB0CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4774;"	d
PWM_CAPTCTRLB_CB1CNT	.\Static_Code\IO_Map\MC56F82748.h	4778;"	d
PWM_CAPTCTRLB_CB1CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4776;"	d
PWM_CAPTCTRLB_CB1CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4777;"	d
PWM_CAPTCTRLB_CFBWM	.\Static_Code\IO_Map\MC56F82748.h	4772;"	d
PWM_CAPTCTRLB_CFBWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	4770;"	d
PWM_CAPTCTRLB_CFBWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4771;"	d
PWM_CAPTCTRLB_EDGB0	.\Static_Code\IO_Map\MC56F82748.h	4762;"	d
PWM_CAPTCTRLB_EDGB0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4760;"	d
PWM_CAPTCTRLB_EDGB0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4761;"	d
PWM_CAPTCTRLB_EDGB1	.\Static_Code\IO_Map\MC56F82748.h	4765;"	d
PWM_CAPTCTRLB_EDGB1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4763;"	d
PWM_CAPTCTRLB_EDGB1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4764;"	d
PWM_CAPTCTRLB_EDGCNTB_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4768;"	d
PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4769;"	d
PWM_CAPTCTRLB_INP_SELB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4766;"	d
PWM_CAPTCTRLB_INP_SELB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4767;"	d
PWM_CAPTCTRLB_ONESHOTB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4758;"	d
PWM_CAPTCTRLB_ONESHOTB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4759;"	d
PWM_CAPTCTRLB_REG	.\Static_Code\IO_Map\MC56F82748.h	4451;"	d
PWM_CAPTCTRLX_ARMX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4787;"	d
PWM_CAPTCTRLX_ARMX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4788;"	d
PWM_CAPTCTRLX_CFXWM	.\Static_Code\IO_Map\MC56F82748.h	4803;"	d
PWM_CAPTCTRLX_CFXWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	4801;"	d
PWM_CAPTCTRLX_CFXWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4802;"	d
PWM_CAPTCTRLX_CX0CNT	.\Static_Code\IO_Map\MC56F82748.h	4806;"	d
PWM_CAPTCTRLX_CX0CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4804;"	d
PWM_CAPTCTRLX_CX0CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4805;"	d
PWM_CAPTCTRLX_CX1CNT	.\Static_Code\IO_Map\MC56F82748.h	4809;"	d
PWM_CAPTCTRLX_CX1CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4807;"	d
PWM_CAPTCTRLX_CX1CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4808;"	d
PWM_CAPTCTRLX_EDGCNTX_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4799;"	d
PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4800;"	d
PWM_CAPTCTRLX_EDGX0	.\Static_Code\IO_Map\MC56F82748.h	4793;"	d
PWM_CAPTCTRLX_EDGX0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4791;"	d
PWM_CAPTCTRLX_EDGX0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4792;"	d
PWM_CAPTCTRLX_EDGX1	.\Static_Code\IO_Map\MC56F82748.h	4796;"	d
PWM_CAPTCTRLX_EDGX1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4794;"	d
PWM_CAPTCTRLX_EDGX1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4795;"	d
PWM_CAPTCTRLX_INP_SELX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4797;"	d
PWM_CAPTCTRLX_INP_SELX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4798;"	d
PWM_CAPTCTRLX_ONESHOTX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4789;"	d
PWM_CAPTCTRLX_ONESHOTX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4790;"	d
PWM_CAPTCTRLX_REG	.\Static_Code\IO_Map\MC56F82748.h	4453;"	d
PWM_CNT_CNT	.\Static_Code\IO_Map\MC56F82748.h	4495;"	d
PWM_CNT_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4493;"	d
PWM_CNT_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4494;"	d
PWM_CNT_REG	.\Static_Code\IO_Map\MC56F82748.h	4425;"	d
PWM_CTRL2_CLK_SEL	.\Static_Code\IO_Map\MC56F82748.h	4503;"	d
PWM_CTRL2_CLK_SEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4501;"	d
PWM_CTRL2_CLK_SEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4502;"	d
PWM_CTRL2_DBGEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4526;"	d
PWM_CTRL2_DBGEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4527;"	d
PWM_CTRL2_FORCE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4509;"	d
PWM_CTRL2_FORCE_SEL	.\Static_Code\IO_Map\MC56F82748.h	4508;"	d
PWM_CTRL2_FORCE_SEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4506;"	d
PWM_CTRL2_FORCE_SEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4507;"	d
PWM_CTRL2_FORCE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4510;"	d
PWM_CTRL2_FRCEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4511;"	d
PWM_CTRL2_FRCEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4512;"	d
PWM_CTRL2_INDEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	4522;"	d
PWM_CTRL2_INDEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4523;"	d
PWM_CTRL2_INIT_SEL	.\Static_Code\IO_Map\MC56F82748.h	4515;"	d
PWM_CTRL2_INIT_SEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4513;"	d
PWM_CTRL2_INIT_SEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4514;"	d
PWM_CTRL2_PWM23_INIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4520;"	d
PWM_CTRL2_PWM23_INIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4521;"	d
PWM_CTRL2_PWM45_INIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4518;"	d
PWM_CTRL2_PWM45_INIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4519;"	d
PWM_CTRL2_PWMX_INIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4516;"	d
PWM_CTRL2_PWMX_INIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4517;"	d
PWM_CTRL2_REG	.\Static_Code\IO_Map\MC56F82748.h	4427;"	d
PWM_CTRL2_RELOAD_SEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4504;"	d
PWM_CTRL2_RELOAD_SEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4505;"	d
PWM_CTRL2_WAITEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4524;"	d
PWM_CTRL2_WAITEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4525;"	d
PWM_CTRL_DBLEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4529;"	d
PWM_CTRL_DBLEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4530;"	d
PWM_CTRL_DBLX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4531;"	d
PWM_CTRL_DBLX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4532;"	d
PWM_CTRL_DT	.\Static_Code\IO_Map\MC56F82748.h	4542;"	d
PWM_CTRL_DT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4540;"	d
PWM_CTRL_DT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4541;"	d
PWM_CTRL_FULL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4543;"	d
PWM_CTRL_FULL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4544;"	d
PWM_CTRL_HALF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4545;"	d
PWM_CTRL_HALF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4546;"	d
PWM_CTRL_LDFQ	.\Static_Code\IO_Map\MC56F82748.h	4549;"	d
PWM_CTRL_LDFQ_MASK	.\Static_Code\IO_Map\MC56F82748.h	4547;"	d
PWM_CTRL_LDFQ_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4548;"	d
PWM_CTRL_LDMOD_MASK	.\Static_Code\IO_Map\MC56F82748.h	4533;"	d
PWM_CTRL_LDMOD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4534;"	d
PWM_CTRL_PRSC	.\Static_Code\IO_Map\MC56F82748.h	4539;"	d
PWM_CTRL_PRSC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4537;"	d
PWM_CTRL_PRSC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4538;"	d
PWM_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4428;"	d
PWM_CTRL_SPLIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4535;"	d
PWM_CTRL_SPLIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4536;"	d
PWM_CVAL0CYC_CVAL0CYC	.\Static_Code\IO_Map\MC56F82748.h	4824;"	d
PWM_CVAL0CYC_CVAL0CYC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4822;"	d
PWM_CVAL0CYC_CVAL0CYC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4823;"	d
PWM_CVAL0CYC_REG	.\Static_Code\IO_Map\MC56F82748.h	4456;"	d
PWM_CVAL0_CAPTVAL0	.\Static_Code\IO_Map\MC56F82748.h	4820;"	d
PWM_CVAL0_CAPTVAL0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4818;"	d
PWM_CVAL0_CAPTVAL0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4819;"	d
PWM_CVAL0_REG	.\Static_Code\IO_Map\MC56F82748.h	4455;"	d
PWM_CVAL1CYC_CVAL1CYC	.\Static_Code\IO_Map\MC56F82748.h	4832;"	d
PWM_CVAL1CYC_CVAL1CYC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4830;"	d
PWM_CVAL1CYC_CVAL1CYC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4831;"	d
PWM_CVAL1CYC_REG	.\Static_Code\IO_Map\MC56F82748.h	4458;"	d
PWM_CVAL1_CAPTVAL1	.\Static_Code\IO_Map\MC56F82748.h	4828;"	d
PWM_CVAL1_CAPTVAL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4826;"	d
PWM_CVAL1_CAPTVAL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4827;"	d
PWM_CVAL1_REG	.\Static_Code\IO_Map\MC56F82748.h	4457;"	d
PWM_CVAL2CYC_CVAL2CYC	.\Static_Code\IO_Map\MC56F82748.h	4840;"	d
PWM_CVAL2CYC_CVAL2CYC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4838;"	d
PWM_CVAL2CYC_CVAL2CYC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4839;"	d
PWM_CVAL2CYC_REG	.\Static_Code\IO_Map\MC56F82748.h	4460;"	d
PWM_CVAL2_CAPTVAL2	.\Static_Code\IO_Map\MC56F82748.h	4836;"	d
PWM_CVAL2_CAPTVAL2_MASK	.\Static_Code\IO_Map\MC56F82748.h	4834;"	d
PWM_CVAL2_CAPTVAL2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4835;"	d
PWM_CVAL2_REG	.\Static_Code\IO_Map\MC56F82748.h	4459;"	d
PWM_CVAL3CYC_CVAL3CYC	.\Static_Code\IO_Map\MC56F82748.h	4848;"	d
PWM_CVAL3CYC_CVAL3CYC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4846;"	d
PWM_CVAL3CYC_CVAL3CYC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4847;"	d
PWM_CVAL3CYC_REG	.\Static_Code\IO_Map\MC56F82748.h	4462;"	d
PWM_CVAL3_CAPTVAL3	.\Static_Code\IO_Map\MC56F82748.h	4844;"	d
PWM_CVAL3_CAPTVAL3_MASK	.\Static_Code\IO_Map\MC56F82748.h	4842;"	d
PWM_CVAL3_CAPTVAL3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4843;"	d
PWM_CVAL3_REG	.\Static_Code\IO_Map\MC56F82748.h	4461;"	d
PWM_CVAL4CYC_CVAL4CYC	.\Static_Code\IO_Map\MC56F82748.h	4856;"	d
PWM_CVAL4CYC_CVAL4CYC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4854;"	d
PWM_CVAL4CYC_CVAL4CYC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4855;"	d
PWM_CVAL4CYC_REG	.\Static_Code\IO_Map\MC56F82748.h	4464;"	d
PWM_CVAL4_CAPTVAL4	.\Static_Code\IO_Map\MC56F82748.h	4852;"	d
PWM_CVAL4_CAPTVAL4_MASK	.\Static_Code\IO_Map\MC56F82748.h	4850;"	d
PWM_CVAL4_CAPTVAL4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4851;"	d
PWM_CVAL4_REG	.\Static_Code\IO_Map\MC56F82748.h	4463;"	d
PWM_CVAL5CYC_CVAL5CYC	.\Static_Code\IO_Map\MC56F82748.h	4864;"	d
PWM_CVAL5CYC_CVAL5CYC_MASK	.\Static_Code\IO_Map\MC56F82748.h	4862;"	d
PWM_CVAL5CYC_CVAL5CYC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4863;"	d
PWM_CVAL5CYC_REG	.\Static_Code\IO_Map\MC56F82748.h	4466;"	d
PWM_CVAL5_CAPTVAL5	.\Static_Code\IO_Map\MC56F82748.h	4860;"	d
PWM_CVAL5_CAPTVAL5_MASK	.\Static_Code\IO_Map\MC56F82748.h	4858;"	d
PWM_CVAL5_CAPTVAL5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4859;"	d
PWM_CVAL5_REG	.\Static_Code\IO_Map\MC56F82748.h	4465;"	d
PWM_DISMAP_DIS0A	.\Static_Code\IO_Map\MC56F82748.h	4700;"	d
PWM_DISMAP_DIS0A_MASK	.\Static_Code\IO_Map\MC56F82748.h	4698;"	d
PWM_DISMAP_DIS0A_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4699;"	d
PWM_DISMAP_DIS0B	.\Static_Code\IO_Map\MC56F82748.h	4706;"	d
PWM_DISMAP_DIS0B_MASK	.\Static_Code\IO_Map\MC56F82748.h	4704;"	d
PWM_DISMAP_DIS0B_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4705;"	d
PWM_DISMAP_DIS0X	.\Static_Code\IO_Map\MC56F82748.h	4715;"	d
PWM_DISMAP_DIS0X_MASK	.\Static_Code\IO_Map\MC56F82748.h	4713;"	d
PWM_DISMAP_DIS0X_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4714;"	d
PWM_DISMAP_DIS1A	.\Static_Code\IO_Map\MC56F82748.h	4703;"	d
PWM_DISMAP_DIS1A_MASK	.\Static_Code\IO_Map\MC56F82748.h	4701;"	d
PWM_DISMAP_DIS1A_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4702;"	d
PWM_DISMAP_DIS1B	.\Static_Code\IO_Map\MC56F82748.h	4709;"	d
PWM_DISMAP_DIS1B_MASK	.\Static_Code\IO_Map\MC56F82748.h	4707;"	d
PWM_DISMAP_DIS1B_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4708;"	d
PWM_DISMAP_DIS1X	.\Static_Code\IO_Map\MC56F82748.h	4712;"	d
PWM_DISMAP_DIS1X_MASK	.\Static_Code\IO_Map\MC56F82748.h	4710;"	d
PWM_DISMAP_DIS1X_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4711;"	d
PWM_DISMAP_REG	.\Static_Code\IO_Map\MC56F82748.h	4446;"	d
PWM_DMAEN_CA0DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4678;"	d
PWM_DMAEN_CA0DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4679;"	d
PWM_DMAEN_CA1DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4680;"	d
PWM_DMAEN_CA1DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4681;"	d
PWM_DMAEN_CAPTDE	.\Static_Code\IO_Map\MC56F82748.h	4684;"	d
PWM_DMAEN_CAPTDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4682;"	d
PWM_DMAEN_CAPTDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4683;"	d
PWM_DMAEN_CB0DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4674;"	d
PWM_DMAEN_CB0DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4675;"	d
PWM_DMAEN_CB1DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4676;"	d
PWM_DMAEN_CB1DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4677;"	d
PWM_DMAEN_CX0DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4670;"	d
PWM_DMAEN_CX0DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4671;"	d
PWM_DMAEN_CX1DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4672;"	d
PWM_DMAEN_CX1DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4673;"	d
PWM_DMAEN_FAND_MASK	.\Static_Code\IO_Map\MC56F82748.h	4685;"	d
PWM_DMAEN_FAND_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4686;"	d
PWM_DMAEN_REG	.\Static_Code\IO_Map\MC56F82748.h	4444;"	d
PWM_DMAEN_VALDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4687;"	d
PWM_DMAEN_VALDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4688;"	d
PWM_DTCNT0_DTCNT0	.\Static_Code\IO_Map\MC56F82748.h	4719;"	d
PWM_DTCNT0_DTCNT0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4717;"	d
PWM_DTCNT0_DTCNT0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4718;"	d
PWM_DTCNT0_REG	.\Static_Code\IO_Map\MC56F82748.h	4447;"	d
PWM_DTCNT1_DTCNT1	.\Static_Code\IO_Map\MC56F82748.h	4723;"	d
PWM_DTCNT1_DTCNT1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4721;"	d
PWM_DTCNT1_DTCNT1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4722;"	d
PWM_DTCNT1_REG	.\Static_Code\IO_Map\MC56F82748.h	4448;"	d
PWM_DTSRCSEL_REG	.\Static_Code\IO_Map\MC56F82748.h	4470;"	d
PWM_DTSRCSEL_SM0SEL23	.\Static_Code\IO_Map\MC56F82748.h	4911;"	d
PWM_DTSRCSEL_SM0SEL23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4909;"	d
PWM_DTSRCSEL_SM0SEL23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4910;"	d
PWM_DTSRCSEL_SM0SEL45	.\Static_Code\IO_Map\MC56F82748.h	4908;"	d
PWM_DTSRCSEL_SM0SEL45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4906;"	d
PWM_DTSRCSEL_SM0SEL45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4907;"	d
PWM_DTSRCSEL_SM1SEL23	.\Static_Code\IO_Map\MC56F82748.h	4917;"	d
PWM_DTSRCSEL_SM1SEL23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4915;"	d
PWM_DTSRCSEL_SM1SEL23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4916;"	d
PWM_DTSRCSEL_SM1SEL45	.\Static_Code\IO_Map\MC56F82748.h	4914;"	d
PWM_DTSRCSEL_SM1SEL45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4912;"	d
PWM_DTSRCSEL_SM1SEL45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4913;"	d
PWM_DTSRCSEL_SM2SEL23	.\Static_Code\IO_Map\MC56F82748.h	4923;"	d
PWM_DTSRCSEL_SM2SEL23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4921;"	d
PWM_DTSRCSEL_SM2SEL23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4922;"	d
PWM_DTSRCSEL_SM2SEL45	.\Static_Code\IO_Map\MC56F82748.h	4920;"	d
PWM_DTSRCSEL_SM2SEL45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4918;"	d
PWM_DTSRCSEL_SM2SEL45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4919;"	d
PWM_DTSRCSEL_SM3SEL23	.\Static_Code\IO_Map\MC56F82748.h	4929;"	d
PWM_DTSRCSEL_SM3SEL23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4927;"	d
PWM_DTSRCSEL_SM3SEL23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4928;"	d
PWM_DTSRCSEL_SM3SEL45	.\Static_Code\IO_Map\MC56F82748.h	4926;"	d
PWM_DTSRCSEL_SM3SEL45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4924;"	d
PWM_DTSRCSEL_SM3SEL45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4925;"	d
PWM_FCTRL_FAUTO	.\Static_Code\IO_Map\MC56F82748.h	4956;"	d
PWM_FCTRL_FAUTO_MASK	.\Static_Code\IO_Map\MC56F82748.h	4954;"	d
PWM_FCTRL_FAUTO_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4955;"	d
PWM_FCTRL_FIE	.\Static_Code\IO_Map\MC56F82748.h	4950;"	d
PWM_FCTRL_FIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4948;"	d
PWM_FCTRL_FIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4949;"	d
PWM_FCTRL_FLVL	.\Static_Code\IO_Map\MC56F82748.h	4959;"	d
PWM_FCTRL_FLVL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4957;"	d
PWM_FCTRL_FLVL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4958;"	d
PWM_FCTRL_FSAFE	.\Static_Code\IO_Map\MC56F82748.h	4953;"	d
PWM_FCTRL_FSAFE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4951;"	d
PWM_FCTRL_FSAFE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4952;"	d
PWM_FCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4473;"	d
PWM_FFILT_FILT_CNT	.\Static_Code\IO_Map\MC56F82748.h	4979;"	d
PWM_FFILT_FILT_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4977;"	d
PWM_FFILT_FILT_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4978;"	d
PWM_FFILT_FILT_PER	.\Static_Code\IO_Map\MC56F82748.h	4976;"	d
PWM_FFILT_FILT_PER_MASK	.\Static_Code\IO_Map\MC56F82748.h	4974;"	d
PWM_FFILT_FILT_PER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4975;"	d
PWM_FFILT_GSTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	4980;"	d
PWM_FFILT_GSTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4981;"	d
PWM_FFILT_REG	.\Static_Code\IO_Map\MC56F82748.h	4475;"	d
PWM_FRACVAL1_FRACVAL1	.\Static_Code\IO_Map\MC56F82748.h	4557;"	d
PWM_FRACVAL1_FRACVAL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4555;"	d
PWM_FRACVAL1_FRACVAL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4556;"	d
PWM_FRACVAL1_REG	.\Static_Code\IO_Map\MC56F82748.h	4430;"	d
PWM_FRACVAL2_FRACVAL2	.\Static_Code\IO_Map\MC56F82748.h	4565;"	d
PWM_FRACVAL2_FRACVAL2_MASK	.\Static_Code\IO_Map\MC56F82748.h	4563;"	d
PWM_FRACVAL2_FRACVAL2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4564;"	d
PWM_FRACVAL2_REG	.\Static_Code\IO_Map\MC56F82748.h	4432;"	d
PWM_FRACVAL3_FRACVAL3	.\Static_Code\IO_Map\MC56F82748.h	4573;"	d
PWM_FRACVAL3_FRACVAL3_MASK	.\Static_Code\IO_Map\MC56F82748.h	4571;"	d
PWM_FRACVAL3_FRACVAL3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4572;"	d
PWM_FRACVAL3_REG	.\Static_Code\IO_Map\MC56F82748.h	4434;"	d
PWM_FRACVAL4_FRACVAL4	.\Static_Code\IO_Map\MC56F82748.h	4581;"	d
PWM_FRACVAL4_FRACVAL4_MASK	.\Static_Code\IO_Map\MC56F82748.h	4579;"	d
PWM_FRACVAL4_FRACVAL4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4580;"	d
PWM_FRACVAL4_REG	.\Static_Code\IO_Map\MC56F82748.h	4436;"	d
PWM_FRACVAL5_FRACVAL5	.\Static_Code\IO_Map\MC56F82748.h	4589;"	d
PWM_FRACVAL5_FRACVAL5_MASK	.\Static_Code\IO_Map\MC56F82748.h	4587;"	d
PWM_FRACVAL5_FRACVAL5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4588;"	d
PWM_FRACVAL5_REG	.\Static_Code\IO_Map\MC56F82748.h	4438;"	d
PWM_FRCTRL_FRAC1_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4595;"	d
PWM_FRCTRL_FRAC1_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4596;"	d
PWM_FRCTRL_FRAC23_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4597;"	d
PWM_FRCTRL_FRAC23_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4598;"	d
PWM_FRCTRL_FRAC45_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4599;"	d
PWM_FRCTRL_FRAC45_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4600;"	d
PWM_FRCTRL_FRAC_PU_MASK	.\Static_Code\IO_Map\MC56F82748.h	4601;"	d
PWM_FRCTRL_FRAC_PU_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4602;"	d
PWM_FRCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4440;"	d
PWM_FRCTRL_TEST_MASK	.\Static_Code\IO_Map\MC56F82748.h	4603;"	d
PWM_FRCTRL_TEST_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4604;"	d
PWM_FSTS_FFLAG	.\Static_Code\IO_Map\MC56F82748.h	4963;"	d
PWM_FSTS_FFLAG_MASK	.\Static_Code\IO_Map\MC56F82748.h	4961;"	d
PWM_FSTS_FFLAG_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4962;"	d
PWM_FSTS_FFPIN	.\Static_Code\IO_Map\MC56F82748.h	4969;"	d
PWM_FSTS_FFPIN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4967;"	d
PWM_FSTS_FFPIN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4968;"	d
PWM_FSTS_FFULL	.\Static_Code\IO_Map\MC56F82748.h	4966;"	d
PWM_FSTS_FFULL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4964;"	d
PWM_FSTS_FFULL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4965;"	d
PWM_FSTS_FHALF	.\Static_Code\IO_Map\MC56F82748.h	4972;"	d
PWM_FSTS_FHALF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4970;"	d
PWM_FSTS_FHALF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4971;"	d
PWM_FSTS_REG	.\Static_Code\IO_Map\MC56F82748.h	4474;"	d
PWM_FTST_FTEST_MASK	.\Static_Code\IO_Map\MC56F82748.h	4983;"	d
PWM_FTST_FTEST_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4984;"	d
PWM_FTST_REG	.\Static_Code\IO_Map\MC56F82748.h	4476;"	d
PWM_INIT_INIT	.\Static_Code\IO_Map\MC56F82748.h	4499;"	d
PWM_INIT_INIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	4497;"	d
PWM_INIT_INIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4498;"	d
PWM_INIT_REG	.\Static_Code\IO_Map\MC56F82748.h	4426;"	d
PWM_INTEN_CA0IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4661;"	d
PWM_INTEN_CA0IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4662;"	d
PWM_INTEN_CA1IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4663;"	d
PWM_INTEN_CA1IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4664;"	d
PWM_INTEN_CB0IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4657;"	d
PWM_INTEN_CB0IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4658;"	d
PWM_INTEN_CB1IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4659;"	d
PWM_INTEN_CB1IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4660;"	d
PWM_INTEN_CMPIE	.\Static_Code\IO_Map\MC56F82748.h	4652;"	d
PWM_INTEN_CMPIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4650;"	d
PWM_INTEN_CMPIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4651;"	d
PWM_INTEN_CX0IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4653;"	d
PWM_INTEN_CX0IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4654;"	d
PWM_INTEN_CX1IE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4655;"	d
PWM_INTEN_CX1IE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4656;"	d
PWM_INTEN_REG	.\Static_Code\IO_Map\MC56F82748.h	4443;"	d
PWM_INTEN_REIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4667;"	d
PWM_INTEN_REIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4668;"	d
PWM_INTEN_RIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4665;"	d
PWM_INTEN_RIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4666;"	d
PWM_MASK_MASKA	.\Static_Code\IO_Map\MC56F82748.h	4884;"	d
PWM_MASK_MASKA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4882;"	d
PWM_MASK_MASKA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4883;"	d
PWM_MASK_MASKB	.\Static_Code\IO_Map\MC56F82748.h	4881;"	d
PWM_MASK_MASKB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4879;"	d
PWM_MASK_MASKB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4880;"	d
PWM_MASK_MASKX	.\Static_Code\IO_Map\MC56F82748.h	4878;"	d
PWM_MASK_MASKX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4876;"	d
PWM_MASK_MASKX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4877;"	d
PWM_MASK_REG	.\Static_Code\IO_Map\MC56F82748.h	4468;"	d
PWM_MASK_UPDATE_MASK	.\Static_Code\IO_Map\MC56F82748.h	4887;"	d
PWM_MASK_UPDATE_MASK_MASK	.\Static_Code\IO_Map\MC56F82748.h	4885;"	d
PWM_MASK_UPDATE_MASK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4886;"	d
PWM_MCTRL2_MONPLL	.\Static_Code\IO_Map\MC56F82748.h	4946;"	d
PWM_MCTRL2_MONPLL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4944;"	d
PWM_MCTRL2_MONPLL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4945;"	d
PWM_MCTRL2_REG	.\Static_Code\IO_Map\MC56F82748.h	4472;"	d
PWM_MCTRL_CLDOK	.\Static_Code\IO_Map\MC56F82748.h	4936;"	d
PWM_MCTRL_CLDOK_MASK	.\Static_Code\IO_Map\MC56F82748.h	4934;"	d
PWM_MCTRL_CLDOK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4935;"	d
PWM_MCTRL_IPOL	.\Static_Code\IO_Map\MC56F82748.h	4942;"	d
PWM_MCTRL_IPOL_MASK	.\Static_Code\IO_Map\MC56F82748.h	4940;"	d
PWM_MCTRL_IPOL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4941;"	d
PWM_MCTRL_LDOK	.\Static_Code\IO_Map\MC56F82748.h	4933;"	d
PWM_MCTRL_LDOK_MASK	.\Static_Code\IO_Map\MC56F82748.h	4931;"	d
PWM_MCTRL_LDOK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4932;"	d
PWM_MCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4471;"	d
PWM_MCTRL_RUN	.\Static_Code\IO_Map\MC56F82748.h	4939;"	d
PWM_MCTRL_RUN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4937;"	d
PWM_MCTRL_RUN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4938;"	d
PWM_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct PWM_MemMap {$/;"	s
PWM_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *PWM_MemMapPtr;$/;"	t
PWM_OCTRL_POLA_MASK	.\Static_Code\IO_Map\MC56F82748.h	4619;"	d
PWM_OCTRL_POLA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4620;"	d
PWM_OCTRL_POLB_MASK	.\Static_Code\IO_Map\MC56F82748.h	4617;"	d
PWM_OCTRL_POLB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4618;"	d
PWM_OCTRL_POLX_MASK	.\Static_Code\IO_Map\MC56F82748.h	4615;"	d
PWM_OCTRL_POLX_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4616;"	d
PWM_OCTRL_PWMAFS	.\Static_Code\IO_Map\MC56F82748.h	4614;"	d
PWM_OCTRL_PWMAFS_MASK	.\Static_Code\IO_Map\MC56F82748.h	4612;"	d
PWM_OCTRL_PWMAFS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4613;"	d
PWM_OCTRL_PWMA_IN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4625;"	d
PWM_OCTRL_PWMA_IN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4626;"	d
PWM_OCTRL_PWMBFS	.\Static_Code\IO_Map\MC56F82748.h	4611;"	d
PWM_OCTRL_PWMBFS_MASK	.\Static_Code\IO_Map\MC56F82748.h	4609;"	d
PWM_OCTRL_PWMBFS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4610;"	d
PWM_OCTRL_PWMB_IN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4623;"	d
PWM_OCTRL_PWMB_IN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4624;"	d
PWM_OCTRL_PWMXFS	.\Static_Code\IO_Map\MC56F82748.h	4608;"	d
PWM_OCTRL_PWMXFS_MASK	.\Static_Code\IO_Map\MC56F82748.h	4606;"	d
PWM_OCTRL_PWMXFS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4607;"	d
PWM_OCTRL_PWMX_IN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4621;"	d
PWM_OCTRL_PWMX_IN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4622;"	d
PWM_OCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4441;"	d
PWM_OUTEN_PWMA_EN	.\Static_Code\IO_Map\MC56F82748.h	4874;"	d
PWM_OUTEN_PWMA_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4872;"	d
PWM_OUTEN_PWMA_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4873;"	d
PWM_OUTEN_PWMB_EN	.\Static_Code\IO_Map\MC56F82748.h	4871;"	d
PWM_OUTEN_PWMB_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4869;"	d
PWM_OUTEN_PWMB_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4870;"	d
PWM_OUTEN_PWMX_EN	.\Static_Code\IO_Map\MC56F82748.h	4868;"	d
PWM_OUTEN_PWMX_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4866;"	d
PWM_OUTEN_PWMX_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4867;"	d
PWM_OUTEN_REG	.\Static_Code\IO_Map\MC56F82748.h	4467;"	d
PWM_PDD_AUTOMATIC_CLEARING	.\Static_Code\PDD\PWM_PDD.h	318;"	d
PWM_PDD_AUX_CLK	.\Static_Code\PDD\PWM_PDD.h	249;"	d
PWM_PDD_BUS_CLK	.\Static_Code\PDD\PWM_PDD.h	247;"	d
PWM_PDD_CAPTUREA0_FLAG	.\Static_Code\PDD\PWM_PDD.h	44;"	d
PWM_PDD_CAPTUREA0_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	60;"	d
PWM_PDD_CAPTUREA1_FLAG	.\Static_Code\PDD\PWM_PDD.h	45;"	d
PWM_PDD_CAPTUREA1_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	61;"	d
PWM_PDD_CAPTUREB0_FLAG	.\Static_Code\PDD\PWM_PDD.h	46;"	d
PWM_PDD_CAPTUREB0_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	62;"	d
PWM_PDD_CAPTUREB1_FLAG	.\Static_Code\PDD\PWM_PDD.h	47;"	d
PWM_PDD_CAPTUREB1_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	63;"	d
PWM_PDD_CAPTUREX0_FLAG	.\Static_Code\PDD\PWM_PDD.h	48;"	d
PWM_PDD_CAPTUREX0_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	64;"	d
PWM_PDD_CAPTUREX1_FLAG	.\Static_Code\PDD\PWM_PDD.h	49;"	d
PWM_PDD_CAPTUREX1_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	65;"	d
PWM_PDD_CAPTURE_ANY_EDGE	.\Static_Code\PDD\PWM_PDD.h	296;"	d
PWM_PDD_CAPTURE_DISABLED	.\Static_Code\PDD\PWM_PDD.h	293;"	d
PWM_PDD_CAPTURE_FALLING	.\Static_Code\PDD\PWM_PDD.h	294;"	d
PWM_PDD_CAPTURE_RISING	.\Static_Code\PDD\PWM_PDD.h	295;"	d
PWM_PDD_COMPARE0_FLAG	.\Static_Code\PDD\PWM_PDD.h	50;"	d
PWM_PDD_COMPARE0_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	66;"	d
PWM_PDD_COMPARE1_FLAG	.\Static_Code\PDD\PWM_PDD.h	51;"	d
PWM_PDD_COMPARE1_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	67;"	d
PWM_PDD_COMPARE2_FLAG	.\Static_Code\PDD\PWM_PDD.h	52;"	d
PWM_PDD_COMPARE2_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	68;"	d
PWM_PDD_COMPARE3_FLAG	.\Static_Code\PDD\PWM_PDD.h	53;"	d
PWM_PDD_COMPARE3_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	69;"	d
PWM_PDD_COMPARE4_FLAG	.\Static_Code\PDD\PWM_PDD.h	54;"	d
PWM_PDD_COMPARE4_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	70;"	d
PWM_PDD_COMPARE5_FLAG	.\Static_Code\PDD\PWM_PDD.h	55;"	d
PWM_PDD_COMPARE5_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	71;"	d
PWM_PDD_COMPLEMENTARY	.\Static_Code\PDD\PWM_PDD.h	220;"	d
PWM_PDD_COMPLEMENTARY_PWM23	.\Static_Code\PDD\PWM_PDD.h	313;"	d
PWM_PDD_COMPLEMENTARY_PWM45	.\Static_Code\PDD\PWM_PDD.h	314;"	d
PWM_PDD_CaptureA0FifoCount	.\Static_Code\PDD\PWM_PDD.h	3467;"	d
PWM_PDD_CaptureA1FifoCount	.\Static_Code\PDD\PWM_PDD.h	3491;"	d
PWM_PDD_CaptureB0FifoCount	.\Static_Code\PDD\PWM_PDD.h	3515;"	d
PWM_PDD_CaptureB1FifoCount	.\Static_Code\PDD\PWM_PDD.h	3539;"	d
PWM_PDD_CaptureValue0	.\Static_Code\PDD\PWM_PDD.h	4950;"	d
PWM_PDD_CaptureValue1	.\Static_Code\PDD\PWM_PDD.h	4973;"	d
PWM_PDD_CaptureValue1Cycle	.\Static_Code\PDD\PWM_PDD.h	5086;"	d
PWM_PDD_CaptureValue2	.\Static_Code\PDD\PWM_PDD.h	4996;"	d
PWM_PDD_CaptureValue2Cycle	.\Static_Code\PDD\PWM_PDD.h	5110;"	d
PWM_PDD_CaptureValue3	.\Static_Code\PDD\PWM_PDD.h	5019;"	d
PWM_PDD_CaptureValue3Cycle	.\Static_Code\PDD\PWM_PDD.h	5134;"	d
PWM_PDD_CaptureValue4	.\Static_Code\PDD\PWM_PDD.h	5042;"	d
PWM_PDD_CaptureValue4Cycle	.\Static_Code\PDD\PWM_PDD.h	5158;"	d
PWM_PDD_CaptureValue5	.\Static_Code\PDD\PWM_PDD.h	5065;"	d
PWM_PDD_CaptureValue5Cycle	.\Static_Code\PDD\PWM_PDD.h	5182;"	d
PWM_PDD_CaptureX0FifoCount	.\Static_Code\PDD\PWM_PDD.h	3563;"	d
PWM_PDD_CaptureX1FifoCount	.\Static_Code\PDD\PWM_PDD.h	3587;"	d
PWM_PDD_ClearFaultInterruptFlags	.\Static_Code\PDD\PWM_PDD.h	6395;"	d
PWM_PDD_ClearInterruptFlags	.\Static_Code\PDD\PWM_PDD.h	1872;"	d
PWM_PDD_ClearLoadOkay	.\Static_Code\PDD\PWM_PDD.h	6043;"	d
PWM_PDD_DMA_DISABLED	.\Static_Code\PDD\PWM_PDD.h	283;"	d
PWM_PDD_DeadtimeSourceSelect	.\Static_Code\PDD\PWM_PDD.h	5888;"	d
PWM_PDD_DisableFaultInterrupts	.\Static_Code\PDD\PWM_PDD.h	6312;"	d
PWM_PDD_DisableInterrupts	.\Static_Code\PDD\PWM_PDD.h	1925;"	d
PWM_PDD_EDGE_COUNTER_OUTPUT	.\Static_Code\PDD\PWM_PDD.h	290;"	d
PWM_PDD_EXTN_SIGNAL	.\Static_Code\PDD\PWM_PDD.h	310;"	d
PWM_PDD_EXT_CLK	.\Static_Code\PDD\PWM_PDD.h	248;"	d
PWM_PDD_EdgeCounterA	.\Static_Code\PDD\PWM_PDD.h	4728;"	d
PWM_PDD_EdgeCounterB	.\Static_Code\PDD\PWM_PDD.h	4753;"	d
PWM_PDD_EdgeCounterX	.\Static_Code\PDD\PWM_PDD.h	4778;"	d
PWM_PDD_EnableAFault	.\Static_Code\PDD\PWM_PDD.h	2967;"	d
PWM_PDD_EnableAMask	.\Static_Code\PDD\PWM_PDD.h	5395;"	d
PWM_PDD_EnableAOutput	.\Static_Code\PDD\PWM_PDD.h	5208;"	d
PWM_PDD_EnableArmA	.\Static_Code\PDD\PWM_PDD.h	4568;"	d
PWM_PDD_EnableArmB	.\Static_Code\PDD\PWM_PDD.h	4601;"	d
PWM_PDD_EnableArmX	.\Static_Code\PDD\PWM_PDD.h	4634;"	d
PWM_PDD_EnableBFault	.\Static_Code\PDD\PWM_PDD.h	3004;"	d
PWM_PDD_EnableBMask	.\Static_Code\PDD\PWM_PDD.h	5427;"	d
PWM_PDD_EnableBOutput	.\Static_Code\PDD\PWM_PDD.h	5240;"	d
PWM_PDD_EnableCaptureA0FifoDma	.\Static_Code\PDD\PWM_PDD.h	2627;"	d
PWM_PDD_EnableCaptureA1FifoDma	.\Static_Code\PDD\PWM_PDD.h	2659;"	d
PWM_PDD_EnableCaptureB0FifoDma	.\Static_Code\PDD\PWM_PDD.h	2691;"	d
PWM_PDD_EnableCaptureB1FifoDma	.\Static_Code\PDD\PWM_PDD.h	2723;"	d
PWM_PDD_EnableCaptureX0FifoDma	.\Static_Code\PDD\PWM_PDD.h	2755;"	d
PWM_PDD_EnableCaptureX1FifoDma	.\Static_Code\PDD\PWM_PDD.h	2787;"	d
PWM_PDD_EnableDebug	.\Static_Code\PDD\PWM_PDD.h	415;"	d
PWM_PDD_EnableDoubleSwitching	.\Static_Code\PDD\PWM_PDD.h	1422;"	d
PWM_PDD_EnableEdgeCounterA	.\Static_Code\PDD\PWM_PDD.h	3770;"	d
PWM_PDD_EnableEdgeCounterB	.\Static_Code\PDD\PWM_PDD.h	3803;"	d
PWM_PDD_EnableEdgeCounterX	.\Static_Code\PDD\PWM_PDD.h	3836;"	d
PWM_PDD_EnableFaultGlitchStretch	.\Static_Code\PDD\PWM_PDD.h	6668;"	d
PWM_PDD_EnableFaultInterrupt	.\Static_Code\PDD\PWM_PDD.h	6237;"	d
PWM_PDD_EnableFaultInterrupts	.\Static_Code\PDD\PWM_PDD.h	6292;"	d
PWM_PDD_EnableFaultTest	.\Static_Code\PDD\PWM_PDD.h	6829;"	d
PWM_PDD_EnableForceInitialization	.\Static_Code\PDD\PWM_PDD.h	804;"	d
PWM_PDD_EnableFractionalCyclePWM_APlacement	.\Static_Code\PDD\PWM_PDD.h	8725;"	d
PWM_PDD_EnableFractionalCyclePWM_BPlacement	.\Static_Code\PDD\PWM_PDD.h	8759;"	d
PWM_PDD_EnableFractionalCyclePWM_PeriodPlacement	.\Static_Code\PDD\PWM_PDD.h	8793;"	d
PWM_PDD_EnableFractionalDelayCircuit	.\Static_Code\PDD\PWM_PDD.h	8668;"	d
PWM_PDD_EnableFullCycleFaultRecovery	.\Static_Code\PDD\PWM_PDD.h	6521;"	d
PWM_PDD_EnableFullCycleReload	.\Static_Code\PDD\PWM_PDD.h	1141;"	d
PWM_PDD_EnableHalfCycleFaultRecovery	.\Static_Code\PDD\PWM_PDD.h	6425;"	d
PWM_PDD_EnableHalfCycleReload	.\Static_Code\PDD\PWM_PDD.h	1093;"	d
PWM_PDD_EnableInterrupts	.\Static_Code\PDD\PWM_PDD.h	1905;"	d
PWM_PDD_EnableRun	.\Static_Code\PDD\PWM_PDD.h	5968;"	d
PWM_PDD_EnableSplitDBLPWM	.\Static_Code\PDD\PWM_PDD.h	1279;"	d
PWM_PDD_EnableVal0OutputTrigger0	.\Static_Code\PDD\PWM_PDD.h	2129;"	d
PWM_PDD_EnableVal1OutputTrigger1	.\Static_Code\PDD\PWM_PDD.h	2157;"	d
PWM_PDD_EnableVal2OutputTrigger0	.\Static_Code\PDD\PWM_PDD.h	2191;"	d
PWM_PDD_EnableVal3OutputTrigger1	.\Static_Code\PDD\PWM_PDD.h	2225;"	d
PWM_PDD_EnableVal4OutputTrigger0	.\Static_Code\PDD\PWM_PDD.h	2259;"	d
PWM_PDD_EnableVal5OutputTrigger1	.\Static_Code\PDD\PWM_PDD.h	2293;"	d
PWM_PDD_EnableValueRegistersDma	.\Static_Code\PDD\PWM_PDD.h	2466;"	d
PWM_PDD_EnableWait	.\Static_Code\PDD\PWM_PDD.h	476;"	d
PWM_PDD_EnableXDoubleSwitching	.\Static_Code\PDD\PWM_PDD.h	1377;"	d
PWM_PDD_EnableXFault	.\Static_Code\PDD\PWM_PDD.h	3041;"	d
PWM_PDD_EnableXMask	.\Static_Code\PDD\PWM_PDD.h	5459;"	d
PWM_PDD_EnableXOutput	.\Static_Code\PDD\PWM_PDD.h	5272;"	d
PWM_PDD_FAULT0_FLAG	.\Static_Code\PDD\PWM_PDD.h	146;"	d
PWM_PDD_FAULT0_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	140;"	d
PWM_PDD_FAULT0_PIN_MASK	.\Static_Code\PDD\PWM_PDD.h	184;"	d
PWM_PDD_FAULT1_FLAG	.\Static_Code\PDD\PWM_PDD.h	147;"	d
PWM_PDD_FAULT1_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	141;"	d
PWM_PDD_FAULT1_PIN_MASK	.\Static_Code\PDD\PWM_PDD.h	185;"	d
PWM_PDD_FAULT2_FLAG	.\Static_Code\PDD\PWM_PDD.h	148;"	d
PWM_PDD_FAULT2_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	142;"	d
PWM_PDD_FAULT2_PIN_MASK	.\Static_Code\PDD\PWM_PDD.h	186;"	d
PWM_PDD_FAULT3_FLAG	.\Static_Code\PDD\PWM_PDD.h	149;"	d
PWM_PDD_FAULT3_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	143;"	d
PWM_PDD_FAULT3_PIN_MASK	.\Static_Code\PDD\PWM_PDD.h	187;"	d
PWM_PDD_FCLK_DIV1	.\Static_Code\PDD\PWM_PDD.h	252;"	d
PWM_PDD_FCLK_DIV128	.\Static_Code\PDD\PWM_PDD.h	259;"	d
PWM_PDD_FCLK_DIV16	.\Static_Code\PDD\PWM_PDD.h	256;"	d
PWM_PDD_FCLK_DIV2	.\Static_Code\PDD\PWM_PDD.h	253;"	d
PWM_PDD_FCLK_DIV32	.\Static_Code\PDD\PWM_PDD.h	257;"	d
PWM_PDD_FCLK_DIV4	.\Static_Code\PDD\PWM_PDD.h	254;"	d
PWM_PDD_FCLK_DIV64	.\Static_Code\PDD\PWM_PDD.h	258;"	d
PWM_PDD_FCLK_DIV8	.\Static_Code\PDD\PWM_PDD.h	255;"	d
PWM_PDD_FIFO_WATERMARK	.\Static_Code\PDD\PWM_PDD.h	284;"	d
PWM_PDD_FO_EXTERNAL_FORCE	.\Static_Code\PDD\PWM_PDD.h	240;"	d
PWM_PDD_FO_LOCAL_FORCE	.\Static_Code\PDD\PWM_PDD.h	234;"	d
PWM_PDD_FO_LOCAL_RELOAD	.\Static_Code\PDD\PWM_PDD.h	236;"	d
PWM_PDD_FO_LOCAL_SYNC	.\Static_Code\PDD\PWM_PDD.h	238;"	d
PWM_PDD_FO_MASTER_FORCE	.\Static_Code\PDD\PWM_PDD.h	235;"	d
PWM_PDD_FO_MASTER_RELOAD	.\Static_Code\PDD\PWM_PDD.h	237;"	d
PWM_PDD_FO_MASTER_SYNC	.\Static_Code\PDD\PWM_PDD.h	239;"	d
PWM_PDD_FREE_RUNNING	.\Static_Code\PDD\PWM_PDD.h	299;"	d
PWM_PDD_FULL_FAULT0_DISABLED	.\Static_Code\PDD\PWM_PDD.h	174;"	d
PWM_PDD_FULL_FAULT0_ENABLED	.\Static_Code\PDD\PWM_PDD.h	178;"	d
PWM_PDD_FULL_FAULT0_MASK	.\Static_Code\PDD\PWM_PDD.h	168;"	d
PWM_PDD_FULL_FAULT1_DISABLED	.\Static_Code\PDD\PWM_PDD.h	175;"	d
PWM_PDD_FULL_FAULT1_ENABLED	.\Static_Code\PDD\PWM_PDD.h	179;"	d
PWM_PDD_FULL_FAULT1_MASK	.\Static_Code\PDD\PWM_PDD.h	169;"	d
PWM_PDD_FULL_FAULT2_DISABLED	.\Static_Code\PDD\PWM_PDD.h	176;"	d
PWM_PDD_FULL_FAULT2_ENABLED	.\Static_Code\PDD\PWM_PDD.h	180;"	d
PWM_PDD_FULL_FAULT2_MASK	.\Static_Code\PDD\PWM_PDD.h	170;"	d
PWM_PDD_FULL_FAULT3_DISABLED	.\Static_Code\PDD\PWM_PDD.h	177;"	d
PWM_PDD_FULL_FAULT3_ENABLED	.\Static_Code\PDD\PWM_PDD.h	181;"	d
PWM_PDD_FULL_FAULT3_MASK	.\Static_Code\PDD\PWM_PDD.h	171;"	d
PWM_PDD_FilteredFaultPins	.\Static_Code\PDD\PWM_PDD.h	6614;"	d
PWM_PDD_FilteredFaultPinsMask	.\Static_Code\PDD\PWM_PDD.h	6640;"	d
PWM_PDD_ForceInitialization	.\Static_Code\PDD\PWM_PDD.h	864;"	d
PWM_PDD_FullCycleFaultRecoveryMask	.\Static_Code\PDD\PWM_PDD.h	6584;"	d
PWM_PDD_GENERATED_SIGNAL	.\Static_Code\PDD\PWM_PDD.h	307;"	d
PWM_PDD_GENERATED_SM0PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	106;"	d
PWM_PDD_GENERATED_SM0PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	110;"	d
PWM_PDD_GENERATED_SM1PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	114;"	d
PWM_PDD_GENERATED_SM1PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	118;"	d
PWM_PDD_GENERATED_SM2PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	122;"	d
PWM_PDD_GENERATED_SM2PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	126;"	d
PWM_PDD_GENERATED_SM3PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	130;"	d
PWM_PDD_GENERATED_SM3PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	134;"	d
PWM_PDD_GetAFaultEnabled	.\Static_Code\PDD\PWM_PDD.h	3073;"	d
PWM_PDD_GetAInput	.\Static_Code\PDD\PWM_PDD.h	1465;"	d
PWM_PDD_GetAMaskEnabled	.\Static_Code\PDD\PWM_PDD.h	5487;"	d
PWM_PDD_GetAOutputEnabled	.\Static_Code\PDD\PWM_PDD.h	5300;"	d
PWM_PDD_GetArmAEnabled	.\Static_Code\PDD\PWM_PDD.h	4661;"	d
PWM_PDD_GetArmBEnabled	.\Static_Code\PDD\PWM_PDD.h	4683;"	d
PWM_PDD_GetArmXEnabled	.\Static_Code\PDD\PWM_PDD.h	4705;"	d
PWM_PDD_GetBFaultEnabled	.\Static_Code\PDD\PWM_PDD.h	3099;"	d
PWM_PDD_GetBInput	.\Static_Code\PDD\PWM_PDD.h	1489;"	d
PWM_PDD_GetBMaskEnabled	.\Static_Code\PDD\PWM_PDD.h	5509;"	d
PWM_PDD_GetBOutputEnabled	.\Static_Code\PDD\PWM_PDD.h	5322;"	d
PWM_PDD_GetCaptureA0FifoDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2816;"	d
PWM_PDD_GetCaptureA1FifoDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2840;"	d
PWM_PDD_GetCaptureAFifoWaterMark	.\Static_Code\PDD\PWM_PDD.h	3692;"	d
PWM_PDD_GetCaptureB0FifoDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2864;"	d
PWM_PDD_GetCaptureB1FifoDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2888;"	d
PWM_PDD_GetCaptureBFifoWaterMark	.\Static_Code\PDD\PWM_PDD.h	3716;"	d
PWM_PDD_GetCaptureDmaSourceSelect	.\Static_Code\PDD\PWM_PDD.h	2600;"	d
PWM_PDD_GetCaptureX0FifoDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2912;"	d
PWM_PDD_GetCaptureX1FifoDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2936;"	d
PWM_PDD_GetCaptureXFifoWaterMark	.\Static_Code\PDD\PWM_PDD.h	3740;"	d
PWM_PDD_GetClockSourceSelect	.\Static_Code\PDD\PWM_PDD.h	1017;"	d
PWM_PDD_GetCountState	.\Static_Code\PDD\PWM_PDD.h	389;"	d
PWM_PDD_GetCurrentPolarity	.\Static_Code\PDD\PWM_PDD.h	5942;"	d
PWM_PDD_GetDeadtimeCount0	.\Static_Code\PDD\PWM_PDD.h	3191;"	d
PWM_PDD_GetDeadtimeCount1	.\Static_Code\PDD\PWM_PDD.h	3210;"	d
PWM_PDD_GetDebugEnabled	.\Static_Code\PDD\PWM_PDD.h	446;"	d
PWM_PDD_GetDoubleSwitchingEnabled	.\Static_Code\PDD\PWM_PDD.h	1446;"	d
PWM_PDD_GetEdgeA0	.\Static_Code\PDD\PWM_PDD.h	4254;"	d
PWM_PDD_GetEdgeA1	.\Static_Code\PDD\PWM_PDD.h	4279;"	d
PWM_PDD_GetEdgeB0	.\Static_Code\PDD\PWM_PDD.h	4304;"	d
PWM_PDD_GetEdgeB1	.\Static_Code\PDD\PWM_PDD.h	4329;"	d
PWM_PDD_GetEdgeCompareA	.\Static_Code\PDD\PWM_PDD.h	4878;"	d
PWM_PDD_GetEdgeCompareB	.\Static_Code\PDD\PWM_PDD.h	4901;"	d
PWM_PDD_GetEdgeCompareX	.\Static_Code\PDD\PWM_PDD.h	4924;"	d
PWM_PDD_GetEdgeCounterAEnabled	.\Static_Code\PDD\PWM_PDD.h	3864;"	d
PWM_PDD_GetEdgeCounterBEnabled	.\Static_Code\PDD\PWM_PDD.h	3887;"	d
PWM_PDD_GetEdgeCounterXEnabled	.\Static_Code\PDD\PWM_PDD.h	3910;"	d
PWM_PDD_GetEdgeX0	.\Static_Code\PDD\PWM_PDD.h	4354;"	d
PWM_PDD_GetEdgeX1	.\Static_Code\PDD\PWM_PDD.h	4379;"	d
PWM_PDD_GetFaultClearing	.\Static_Code\PDD\PWM_PDD.h	6154;"	d
PWM_PDD_GetFaultFilterCount	.\Static_Code\PDD\PWM_PDD.h	6798;"	d
PWM_PDD_GetFaultFilterPeriod	.\Static_Code\PDD\PWM_PDD.h	6746;"	d
PWM_PDD_GetFaultGlitchStretchEnabled	.\Static_Code\PDD\PWM_PDD.h	6696;"	d
PWM_PDD_GetFaultInterruptEnabled	.\Static_Code\PDD\PWM_PDD.h	6268;"	d
PWM_PDD_GetFaultInterruptFlags	.\Static_Code\PDD\PWM_PDD.h	6374;"	d
PWM_PDD_GetFaultInterruptMask	.\Static_Code\PDD\PWM_PDD.h	6355;"	d
PWM_PDD_GetFaultLevel	.\Static_Code\PDD\PWM_PDD.h	6098;"	d
PWM_PDD_GetFaultMode	.\Static_Code\PDD\PWM_PDD.h	6209;"	d
PWM_PDD_GetFaultStateA	.\Static_Code\PDD\PWM_PDD.h	1768;"	d
PWM_PDD_GetFaultStateB	.\Static_Code\PDD\PWM_PDD.h	1792;"	d
PWM_PDD_GetFaultStateX	.\Static_Code\PDD\PWM_PDD.h	1816;"	d
PWM_PDD_GetFaultTestEnabled	.\Static_Code\PDD\PWM_PDD.h	6853;"	d
PWM_PDD_GetFifoWatermarkAndControl	.\Static_Code\PDD\PWM_PDD.h	2552;"	d
PWM_PDD_GetForceInitializationEnabled	.\Static_Code\PDD\PWM_PDD.h	834;"	d
PWM_PDD_GetForceOutputSource	.\Static_Code\PDD\PWM_PDD.h	913;"	d
PWM_PDD_GetFractionalCyclePWM_APlacementEnabled	.\Static_Code\PDD\PWM_PDD.h	8821;"	d
PWM_PDD_GetFractionalCyclePWM_BPlacementEnabled	.\Static_Code\PDD\PWM_PDD.h	8844;"	d
PWM_PDD_GetFractionalCyclePWM_PeriodPlacementEnabled	.\Static_Code\PDD\PWM_PDD.h	8868;"	d
PWM_PDD_GetFractionalDelayCircuitEnabled	.\Static_Code\PDD\PWM_PDD.h	8696;"	d
PWM_PDD_GetFractionalValue1	.\Static_Code\PDD\PWM_PDD.h	8920;"	d
PWM_PDD_GetFractionalValue2	.\Static_Code\PDD\PWM_PDD.h	9056;"	d
PWM_PDD_GetFractionalValue3	.\Static_Code\PDD\PWM_PDD.h	9080;"	d
PWM_PDD_GetFractionalValue4	.\Static_Code\PDD\PWM_PDD.h	9104;"	d
PWM_PDD_GetFractionalValue5	.\Static_Code\PDD\PWM_PDD.h	9128;"	d
PWM_PDD_GetFullCycleFaultRecoveryEnabled	.\Static_Code\PDD\PWM_PDD.h	6554;"	d
PWM_PDD_GetFullCycleReloadEnabled	.\Static_Code\PDD\PWM_PDD.h	1162;"	d
PWM_PDD_GetHalfCycleFaultRecoveryEnabled	.\Static_Code\PDD\PWM_PDD.h	6458;"	d
PWM_PDD_GetHalfCycleReloadEnabled	.\Static_Code\PDD\PWM_PDD.h	1114;"	d
PWM_PDD_GetInitialCount	.\Static_Code\PDD\PWM_PDD.h	370;"	d
PWM_PDD_GetInitialValueA	.\Static_Code\PDD\PWM_PDD.h	674;"	d
PWM_PDD_GetInitialValueB	.\Static_Code\PDD\PWM_PDD.h	699;"	d
PWM_PDD_GetInitialValueX	.\Static_Code\PDD\PWM_PDD.h	724;"	d
PWM_PDD_GetInitializationControlSelect	.\Static_Code\PDD\PWM_PDD.h	777;"	d
PWM_PDD_GetInputSelectA	.\Static_Code\PDD\PWM_PDD.h	4027;"	d
PWM_PDD_GetInputSelectB	.\Static_Code\PDD\PWM_PDD.h	4051;"	d
PWM_PDD_GetInputSelectX	.\Static_Code\PDD\PWM_PDD.h	4075;"	d
PWM_PDD_GetInterruptFlags	.\Static_Code\PDD\PWM_PDD.h	1838;"	d
PWM_PDD_GetInterruptMask	.\Static_Code\PDD\PWM_PDD.h	1977;"	d
PWM_PDD_GetLoadModeSelect	.\Static_Code\PDD\PWM_PDD.h	1352;"	d
PWM_PDD_GetMonitorPLL	.\Static_Code\PDD\PWM_PDD.h	9172;"	d
PWM_PDD_GetOneShotModeA	.\Static_Code\PDD\PWM_PDD.h	4494;"	d
PWM_PDD_GetOneShotModeB	.\Static_Code\PDD\PWM_PDD.h	4517;"	d
PWM_PDD_GetOneShotModeX	.\Static_Code\PDD\PWM_PDD.h	4540;"	d
PWM_PDD_GetOutputAPolarity	.\Static_Code\PDD\PWM_PDD.h	1619;"	d
PWM_PDD_GetOutputBPolarity	.\Static_Code\PDD\PWM_PDD.h	1641;"	d
PWM_PDD_GetOutputTrigger0SourceSelect	.\Static_Code\PDD\PWM_PDD.h	2076;"	d
PWM_PDD_GetOutputTrigger1SourceSelect	.\Static_Code\PDD\PWM_PDD.h	2100;"	d
PWM_PDD_GetOutputXPolarity	.\Static_Code\PDD\PWM_PDD.h	1663;"	d
PWM_PDD_GetOverride23ControlSelect	.\Static_Code\PDD\PWM_PDD.h	5841;"	d
PWM_PDD_GetOverride45ControlSelect	.\Static_Code\PDD\PWM_PDD.h	5865;"	d
PWM_PDD_GetPairOperation	.\Static_Code\PDD\PWM_PDD.h	561;"	d
PWM_PDD_GetPrescaler	.\Static_Code\PDD\PWM_PDD.h	1251;"	d
PWM_PDD_GetReloadFrequency	.\Static_Code\PDD\PWM_PDD.h	1066;"	d
PWM_PDD_GetReloadSourceSelect	.\Static_Code\PDD\PWM_PDD.h	969;"	d
PWM_PDD_GetRunEnabled	.\Static_Code\PDD\PWM_PDD.h	5996;"	d
PWM_PDD_GetSoftwareControlledOutput23	.\Static_Code\PDD\PWM_PDD.h	5670;"	d
PWM_PDD_GetSoftwareControlledOutput45	.\Static_Code\PDD\PWM_PDD.h	5696;"	d
PWM_PDD_GetSplitDBLPWMEnabled	.\Static_Code\PDD\PWM_PDD.h	1303;"	d
PWM_PDD_GetVal0OutputTrigger0Enabled	.\Static_Code\PDD\PWM_PDD.h	2322;"	d
PWM_PDD_GetVal1OutputTrigger1Enabled	.\Static_Code\PDD\PWM_PDD.h	2343;"	d
PWM_PDD_GetVal2OutputTrigger0Enabled	.\Static_Code\PDD\PWM_PDD.h	2367;"	d
PWM_PDD_GetVal3OutputTrigger1Enabled	.\Static_Code\PDD\PWM_PDD.h	2391;"	d
PWM_PDD_GetVal4OutputTrigger0Enabled	.\Static_Code\PDD\PWM_PDD.h	2415;"	d
PWM_PDD_GetVal5OutputTrigger1Enabled	.\Static_Code\PDD\PWM_PDD.h	2439;"	d
PWM_PDD_GetValue0	.\Static_Code\PDD\PWM_PDD.h	3353;"	d
PWM_PDD_GetValue1	.\Static_Code\PDD\PWM_PDD.h	3372;"	d
PWM_PDD_GetValue2	.\Static_Code\PDD\PWM_PDD.h	3391;"	d
PWM_PDD_GetValue3	.\Static_Code\PDD\PWM_PDD.h	3410;"	d
PWM_PDD_GetValue4	.\Static_Code\PDD\PWM_PDD.h	3429;"	d
PWM_PDD_GetValue5	.\Static_Code\PDD\PWM_PDD.h	3448;"	d
PWM_PDD_GetValueRegistersDmaEnabled	.\Static_Code\PDD\PWM_PDD.h	2495;"	d
PWM_PDD_GetWaitEnabled	.\Static_Code\PDD\PWM_PDD.h	508;"	d
PWM_PDD_GetXDoubleSwitchingEnabled	.\Static_Code\PDD\PWM_PDD.h	1399;"	d
PWM_PDD_GetXFaultEnabled	.\Static_Code\PDD\PWM_PDD.h	3125;"	d
PWM_PDD_GetXInput	.\Static_Code\PDD\PWM_PDD.h	1513;"	d
PWM_PDD_GetXMaskEnabled	.\Static_Code\PDD\PWM_PDD.h	5531;"	d
PWM_PDD_GetXOutputEnabled	.\Static_Code\PDD\PWM_PDD.h	5344;"	d
PWM_PDD_HALF_FAULT0_DISABLED	.\Static_Code\PDD\PWM_PDD.h	158;"	d
PWM_PDD_HALF_FAULT0_ENABLED	.\Static_Code\PDD\PWM_PDD.h	162;"	d
PWM_PDD_HALF_FAULT0_MASK	.\Static_Code\PDD\PWM_PDD.h	152;"	d
PWM_PDD_HALF_FAULT1_DISABLED	.\Static_Code\PDD\PWM_PDD.h	159;"	d
PWM_PDD_HALF_FAULT1_ENABLED	.\Static_Code\PDD\PWM_PDD.h	163;"	d
PWM_PDD_HALF_FAULT1_MASK	.\Static_Code\PDD\PWM_PDD.h	153;"	d
PWM_PDD_HALF_FAULT2_DISABLED	.\Static_Code\PDD\PWM_PDD.h	160;"	d
PWM_PDD_HALF_FAULT2_ENABLED	.\Static_Code\PDD\PWM_PDD.h	164;"	d
PWM_PDD_HALF_FAULT2_MASK	.\Static_Code\PDD\PWM_PDD.h	154;"	d
PWM_PDD_HALF_FAULT3_DISABLED	.\Static_Code\PDD\PWM_PDD.h	161;"	d
PWM_PDD_HALF_FAULT3_ENABLED	.\Static_Code\PDD\PWM_PDD.h	165;"	d
PWM_PDD_HALF_FAULT3_MASK	.\Static_Code\PDD\PWM_PDD.h	155;"	d
PWM_PDD_HIGH	.\Static_Code\PDD\PWM_PDD.h	225;"	d
PWM_PDD_H_	.\Static_Code\PDD\PWM_PDD.h	9;"	d
PWM_PDD_HalfCycleFaultRecoveryMask	.\Static_Code\PDD\PWM_PDD.h	6488;"	d
PWM_PDD_INDEPENDENT	.\Static_Code\PDD\PWM_PDD.h	221;"	d
PWM_PDD_INVERTED_GENERATED	.\Static_Code\PDD\PWM_PDD.h	308;"	d
PWM_PDD_INVERTED_SM0PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	107;"	d
PWM_PDD_INVERTED_SM0PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	111;"	d
PWM_PDD_INVERTED_SM1PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	115;"	d
PWM_PDD_INVERTED_SM1PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	119;"	d
PWM_PDD_INVERTED_SM2PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	123;"	d
PWM_PDD_INVERTED_SM2PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	127;"	d
PWM_PDD_INVERTED_SM3PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	131;"	d
PWM_PDD_INVERTED_SM3PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	135;"	d
PWM_PDD_IS_EXTERNAL_SYNC	.\Static_Code\PDD\PWM_PDD.h	231;"	d
PWM_PDD_IS_LOCAL_SYNC	.\Static_Code\PDD\PWM_PDD.h	228;"	d
PWM_PDD_IS_MASTER_RELOAD	.\Static_Code\PDD\PWM_PDD.h	229;"	d
PWM_PDD_IS_MASTER_SYNC	.\Static_Code\PDD\PWM_PDD.h	230;"	d
PWM_PDD_LDOK_ONLY	.\Static_Code\PDD\PWM_PDD.h	263;"	d
PWM_PDD_LDOK_RELOAD	.\Static_Code\PDD\PWM_PDD.h	262;"	d
PWM_PDD_LOCAL_RELOAD_DMA	.\Static_Code\PDD\PWM_PDD.h	286;"	d
PWM_PDD_LOCAL_SYNC_DMA	.\Static_Code\PDD\PWM_PDD.h	285;"	d
PWM_PDD_LOGIC0	.\Static_Code\PDD\PWM_PDD.h	266;"	d
PWM_PDD_LOGIC1	.\Static_Code\PDD\PWM_PDD.h	267;"	d
PWM_PDD_LOGIC_ONE	.\Static_Code\PDD\PWM_PDD.h	304;"	d
PWM_PDD_LOGIC_ZERO	.\Static_Code\PDD\PWM_PDD.h	303;"	d
PWM_PDD_LOW	.\Static_Code\PDD\PWM_PDD.h	224;"	d
PWM_PDD_LoadOkay	.\Static_Code\PDD\PWM_PDD.h	6020;"	d
PWM_PDD_MANUAL_CLEARING	.\Static_Code\PDD\PWM_PDD.h	317;"	d
PWM_PDD_MONITOR_PLL_LOCKED	.\Static_Code\PDD\PWM_PDD.h	328;"	d
PWM_PDD_MONITOR_PLL_NOT_LOCKED	.\Static_Code\PDD\PWM_PDD.h	326;"	d
PWM_PDD_NORMAL_MODE	.\Static_Code\PDD\PWM_PDD.h	321;"	d
PWM_PDD_NOT_MONITOR_LOCKED	.\Static_Code\PDD\PWM_PDD.h	327;"	d
PWM_PDD_NOT_MONITOR_NOT_LOCKED	.\Static_Code\PDD\PWM_PDD.h	325;"	d
PWM_PDD_ONE_SHOT	.\Static_Code\PDD\PWM_PDD.h	300;"	d
PWM_PDD_OutputEnable	.\Static_Code\PDD\PWM_PDD.h	5368;"	d
PWM_PDD_OutputMasks	.\Static_Code\PDD\PWM_PDD.h	5557;"	d
PWM_PDD_PWM0_EXTA_MASK	.\Static_Code\PDD\PWM_PDD.h	109;"	d
PWM_PDD_PWM0_EXTB_MASK	.\Static_Code\PDD\PWM_PDD.h	113;"	d
PWM_PDD_PWM1_EXTA_MASK	.\Static_Code\PDD\PWM_PDD.h	117;"	d
PWM_PDD_PWM1_EXTB_MASK	.\Static_Code\PDD\PWM_PDD.h	121;"	d
PWM_PDD_PWM2_EXTA_MASK	.\Static_Code\PDD\PWM_PDD.h	125;"	d
PWM_PDD_PWM2_EXTB_MASK	.\Static_Code\PDD\PWM_PDD.h	129;"	d
PWM_PDD_PWM3_EXTA_MASK	.\Static_Code\PDD\PWM_PDD.h	133;"	d
PWM_PDD_PWM3_EXTB_MASK	.\Static_Code\PDD\PWM_PDD.h	137;"	d
PWM_PDD_PWMA_OUTPUT	.\Static_Code\PDD\PWM_PDD.h	272;"	d
PWM_PDD_PWMB_OUTPUT	.\Static_Code\PDD\PWM_PDD.h	276;"	d
PWM_PDD_PWM_OUT_TRIG0	.\Static_Code\PDD\PWM_PDD.h	271;"	d
PWM_PDD_PWM_OUT_TRIG1	.\Static_Code\PDD\PWM_PDD.h	275;"	d
PWM_PDD_RAW_INPUT	.\Static_Code\PDD\PWM_PDD.h	289;"	d
PWM_PDD_REGISTERS_UPDATED_FLAG	.\Static_Code\PDD\PWM_PDD.h	41;"	d
PWM_PDD_RELOAD_ERROR_FLAG	.\Static_Code\PDD\PWM_PDD.h	42;"	d
PWM_PDD_RELOAD_ERROR_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	58;"	d
PWM_PDD_RELOAD_FLAG	.\Static_Code\PDD\PWM_PDD.h	43;"	d
PWM_PDD_RELOAD_INTERRUPT	.\Static_Code\PDD\PWM_PDD.h	59;"	d
PWM_PDD_RS_LOCAL_RELOAD	.\Static_Code\PDD\PWM_PDD.h	243;"	d
PWM_PDD_RS_MASTER_RELOAD	.\Static_Code\PDD\PWM_PDD.h	244;"	d
PWM_PDD_ReadCaptureCompareAReg	.\Static_Code\PDD\PWM_PDD.h	7830;"	d
PWM_PDD_ReadCaptureCompareBReg	.\Static_Code\PDD\PWM_PDD.h	7849;"	d
PWM_PDD_ReadCaptureCompareXReg	.\Static_Code\PDD\PWM_PDD.h	7868;"	d
PWM_PDD_ReadCaptureControlAReg	.\Static_Code\PDD\PWM_PDD.h	7713;"	d
PWM_PDD_ReadCaptureControlBReg	.\Static_Code\PDD\PWM_PDD.h	7732;"	d
PWM_PDD_ReadCaptureControlXReg	.\Static_Code\PDD\PWM_PDD.h	7751;"	d
PWM_PDD_ReadCaptureValue0CycleReg	.\Static_Code\PDD\PWM_PDD.h	8241;"	d
PWM_PDD_ReadCaptureValue0Reg	.\Static_Code\PDD\PWM_PDD.h	8007;"	d
PWM_PDD_ReadCaptureValue1CycleReg	.\Static_Code\PDD\PWM_PDD.h	8260;"	d
PWM_PDD_ReadCaptureValue1Reg	.\Static_Code\PDD\PWM_PDD.h	8026;"	d
PWM_PDD_ReadCaptureValue2CycleReg	.\Static_Code\PDD\PWM_PDD.h	8279;"	d
PWM_PDD_ReadCaptureValue2Reg	.\Static_Code\PDD\PWM_PDD.h	8045;"	d
PWM_PDD_ReadCaptureValue3CycleReg	.\Static_Code\PDD\PWM_PDD.h	8298;"	d
PWM_PDD_ReadCaptureValue3Reg	.\Static_Code\PDD\PWM_PDD.h	8064;"	d
PWM_PDD_ReadCaptureValue4CycleReg	.\Static_Code\PDD\PWM_PDD.h	8317;"	d
PWM_PDD_ReadCaptureValue4Reg	.\Static_Code\PDD\PWM_PDD.h	8083;"	d
PWM_PDD_ReadCaptureValue5CycleReg	.\Static_Code\PDD\PWM_PDD.h	8336;"	d
PWM_PDD_ReadCaptureValue5Reg	.\Static_Code\PDD\PWM_PDD.h	8102;"	d
PWM_PDD_ReadControl2Reg	.\Static_Code\PDD\PWM_PDD.h	7007;"	d
PWM_PDD_ReadControlReg	.\Static_Code\PDD\PWM_PDD.h	7046;"	d
PWM_PDD_ReadCounterReg	.\Static_Code\PDD\PWM_PDD.h	6929;"	d
PWM_PDD_ReadDeadtimeCount0Reg	.\Static_Code\PDD\PWM_PDD.h	7615;"	d
PWM_PDD_ReadDeadtimeCount1Reg	.\Static_Code\PDD\PWM_PDD.h	7634;"	d
PWM_PDD_ReadDmaEnableReg	.\Static_Code\PDD\PWM_PDD.h	7436;"	d
PWM_PDD_ReadFaultControlReg	.\Static_Code\PDD\PWM_PDD.h	8523;"	d
PWM_PDD_ReadFaultDisableMapping0Reg	.\Static_Code\PDD\PWM_PDD.h	7536;"	d
PWM_PDD_ReadFaultDisableMapping1Reg	.\Static_Code\PDD\PWM_PDD.h	7556;"	d
PWM_PDD_ReadFaultFilterReg	.\Static_Code\PDD\PWM_PDD.h	8601;"	d
PWM_PDD_ReadFaultStatusReg	.\Static_Code\PDD\PWM_PDD.h	8562;"	d
PWM_PDD_ReadFaultTestReg	.\Static_Code\PDD\PWM_PDD.h	8640;"	d
PWM_PDD_ReadFractionalControlReg	.\Static_Code\PDD\PWM_PDD.h	9211;"	d
PWM_PDD_ReadFractionalValue1Reg	.\Static_Code\PDD\PWM_PDD.h	9330;"	d
PWM_PDD_ReadFractionalValue2Reg	.\Static_Code\PDD\PWM_PDD.h	9349;"	d
PWM_PDD_ReadFractionalValue3Reg	.\Static_Code\PDD\PWM_PDD.h	9368;"	d
PWM_PDD_ReadFractionalValue4Reg	.\Static_Code\PDD\PWM_PDD.h	9387;"	d
PWM_PDD_ReadFractionalValue5Reg	.\Static_Code\PDD\PWM_PDD.h	9406;"	d
PWM_PDD_ReadInitialCountReg	.\Static_Code\PDD\PWM_PDD.h	6968;"	d
PWM_PDD_ReadInterruptEnableReg	.\Static_Code\PDD\PWM_PDD.h	7397;"	d
PWM_PDD_ReadMaskReg	.\Static_Code\PDD\PWM_PDD.h	8410;"	d
PWM_PDD_ReadMasterControl2Reg	.\Static_Code\PDD\PWM_PDD.h	9443;"	d
PWM_PDD_ReadMasterControlReg	.\Static_Code\PDD\PWM_PDD.h	6890;"	d
PWM_PDD_ReadOutputControlReg	.\Static_Code\PDD\PWM_PDD.h	7319;"	d
PWM_PDD_ReadOutputEnableReg	.\Static_Code\PDD\PWM_PDD.h	8373;"	d
PWM_PDD_ReadOutputTriggerControlReg	.\Static_Code\PDD\PWM_PDD.h	7476;"	d
PWM_PDD_ReadPWMSourceSelectReg	.\Static_Code\PDD\PWM_PDD.h	8484;"	d
PWM_PDD_ReadSoftwareControlledOutputReg	.\Static_Code\PDD\PWM_PDD.h	8447;"	d
PWM_PDD_ReadStatusReg	.\Static_Code\PDD\PWM_PDD.h	7358;"	d
PWM_PDD_ReadValue0Reg	.\Static_Code\PDD\PWM_PDD.h	7185;"	d
PWM_PDD_ReadValue1Reg	.\Static_Code\PDD\PWM_PDD.h	7204;"	d
PWM_PDD_ReadValue2Reg	.\Static_Code\PDD\PWM_PDD.h	7223;"	d
PWM_PDD_ReadValue3Reg	.\Static_Code\PDD\PWM_PDD.h	7242;"	d
PWM_PDD_ReadValue4Reg	.\Static_Code\PDD\PWM_PDD.h	7261;"	d
PWM_PDD_ReadValue5Reg	.\Static_Code\PDD\PWM_PDD.h	7280;"	d
PWM_PDD_SAFE_MODE	.\Static_Code\PDD\PWM_PDD.h	322;"	d
PWM_PDD_SM0CLEARLOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	206;"	d
PWM_PDD_SM0COMPLEMENTARY23_MASK	.\Static_Code\PDD\PWM_PDD.h	190;"	d
PWM_PDD_SM0COMPLEMENTARY45_MASK	.\Static_Code\PDD\PWM_PDD.h	194;"	d
PWM_PDD_SM0LOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	214;"	d
PWM_PDD_SM0NOTLOAD_MASK	.\Static_Code\PDD\PWM_PDD.h	210;"	d
PWM_PDD_SM0RUN_DISABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	198;"	d
PWM_PDD_SM0RUN_ENABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	202;"	d
PWM_PDD_SM0UPDATE_MASK	.\Static_Code\PDD\PWM_PDD.h	90;"	d
PWM_PDD_SM0_OUTPUT23_MASK	.\Static_Code\PDD\PWM_PDD.h	96;"	d
PWM_PDD_SM0_OUTPUT45_MASK	.\Static_Code\PDD\PWM_PDD.h	97;"	d
PWM_PDD_SM0_OUTPUTA_MASK	.\Static_Code\PDD\PWM_PDD.h	74;"	d
PWM_PDD_SM0_OUTPUTB_MASK	.\Static_Code\PDD\PWM_PDD.h	75;"	d
PWM_PDD_SM0_OUTPUTX_MASK	.\Static_Code\PDD\PWM_PDD.h	76;"	d
PWM_PDD_SM1CLEARLOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	207;"	d
PWM_PDD_SM1COMPLEMENTARY23_MASK	.\Static_Code\PDD\PWM_PDD.h	191;"	d
PWM_PDD_SM1COMPLEMENTARY45_MASK	.\Static_Code\PDD\PWM_PDD.h	195;"	d
PWM_PDD_SM1LOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	215;"	d
PWM_PDD_SM1NOTLOAD_MASK	.\Static_Code\PDD\PWM_PDD.h	211;"	d
PWM_PDD_SM1RUN_DISABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	199;"	d
PWM_PDD_SM1RUN_ENABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	203;"	d
PWM_PDD_SM1UPDATE_MASK	.\Static_Code\PDD\PWM_PDD.h	91;"	d
PWM_PDD_SM1_OUTPUT23_MASK	.\Static_Code\PDD\PWM_PDD.h	98;"	d
PWM_PDD_SM1_OUTPUT45_MASK	.\Static_Code\PDD\PWM_PDD.h	99;"	d
PWM_PDD_SM1_OUTPUTA_MASK	.\Static_Code\PDD\PWM_PDD.h	77;"	d
PWM_PDD_SM1_OUTPUTB_MASK	.\Static_Code\PDD\PWM_PDD.h	78;"	d
PWM_PDD_SM1_OUTPUTX_MASK	.\Static_Code\PDD\PWM_PDD.h	79;"	d
PWM_PDD_SM2CLEARLOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	208;"	d
PWM_PDD_SM2COMPLEMENTARY23_MASK	.\Static_Code\PDD\PWM_PDD.h	192;"	d
PWM_PDD_SM2COMPLEMENTARY45_MASK	.\Static_Code\PDD\PWM_PDD.h	196;"	d
PWM_PDD_SM2LOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	216;"	d
PWM_PDD_SM2NOTLOAD_MASK	.\Static_Code\PDD\PWM_PDD.h	212;"	d
PWM_PDD_SM2RUN_DISABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	200;"	d
PWM_PDD_SM2RUN_ENABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	204;"	d
PWM_PDD_SM2UPDATE_MASK	.\Static_Code\PDD\PWM_PDD.h	92;"	d
PWM_PDD_SM2_OUTPUT23_MASK	.\Static_Code\PDD\PWM_PDD.h	100;"	d
PWM_PDD_SM2_OUTPUT45_MASK	.\Static_Code\PDD\PWM_PDD.h	101;"	d
PWM_PDD_SM2_OUTPUTA_MASK	.\Static_Code\PDD\PWM_PDD.h	80;"	d
PWM_PDD_SM2_OUTPUTB_MASK	.\Static_Code\PDD\PWM_PDD.h	81;"	d
PWM_PDD_SM2_OUTPUTX_MASK	.\Static_Code\PDD\PWM_PDD.h	82;"	d
PWM_PDD_SM3CLEARLOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	209;"	d
PWM_PDD_SM3COMPLEMENTARY23_MASK	.\Static_Code\PDD\PWM_PDD.h	193;"	d
PWM_PDD_SM3COMPLEMENTARY45_MASK	.\Static_Code\PDD\PWM_PDD.h	197;"	d
PWM_PDD_SM3LOADOK_MASK	.\Static_Code\PDD\PWM_PDD.h	217;"	d
PWM_PDD_SM3NOTLOAD_MASK	.\Static_Code\PDD\PWM_PDD.h	213;"	d
PWM_PDD_SM3RUN_DISABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	201;"	d
PWM_PDD_SM3RUN_ENABLED_MASK	.\Static_Code\PDD\PWM_PDD.h	205;"	d
PWM_PDD_SM3UPDATE_MASK	.\Static_Code\PDD\PWM_PDD.h	93;"	d
PWM_PDD_SM3_OUTPUT23_MASK	.\Static_Code\PDD\PWM_PDD.h	102;"	d
PWM_PDD_SM3_OUTPUT45_MASK	.\Static_Code\PDD\PWM_PDD.h	103;"	d
PWM_PDD_SM3_OUTPUTA_MASK	.\Static_Code\PDD\PWM_PDD.h	83;"	d
PWM_PDD_SM3_OUTPUTB_MASK	.\Static_Code\PDD\PWM_PDD.h	84;"	d
PWM_PDD_SM3_OUTPUTX_MASK	.\Static_Code\PDD\PWM_PDD.h	85;"	d
PWM_PDD_SOFTWARE_CONTROLED	.\Static_Code\PDD\PWM_PDD.h	309;"	d
PWM_PDD_SWCOUT_SM0PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	108;"	d
PWM_PDD_SWCOUT_SM0PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	112;"	d
PWM_PDD_SWCOUT_SM1PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	116;"	d
PWM_PDD_SWCOUT_SM1PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	120;"	d
PWM_PDD_SWCOUT_SM2PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	124;"	d
PWM_PDD_SWCOUT_SM2PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	128;"	d
PWM_PDD_SWCOUT_SM3PWM23_MASK	.\Static_Code\PDD\PWM_PDD.h	132;"	d
PWM_PDD_SWCOUT_SM3PWM45_MASK	.\Static_Code\PDD\PWM_PDD.h	136;"	d
PWM_PDD_SetCaptureAFifoWaterMark	.\Static_Code\PDD\PWM_PDD.h	3615;"	d
PWM_PDD_SetCaptureBFifoWaterMark	.\Static_Code\PDD\PWM_PDD.h	3642;"	d
PWM_PDD_SetCaptureDmaSourceSelect	.\Static_Code\PDD\PWM_PDD.h	2575;"	d
PWM_PDD_SetCaptureXFifoWaterMark	.\Static_Code\PDD\PWM_PDD.h	3669;"	d
PWM_PDD_SetClockSourceSelect	.\Static_Code\PDD\PWM_PDD.h	993;"	d
PWM_PDD_SetCurrentPolarity	.\Static_Code\PDD\PWM_PDD.h	5913;"	d
PWM_PDD_SetDeadtimeCount0	.\Static_Code\PDD\PWM_PDD.h	3150;"	d
PWM_PDD_SetDeadtimeCount1	.\Static_Code\PDD\PWM_PDD.h	3172;"	d
PWM_PDD_SetEdgeA0	.\Static_Code\PDD\PWM_PDD.h	4100;"	d
PWM_PDD_SetEdgeA1	.\Static_Code\PDD\PWM_PDD.h	4126;"	d
PWM_PDD_SetEdgeB0	.\Static_Code\PDD\PWM_PDD.h	4152;"	d
PWM_PDD_SetEdgeB1	.\Static_Code\PDD\PWM_PDD.h	4178;"	d
PWM_PDD_SetEdgeCompareA	.\Static_Code\PDD\PWM_PDD.h	4804;"	d
PWM_PDD_SetEdgeCompareB	.\Static_Code\PDD\PWM_PDD.h	4829;"	d
PWM_PDD_SetEdgeCompareX	.\Static_Code\PDD\PWM_PDD.h	4854;"	d
PWM_PDD_SetEdgeX0	.\Static_Code\PDD\PWM_PDD.h	4204;"	d
PWM_PDD_SetEdgeX1	.\Static_Code\PDD\PWM_PDD.h	4230;"	d
PWM_PDD_SetFaultClearing	.\Static_Code\PDD\PWM_PDD.h	6125;"	d
PWM_PDD_SetFaultFilterCount	.\Static_Code\PDD\PWM_PDD.h	6771;"	d
PWM_PDD_SetFaultFilterPeriod	.\Static_Code\PDD\PWM_PDD.h	6721;"	d
PWM_PDD_SetFaultInterruptMask	.\Static_Code\PDD\PWM_PDD.h	6332;"	d
PWM_PDD_SetFaultLevel	.\Static_Code\PDD\PWM_PDD.h	6068;"	d
PWM_PDD_SetFaultMode	.\Static_Code\PDD\PWM_PDD.h	6180;"	d
PWM_PDD_SetFaultStateA	.\Static_Code\PDD\PWM_PDD.h	1689;"	d
PWM_PDD_SetFaultStateB	.\Static_Code\PDD\PWM_PDD.h	1717;"	d
PWM_PDD_SetFaultStateX	.\Static_Code\PDD\PWM_PDD.h	1745;"	d
PWM_PDD_SetFifoWatermarkAndControl	.\Static_Code\PDD\PWM_PDD.h	2525;"	d
PWM_PDD_SetForceOutputSource	.\Static_Code\PDD\PWM_PDD.h	889;"	d
PWM_PDD_SetFractionalValue1	.\Static_Code\PDD\PWM_PDD.h	8897;"	d
PWM_PDD_SetFractionalValue2	.\Static_Code\PDD\PWM_PDD.h	8949;"	d
PWM_PDD_SetFractionalValue3	.\Static_Code\PDD\PWM_PDD.h	8977;"	d
PWM_PDD_SetFractionalValue4	.\Static_Code\PDD\PWM_PDD.h	9005;"	d
PWM_PDD_SetFractionalValue5	.\Static_Code\PDD\PWM_PDD.h	9033;"	d
PWM_PDD_SetInitialCount	.\Static_Code\PDD\PWM_PDD.h	349;"	d
PWM_PDD_SetInitialValueA	.\Static_Code\PDD\PWM_PDD.h	586;"	d
PWM_PDD_SetInitialValueB	.\Static_Code\PDD\PWM_PDD.h	616;"	d
PWM_PDD_SetInitialValueX	.\Static_Code\PDD\PWM_PDD.h	646;"	d
PWM_PDD_SetInitializationControlSelect	.\Static_Code\PDD\PWM_PDD.h	752;"	d
PWM_PDD_SetInputSelectA	.\Static_Code\PDD\PWM_PDD.h	3936;"	d
PWM_PDD_SetInputSelectB	.\Static_Code\PDD\PWM_PDD.h	3967;"	d
PWM_PDD_SetInputSelectX	.\Static_Code\PDD\PWM_PDD.h	3998;"	d
PWM_PDD_SetInterruptMask	.\Static_Code\PDD\PWM_PDD.h	1945;"	d
PWM_PDD_SetLoadModeSelect	.\Static_Code\PDD\PWM_PDD.h	1326;"	d
PWM_PDD_SetMonitorPLL	.\Static_Code\PDD\PWM_PDD.h	9154;"	d
PWM_PDD_SetOneShotModeA	.\Static_Code\PDD\PWM_PDD.h	4406;"	d
PWM_PDD_SetOneShotModeB	.\Static_Code\PDD\PWM_PDD.h	4436;"	d
PWM_PDD_SetOneShotModeX	.\Static_Code\PDD\PWM_PDD.h	4466;"	d
PWM_PDD_SetOutputAPolarity	.\Static_Code\PDD\PWM_PDD.h	1540;"	d
PWM_PDD_SetOutputBPolarity	.\Static_Code\PDD\PWM_PDD.h	1567;"	d
PWM_PDD_SetOutputTrigger0SourceSelect	.\Static_Code\PDD\PWM_PDD.h	2014;"	d
PWM_PDD_SetOutputTrigger1SourceSelect	.\Static_Code\PDD\PWM_PDD.h	2047;"	d
PWM_PDD_SetOutputXPolarity	.\Static_Code\PDD\PWM_PDD.h	1594;"	d
PWM_PDD_SetOverride23ControlSelect	.\Static_Code\PDD\PWM_PDD.h	5757;"	d
PWM_PDD_SetOverride45ControlSelect	.\Static_Code\PDD\PWM_PDD.h	5801;"	d
PWM_PDD_SetPairOperation	.\Static_Code\PDD\PWM_PDD.h	534;"	d
PWM_PDD_SetPrescaler	.\Static_Code\PDD\PWM_PDD.h	1227;"	d
PWM_PDD_SetReloadFrequency	.\Static_Code\PDD\PWM_PDD.h	1042;"	d
PWM_PDD_SetReloadSourceSelect	.\Static_Code\PDD\PWM_PDD.h	941;"	d
PWM_PDD_SetSoftwareControlledOutput23	.\Static_Code\PDD\PWM_PDD.h	5605;"	d
PWM_PDD_SetSoftwareControlledOutput45	.\Static_Code\PDD\PWM_PDD.h	5639;"	d
PWM_PDD_SetValue0	.\Static_Code\PDD\PWM_PDD.h	3232;"	d
PWM_PDD_SetValue1	.\Static_Code\PDD\PWM_PDD.h	3254;"	d
PWM_PDD_SetValue2	.\Static_Code\PDD\PWM_PDD.h	3274;"	d
PWM_PDD_SetValue3	.\Static_Code\PDD\PWM_PDD.h	3294;"	d
PWM_PDD_SetValue4	.\Static_Code\PDD\PWM_PDD.h	3314;"	d
PWM_PDD_SetValue5	.\Static_Code\PDD\PWM_PDD.h	3334;"	d
PWM_PDD_SoftwareControlledOutput	.\Static_Code\PDD\PWM_PDD.h	5721;"	d
PWM_PDD_TRISTATED	.\Static_Code\PDD\PWM_PDD.h	268;"	d
PWM_PDD_UpdateImmediately	.\Static_Code\PDD\PWM_PDD.h	5577;"	d
PWM_PDD_WATERMARKS_ANDED	.\Static_Code\PDD\PWM_PDD.h	280;"	d
PWM_PDD_WATERMARKS_ORED	.\Static_Code\PDD\PWM_PDD.h	279;"	d
PWM_PDD_WriteCaptureCompareAReg	.\Static_Code\PDD\PWM_PDD.h	7771;"	d
PWM_PDD_WriteCaptureCompareBReg	.\Static_Code\PDD\PWM_PDD.h	7791;"	d
PWM_PDD_WriteCaptureCompareXReg	.\Static_Code\PDD\PWM_PDD.h	7811;"	d
PWM_PDD_WriteCaptureControlAReg	.\Static_Code\PDD\PWM_PDD.h	7654;"	d
PWM_PDD_WriteCaptureControlBReg	.\Static_Code\PDD\PWM_PDD.h	7674;"	d
PWM_PDD_WriteCaptureControlXReg	.\Static_Code\PDD\PWM_PDD.h	7694;"	d
PWM_PDD_WriteCaptureValue0CycleReg	.\Static_Code\PDD\PWM_PDD.h	8122;"	d
PWM_PDD_WriteCaptureValue0Reg	.\Static_Code\PDD\PWM_PDD.h	7888;"	d
PWM_PDD_WriteCaptureValue1CycleReg	.\Static_Code\PDD\PWM_PDD.h	8142;"	d
PWM_PDD_WriteCaptureValue1Reg	.\Static_Code\PDD\PWM_PDD.h	7908;"	d
PWM_PDD_WriteCaptureValue2CycleReg	.\Static_Code\PDD\PWM_PDD.h	8162;"	d
PWM_PDD_WriteCaptureValue2Reg	.\Static_Code\PDD\PWM_PDD.h	7928;"	d
PWM_PDD_WriteCaptureValue3CycleReg	.\Static_Code\PDD\PWM_PDD.h	8182;"	d
PWM_PDD_WriteCaptureValue3Reg	.\Static_Code\PDD\PWM_PDD.h	7948;"	d
PWM_PDD_WriteCaptureValue4CycleReg	.\Static_Code\PDD\PWM_PDD.h	8202;"	d
PWM_PDD_WriteCaptureValue4Reg	.\Static_Code\PDD\PWM_PDD.h	7968;"	d
PWM_PDD_WriteCaptureValue5CycleReg	.\Static_Code\PDD\PWM_PDD.h	8222;"	d
PWM_PDD_WriteCaptureValue5Reg	.\Static_Code\PDD\PWM_PDD.h	7988;"	d
PWM_PDD_WriteControl2Reg	.\Static_Code\PDD\PWM_PDD.h	6988;"	d
PWM_PDD_WriteControlReg	.\Static_Code\PDD\PWM_PDD.h	7027;"	d
PWM_PDD_WriteCounterReg	.\Static_Code\PDD\PWM_PDD.h	6910;"	d
PWM_PDD_WriteDeadtimeCount0Reg	.\Static_Code\PDD\PWM_PDD.h	7576;"	d
PWM_PDD_WriteDeadtimeCount1Reg	.\Static_Code\PDD\PWM_PDD.h	7596;"	d
PWM_PDD_WriteDmaEnableReg	.\Static_Code\PDD\PWM_PDD.h	7417;"	d
PWM_PDD_WriteFaultControlReg	.\Static_Code\PDD\PWM_PDD.h	8504;"	d
PWM_PDD_WriteFaultDisableMapping0Reg	.\Static_Code\PDD\PWM_PDD.h	7496;"	d
PWM_PDD_WriteFaultDisableMapping1Reg	.\Static_Code\PDD\PWM_PDD.h	7516;"	d
PWM_PDD_WriteFaultFilterReg	.\Static_Code\PDD\PWM_PDD.h	8582;"	d
PWM_PDD_WriteFaultStatusReg	.\Static_Code\PDD\PWM_PDD.h	8543;"	d
PWM_PDD_WriteFaultTestReg	.\Static_Code\PDD\PWM_PDD.h	8621;"	d
PWM_PDD_WriteFractionalControlReg	.\Static_Code\PDD\PWM_PDD.h	9192;"	d
PWM_PDD_WriteFractionalValue1Reg	.\Static_Code\PDD\PWM_PDD.h	9231;"	d
PWM_PDD_WriteFractionalValue2Reg	.\Static_Code\PDD\PWM_PDD.h	9251;"	d
PWM_PDD_WriteFractionalValue3Reg	.\Static_Code\PDD\PWM_PDD.h	9271;"	d
PWM_PDD_WriteFractionalValue4Reg	.\Static_Code\PDD\PWM_PDD.h	9291;"	d
PWM_PDD_WriteFractionalValue5Reg	.\Static_Code\PDD\PWM_PDD.h	9311;"	d
PWM_PDD_WriteInitialCountReg	.\Static_Code\PDD\PWM_PDD.h	6949;"	d
PWM_PDD_WriteInterruptEnableReg	.\Static_Code\PDD\PWM_PDD.h	7378;"	d
PWM_PDD_WriteMaskReg	.\Static_Code\PDD\PWM_PDD.h	8392;"	d
PWM_PDD_WriteMasterControl2Reg	.\Static_Code\PDD\PWM_PDD.h	9425;"	d
PWM_PDD_WriteMasterControlReg	.\Static_Code\PDD\PWM_PDD.h	6872;"	d
PWM_PDD_WriteOutputControlReg	.\Static_Code\PDD\PWM_PDD.h	7300;"	d
PWM_PDD_WriteOutputEnableReg	.\Static_Code\PDD\PWM_PDD.h	8355;"	d
PWM_PDD_WriteOutputTriggerControlReg	.\Static_Code\PDD\PWM_PDD.h	7456;"	d
PWM_PDD_WritePWMSourceSelectReg	.\Static_Code\PDD\PWM_PDD.h	8466;"	d
PWM_PDD_WriteSoftwareControlledOutputReg	.\Static_Code\PDD\PWM_PDD.h	8429;"	d
PWM_PDD_WriteStatusReg	.\Static_Code\PDD\PWM_PDD.h	7339;"	d
PWM_PDD_WriteValue0Reg	.\Static_Code\PDD\PWM_PDD.h	7066;"	d
PWM_PDD_WriteValue1Reg	.\Static_Code\PDD\PWM_PDD.h	7086;"	d
PWM_PDD_WriteValue2Reg	.\Static_Code\PDD\PWM_PDD.h	7106;"	d
PWM_PDD_WriteValue3Reg	.\Static_Code\PDD\PWM_PDD.h	7126;"	d
PWM_PDD_WriteValue4Reg	.\Static_Code\PDD\PWM_PDD.h	7146;"	d
PWM_PDD_WriteValue5Reg	.\Static_Code\PDD\PWM_PDD.h	7166;"	d
PWM_PDD_XInputInDeadtime0	.\Static_Code\PDD\PWM_PDD.h	1182;"	d
PWM_PDD_XInputInDeadtime1	.\Static_Code\PDD\PWM_PDD.h	1204;"	d
PWM_STS_CFA0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4639;"	d
PWM_STS_CFA0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4640;"	d
PWM_STS_CFA1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4641;"	d
PWM_STS_CFA1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4642;"	d
PWM_STS_CFB0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4635;"	d
PWM_STS_CFB0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4636;"	d
PWM_STS_CFB1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4637;"	d
PWM_STS_CFB1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4638;"	d
PWM_STS_CFX0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4631;"	d
PWM_STS_CFX0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4632;"	d
PWM_STS_CFX1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4633;"	d
PWM_STS_CFX1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4634;"	d
PWM_STS_CMPF	.\Static_Code\IO_Map\MC56F82748.h	4630;"	d
PWM_STS_CMPF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4628;"	d
PWM_STS_CMPF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4629;"	d
PWM_STS_REF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4645;"	d
PWM_STS_REF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4646;"	d
PWM_STS_REG	.\Static_Code\IO_Map\MC56F82748.h	4442;"	d
PWM_STS_RF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4643;"	d
PWM_STS_RF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4644;"	d
PWM_STS_RUF_MASK	.\Static_Code\IO_Map\MC56F82748.h	4647;"	d
PWM_STS_RUF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4648;"	d
PWM_SWCOUT_REG	.\Static_Code\IO_Map\MC56F82748.h	4469;"	d
PWM_SWCOUT_SM0OUT23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4891;"	d
PWM_SWCOUT_SM0OUT23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4892;"	d
PWM_SWCOUT_SM0OUT45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4889;"	d
PWM_SWCOUT_SM0OUT45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4890;"	d
PWM_SWCOUT_SM1OUT23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4895;"	d
PWM_SWCOUT_SM1OUT23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4896;"	d
PWM_SWCOUT_SM1OUT45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4893;"	d
PWM_SWCOUT_SM1OUT45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4894;"	d
PWM_SWCOUT_SM2OUT23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4899;"	d
PWM_SWCOUT_SM2OUT23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4900;"	d
PWM_SWCOUT_SM2OUT45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4897;"	d
PWM_SWCOUT_SM2OUT45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4898;"	d
PWM_SWCOUT_SM3OUT23_MASK	.\Static_Code\IO_Map\MC56F82748.h	4903;"	d
PWM_SWCOUT_SM3OUT23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4904;"	d
PWM_SWCOUT_SM3OUT45_MASK	.\Static_Code\IO_Map\MC56F82748.h	4901;"	d
PWM_SWCOUT_SM3OUT45_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4902;"	d
PWM_TCTRL_OUT_TRIG_EN	.\Static_Code\IO_Map\MC56F82748.h	4692;"	d
PWM_TCTRL_OUT_TRIG_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	4690;"	d
PWM_TCTRL_OUT_TRIG_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4691;"	d
PWM_TCTRL_PWAOT0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4695;"	d
PWM_TCTRL_PWAOT0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4696;"	d
PWM_TCTRL_PWBOT1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4693;"	d
PWM_TCTRL_PWBOT1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4694;"	d
PWM_TCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	4445;"	d
PWM_VAL0_REG	.\Static_Code\IO_Map\MC56F82748.h	4429;"	d
PWM_VAL0_VAL0	.\Static_Code\IO_Map\MC56F82748.h	4553;"	d
PWM_VAL0_VAL0_MASK	.\Static_Code\IO_Map\MC56F82748.h	4551;"	d
PWM_VAL0_VAL0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4552;"	d
PWM_VAL1_REG	.\Static_Code\IO_Map\MC56F82748.h	4431;"	d
PWM_VAL1_VAL1	.\Static_Code\IO_Map\MC56F82748.h	4561;"	d
PWM_VAL1_VAL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	4559;"	d
PWM_VAL1_VAL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4560;"	d
PWM_VAL2_REG	.\Static_Code\IO_Map\MC56F82748.h	4433;"	d
PWM_VAL2_VAL2	.\Static_Code\IO_Map\MC56F82748.h	4569;"	d
PWM_VAL2_VAL2_MASK	.\Static_Code\IO_Map\MC56F82748.h	4567;"	d
PWM_VAL2_VAL2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4568;"	d
PWM_VAL3_REG	.\Static_Code\IO_Map\MC56F82748.h	4435;"	d
PWM_VAL3_VAL3	.\Static_Code\IO_Map\MC56F82748.h	4577;"	d
PWM_VAL3_VAL3_MASK	.\Static_Code\IO_Map\MC56F82748.h	4575;"	d
PWM_VAL3_VAL3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4576;"	d
PWM_VAL4_REG	.\Static_Code\IO_Map\MC56F82748.h	4437;"	d
PWM_VAL4_VAL4	.\Static_Code\IO_Map\MC56F82748.h	4585;"	d
PWM_VAL4_VAL4_MASK	.\Static_Code\IO_Map\MC56F82748.h	4583;"	d
PWM_VAL4_VAL4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4584;"	d
PWM_VAL5_REG	.\Static_Code\IO_Map\MC56F82748.h	4439;"	d
PWM_VAL5_VAL5	.\Static_Code\IO_Map\MC56F82748.h	4593;"	d
PWM_VAL5_VAL5_MASK	.\Static_Code\IO_Map\MC56F82748.h	4591;"	d
PWM_VAL5_VAL5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	4592;"	d
PWR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PWR;                                    \/**< ADC Power Control Register, offset: 0x4E *\/$/;"	m	struct:ADC_MemMap
PWR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PWR;                                    \/**< Power Control Register, offset: 0x8 *\/$/;"	m	struct:SIM_MemMap
PWR2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PWR2;                                   \/**< ADC Power Control Register 2, offset: 0x53 *\/$/;"	m	struct:ADC_MemMap
PWRMODE	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t PWRMODE;                                \/**< Power Mode Register, offset: 0x28 *\/$/;"	m	struct:SIM_MemMap
ParityErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t ParityErrors;               \/* Number of receiver parity errors *\/$/;"	m	struct:__anon19
PeriphClearBitMask16	.\Static_Code\System\PE_Types.h	156;"	d
PeriphClearBitMask32	.\Static_Code\System\PE_Types.h	157;"	d
PeriphClearBitMask8	.\Static_Code\System\PE_Types.h	155;"	d
PeriphClearSetBits16	.\Static_Code\System\PE_Types.h	297;"	d
PeriphClearSetBits32	.\Static_Code\System\PE_Types.h	300;"	d
PeriphClearSetBits8	.\Static_Code\System\PE_Types.h	294;"	d
PeriphGetBitMask16	.\Static_Code\System\PE_Types.h	181;"	d
PeriphGetBitMask32	.\Static_Code\System\PE_Types.h	182;"	d
PeriphGetBitMask8	.\Static_Code\System\PE_Types.h	180;"	d
PeriphInvertBitMask16	.\Static_Code\System\PE_Types.h	206;"	d
PeriphInvertBitMask32	.\Static_Code\System\PE_Types.h	207;"	d
PeriphInvertBitMask8	.\Static_Code\System\PE_Types.h	205;"	d
PeriphInvertRegSetBitMask16	.\Static_Code\System\PE_Types.h	382;"	d
PeriphInvertRegSetBitMask32	.\Static_Code\System\PE_Types.h	383;"	d
PeriphInvertRegSetBitMask8	.\Static_Code\System\PE_Types.h	381;"	d
PeriphReadReg16	.\Static_Code\System\PE_Types.h	83;"	d
PeriphReadReg32	.\Static_Code\System\PE_Types.h	84;"	d
PeriphReadReg8	.\Static_Code\System\PE_Types.h	82;"	d
PeriphResetSetBits16	.\Static_Code\System\PE_Types.h	331;"	d
PeriphResetSetBits32	.\Static_Code\System\PE_Types.h	334;"	d
PeriphResetSetBits8	.\Static_Code\System\PE_Types.h	328;"	d
PeriphSafeClearBitMask16	.\Static_Code\System\PE_Types.h	407;"	d
PeriphSafeClearBitMask32	.\Static_Code\System\PE_Types.h	408;"	d
PeriphSafeClearBitMask8	.\Static_Code\System\PE_Types.h	406;"	d
PeriphSafeClearFlags16	.\Static_Code\System\PE_Types.h	359;"	d
PeriphSafeClearFlags32	.\Static_Code\System\PE_Types.h	360;"	d
PeriphSafeClearFlags8	.\Static_Code\System\PE_Types.h	358;"	d
PeriphSafeResetSetBits16	.\Static_Code\System\PE_Types.h	463;"	d
PeriphSafeResetSetBits32	.\Static_Code\System\PE_Types.h	468;"	d
PeriphSafeResetSetBits8	.\Static_Code\System\PE_Types.h	458;"	d
PeriphSafeSetBitMask16	.\Static_Code\System\PE_Types.h	432;"	d
PeriphSafeSetBitMask32	.\Static_Code\System\PE_Types.h	433;"	d
PeriphSafeSetBitMask8	.\Static_Code\System\PE_Types.h	431;"	d
PeriphSafeSetBits16	.\Static_Code\System\PE_Types.h	498;"	d
PeriphSafeSetBits32	.\Static_Code\System\PE_Types.h	499;"	d
PeriphSafeSetBits8	.\Static_Code\System\PE_Types.h	497;"	d
PeriphSetBitMask16	.\Static_Code\System\PE_Types.h	131;"	d
PeriphSetBitMask32	.\Static_Code\System\PE_Types.h	132;"	d
PeriphSetBitMask8	.\Static_Code\System\PE_Types.h	130;"	d
PeriphSetBits16	.\Static_Code\System\PE_Types.h	233;"	d
PeriphSetBits32	.\Static_Code\System\PE_Types.h	234;"	d
PeriphSetBits8	.\Static_Code\System\PE_Types.h	232;"	d
PeriphSetClearBits16	.\Static_Code\System\PE_Types.h	263;"	d
PeriphSetClearBits32	.\Static_Code\System\PE_Types.h	266;"	d
PeriphSetClearBits8	.\Static_Code\System\PE_Types.h	260;"	d
PeriphWriteReg16	.\Static_Code\System\PE_Types.h	106;"	d
PeriphWriteReg32	.\Static_Code\System\PE_Types.h	107;"	d
PeriphWriteReg8	.\Static_Code\System\PE_Types.h	105;"	d
Peripherals_Init	.\Static_Code\System\Peripherals_Init.c	/^void Peripherals_Init(void)$/;"	f
PhaseA	.\Static_Code\System\PE_Types.h	/^        Frac16 PhaseA;$/;"	m	struct:__anon77
PhaseA	.\Static_Code\System\PE_Types.h	/^        UWord16 PhaseA   :1;$/;"	m	struct:__anon74
PhaseB	.\Static_Code\System\PE_Types.h	/^        Frac16 PhaseB;$/;"	m	struct:__anon77
PhaseB	.\Static_Code\System\PE_Types.h	/^        UWord16 PhaseB   :1;$/;"	m	struct:__anon74
PhaseC	.\Static_Code\System\PE_Types.h	/^        Frac16 PhaseC;$/;"	m	struct:__anon77
Pins1_H_	.\Generated_Code\Pins1.h	60;"	d
PolyHigh	.\Generated_Code\PE_LDD.h	/^  uint16_t PolyHigh;                   \/* Poly high value *\/$/;"	m	struct:__anon13
PolyLow	.\Generated_Code\PE_LDD.h	/^  uint16_t PolyLow;                    \/* Poly low value *\/$/;"	m	struct:__anon13
PositionDifferenceHoldReg	.\Static_Code\System\PE_Types.h	/^        union { Word16 PositionDifferenceHoldReg;$/;"	m	union:__anon69::__anon70
PositionHoldReg	.\Static_Code\System\PE_Types.h	/^        union { decoder_uReg32bit PositionHoldReg;$/;"	m	union:__anon69::__anon72
PositivePIDLimit	.\Static_Code\System\PE_Types.h	/^   Word16 PositivePIDLimit;$/;"	m	struct:__anon82
PositivePILimit	.\Static_Code\System\PE_Types.h	/^   Word16 PositivePILimit;$/;"	m	struct:__anon83
ProportionalGain	.\Static_Code\System\PE_Types.h	/^   Word16 ProportionalGain;$/;"	m	struct:__anon82
ProportionalGain	.\Static_Code\System\PE_Types.h	/^   Word16 ProportionalGain;$/;"	m	struct:__anon83
ProportionalGainScale	.\Static_Code\System\PE_Types.h	/^   Word16 ProportionalGainScale;$/;"	m	struct:__anon82
ProportionalGainScale	.\Static_Code\System\PE_Types.h	/^   Word16 ProportionalGainScale;$/;"	m	struct:__anon83
QSCI0_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	5413;"	d
QSCI0_CTRL1	.\Static_Code\IO_Map\MC56F82748.h	5432;"	d
QSCI0_CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5433;"	d
QSCI0_CTRL3	.\Static_Code\IO_Map\MC56F82748.h	5436;"	d
QSCI0_DATA	.\Static_Code\IO_Map\MC56F82748.h	5435;"	d
QSCI0_Init	.\Static_Code\Peripherals\QSCI0_Init.c	/^void QSCI0_Init(void) {$/;"	f
QSCI0_RATE	.\Static_Code\IO_Map\MC56F82748.h	5431;"	d
QSCI0_STAT	.\Static_Code\IO_Map\MC56F82748.h	5434;"	d
QSCI1_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	5415;"	d
QSCI1_CTRL1	.\Static_Code\IO_Map\MC56F82748.h	5439;"	d
QSCI1_CTRL2	.\Static_Code\IO_Map\MC56F82748.h	5440;"	d
QSCI1_CTRL3	.\Static_Code\IO_Map\MC56F82748.h	5443;"	d
QSCI1_DATA	.\Static_Code\IO_Map\MC56F82748.h	5442;"	d
QSCI1_Init	.\Static_Code\Peripherals\QSCI1_Init.c	/^void QSCI1_Init(void) {$/;"	f
QSCI1_RATE	.\Static_Code\IO_Map\MC56F82748.h	5438;"	d
QSCI1_STAT	.\Static_Code\IO_Map\MC56F82748.h	5441;"	d
QSCI_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	5417;"	d
QSCI_CTRL1_LOOP_MASK	.\Static_Code\IO_Map\MC56F82748.h	5343;"	d
QSCI_CTRL1_LOOP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5344;"	d
QSCI_CTRL1_M_MASK	.\Static_Code\IO_Map\MC56F82748.h	5337;"	d
QSCI_CTRL1_M_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5338;"	d
QSCI_CTRL1_PE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5331;"	d
QSCI_CTRL1_PE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5332;"	d
QSCI_CTRL1_POL_MASK	.\Static_Code\IO_Map\MC56F82748.h	5333;"	d
QSCI_CTRL1_POL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5334;"	d
QSCI_CTRL1_PT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5329;"	d
QSCI_CTRL1_PT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5330;"	d
QSCI_CTRL1_REG	.\Static_Code\IO_Map\MC56F82748.h	5285;"	d
QSCI_CTRL1_REIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5321;"	d
QSCI_CTRL1_REIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5322;"	d
QSCI_CTRL1_RE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5317;"	d
QSCI_CTRL1_RE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5318;"	d
QSCI_CTRL1_RFIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5323;"	d
QSCI_CTRL1_RFIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5324;"	d
QSCI_CTRL1_RSRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	5339;"	d
QSCI_CTRL1_RSRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5340;"	d
QSCI_CTRL1_RWU_MASK	.\Static_Code\IO_Map\MC56F82748.h	5315;"	d
QSCI_CTRL1_RWU_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5316;"	d
QSCI_CTRL1_SBK_MASK	.\Static_Code\IO_Map\MC56F82748.h	5313;"	d
QSCI_CTRL1_SBK_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5314;"	d
QSCI_CTRL1_SWAI_MASK	.\Static_Code\IO_Map\MC56F82748.h	5341;"	d
QSCI_CTRL1_SWAI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5342;"	d
QSCI_CTRL1_TEIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5327;"	d
QSCI_CTRL1_TEIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5328;"	d
QSCI_CTRL1_TE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5319;"	d
QSCI_CTRL1_TE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5320;"	d
QSCI_CTRL1_TIIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5325;"	d
QSCI_CTRL1_TIIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5326;"	d
QSCI_CTRL1_WAKE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5335;"	d
QSCI_CTRL1_WAKE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5336;"	d
QSCI_CTRL2_FIFO_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5354;"	d
QSCI_CTRL2_FIFO_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5355;"	d
QSCI_CTRL2_LINMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5350;"	d
QSCI_CTRL2_LINMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5351;"	d
QSCI_CTRL2_RDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5346;"	d
QSCI_CTRL2_RDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5347;"	d
QSCI_CTRL2_REG	.\Static_Code\IO_Map\MC56F82748.h	5286;"	d
QSCI_CTRL2_RFCNT	.\Static_Code\IO_Map\MC56F82748.h	5361;"	d
QSCI_CTRL2_RFCNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5359;"	d
QSCI_CTRL2_RFCNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5360;"	d
QSCI_CTRL2_RFWM	.\Static_Code\IO_Map\MC56F82748.h	5358;"	d
QSCI_CTRL2_RFWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5356;"	d
QSCI_CTRL2_RFWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5357;"	d
QSCI_CTRL2_RIEIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5352;"	d
QSCI_CTRL2_RIEIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5353;"	d
QSCI_CTRL2_TDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5348;"	d
QSCI_CTRL2_TDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5349;"	d
QSCI_CTRL2_TFCNT	.\Static_Code\IO_Map\MC56F82748.h	5367;"	d
QSCI_CTRL2_TFCNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5365;"	d
QSCI_CTRL2_TFCNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5366;"	d
QSCI_CTRL2_TFWM	.\Static_Code\IO_Map\MC56F82748.h	5364;"	d
QSCI_CTRL2_TFWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5362;"	d
QSCI_CTRL2_TFWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5363;"	d
QSCI_CTRL3_REG	.\Static_Code\IO_Map\MC56F82748.h	5289;"	d
QSCI_CTRL3_SBRH	.\Static_Code\IO_Map\MC56F82748.h	5404;"	d
QSCI_CTRL3_SBRH_MASK	.\Static_Code\IO_Map\MC56F82748.h	5402;"	d
QSCI_CTRL3_SBRH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5403;"	d
QSCI_CTRL3_SHEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5400;"	d
QSCI_CTRL3_SHEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5401;"	d
QSCI_DATA_RECEIVE_TRANSMIT_DATA	.\Static_Code\IO_Map\MC56F82748.h	5398;"	d
QSCI_DATA_RECEIVE_TRANSMIT_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5396;"	d
QSCI_DATA_RECEIVE_TRANSMIT_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5397;"	d
QSCI_DATA_REG	.\Static_Code\IO_Map\MC56F82748.h	5288;"	d
QSCI_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct QSCI_MemMap {$/;"	s
QSCI_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *QSCI_MemMapPtr;$/;"	t
QSCI_PDD_BY_ADDRESS_MARK	.\Static_Code\PDD\QSCI_PDD.h	76;"	d
QSCI_PDD_BY_IDLE_LINE	.\Static_Code\PDD\QSCI_PDD.h	75;"	d
QSCI_PDD_ClearBreak	.\Static_Code\PDD\QSCI_PDD.h	503;"	d
QSCI_PDD_DisableInterrupt	.\Static_Code\PDD\QSCI_PDD.h	374;"	d
QSCI_PDD_DisableRxStateInterruptMask	.\Static_Code\PDD\QSCI_PDD.h	720;"	d
QSCI_PDD_EnableFifo	.\Static_Code\PDD\QSCI_PDD.h	678;"	d
QSCI_PDD_EnableInterrupt	.\Static_Code\PDD\QSCI_PDD.h	354;"	d
QSCI_PDD_EnableLinSlaveMode	.\Static_Code\PDD\QSCI_PDD.h	742;"	d
QSCI_PDD_EnableOperateInWaitMode	.\Static_Code\PDD\QSCI_PDD.h	240;"	d
QSCI_PDD_EnableReceiveDma	.\Static_Code\PDD\QSCI_PDD.h	790;"	d
QSCI_PDD_EnableReceiver	.\Static_Code\PDD\QSCI_PDD.h	439;"	d
QSCI_PDD_EnableRxStateInterruptMask	.\Static_Code\PDD\QSCI_PDD.h	700;"	d
QSCI_PDD_EnableStopHoldOffMode	.\Static_Code\PDD\QSCI_PDD.h	1034;"	d
QSCI_PDD_EnableTransmitDma	.\Static_Code\PDD\QSCI_PDD.h	766;"	d
QSCI_PDD_EnableTransmitter	.\Static_Code\PDD\QSCI_PDD.h	415;"	d
QSCI_PDD_GetChar8	.\Static_Code\PDD\QSCI_PDD.h	953;"	d
QSCI_PDD_GetChar9	.\Static_Code\PDD\QSCI_PDD.h	972;"	d
QSCI_PDD_GetRxFifoWordCount	.\Static_Code\PDD\QSCI_PDD.h	629;"	d
QSCI_PDD_GetTxCompleteInterruptMask	.\Static_Code\PDD\QSCI_PDD.h	393;"	d
QSCI_PDD_GetTxFifoWordCount	.\Static_Code\PDD\QSCI_PDD.h	583;"	d
QSCI_PDD_H_	.\Static_Code\PDD\QSCI_PDD.h	9;"	d
QSCI_PDD_INTERRUPT_RECEIVER	.\Static_Code\PDD\QSCI_PDD.h	44;"	d
QSCI_PDD_INTERRUPT_RECEIVER_ERROR	.\Static_Code\PDD\QSCI_PDD.h	45;"	d
QSCI_PDD_INTERRUPT_TRANSMITTER	.\Static_Code\PDD\QSCI_PDD.h	42;"	d
QSCI_PDD_INTERRUPT_TRANSMITTER_COMPLETE	.\Static_Code\PDD\QSCI_PDD.h	43;"	d
QSCI_PDD_INVERTED_POLARITY	.\Static_Code\PDD\QSCI_PDD.h	80;"	d
QSCI_PDD_LIN_SYNC_ERROR_FLAG	.\Static_Code\PDD\QSCI_PDD.h	60;"	d
QSCI_PDD_LOOP_MODE_LOCAL_LOOP	.\Static_Code\PDD\QSCI_PDD.h	67;"	d
QSCI_PDD_LOOP_MODE_NORMAL	.\Static_Code\PDD\QSCI_PDD.h	66;"	d
QSCI_PDD_LOOP_MODE_RX_TO_TX_PIN	.\Static_Code\PDD\QSCI_PDD.h	68;"	d
QSCI_PDD_NORMAL_OPERATION	.\Static_Code\PDD\QSCI_PDD.h	88;"	d
QSCI_PDD_NORMAL_POLARITY	.\Static_Code\PDD\QSCI_PDD.h	79;"	d
QSCI_PDD_PARITY_EVEN	.\Static_Code\PDD\QSCI_PDD.h	84;"	d
QSCI_PDD_PARITY_NONE	.\Static_Code\PDD\QSCI_PDD.h	83;"	d
QSCI_PDD_PARITY_ODD	.\Static_Code\PDD\QSCI_PDD.h	85;"	d
QSCI_PDD_PutChar8	.\Static_Code\PDD\QSCI_PDD.h	913;"	d
QSCI_PDD_PutChar9	.\Static_Code\PDD\QSCI_PDD.h	934;"	d
QSCI_PDD_RX_ACTIVE_FLAG	.\Static_Code\PDD\QSCI_PDD.h	63;"	d
QSCI_PDD_RX_DATA_FULL_FLAG	.\Static_Code\PDD\QSCI_PDD.h	53;"	d
QSCI_PDD_RX_DMA_REQUEST_FLAG	.\Static_Code\PDD\QSCI_PDD.h	62;"	d
QSCI_PDD_RX_FIFO_1_OR_MORE	.\Static_Code\PDD\QSCI_PDD.h	98;"	d
QSCI_PDD_RX_FIFO_2_OR_MORE	.\Static_Code\PDD\QSCI_PDD.h	99;"	d
QSCI_PDD_RX_FIFO_3_OR_MORE	.\Static_Code\PDD\QSCI_PDD.h	100;"	d
QSCI_PDD_RX_FIFO_4_OR_MORE	.\Static_Code\PDD\QSCI_PDD.h	101;"	d
QSCI_PDD_RX_FRAMING_ERROR_FLAG	.\Static_Code\PDD\QSCI_PDD.h	57;"	d
QSCI_PDD_RX_IDLE_FLAG	.\Static_Code\PDD\QSCI_PDD.h	54;"	d
QSCI_PDD_RX_INPUT_EDGE	.\Static_Code\PDD\QSCI_PDD.h	48;"	d
QSCI_PDD_RX_INPUT_EDGE_FLAG	.\Static_Code\PDD\QSCI_PDD.h	59;"	d
QSCI_PDD_RX_NOISE_FLAG	.\Static_Code\PDD\QSCI_PDD.h	56;"	d
QSCI_PDD_RX_OVERRUN_FLAG	.\Static_Code\PDD\QSCI_PDD.h	55;"	d
QSCI_PDD_RX_PARITY_ERROR_FLAG	.\Static_Code\PDD\QSCI_PDD.h	58;"	d
QSCI_PDD_ReadBaudRateReg	.\Static_Code\PDD\QSCI_PDD.h	172;"	d
QSCI_PDD_ReadControl1Reg	.\Static_Code\PDD\QSCI_PDD.h	542;"	d
QSCI_PDD_ReadControl2Reg	.\Static_Code\PDD\QSCI_PDD.h	811;"	d
QSCI_PDD_ReadControl3Reg	.\Static_Code\PDD\QSCI_PDD.h	1055;"	d
QSCI_PDD_ReadDataReg	.\Static_Code\PDD\QSCI_PDD.h	991;"	d
QSCI_PDD_ReadStatusFlags	.\Static_Code\PDD\QSCI_PDD.h	852;"	d
QSCI_PDD_ReadStatusReg	.\Static_Code\PDD\QSCI_PDD.h	871;"	d
QSCI_PDD_ReceiverWakeup	.\Static_Code\PDD\QSCI_PDD.h	463;"	d
QSCI_PDD_STANDBY_STATE	.\Static_Code\PDD\QSCI_PDD.h	89;"	d
QSCI_PDD_SendBreak	.\Static_Code\PDD\QSCI_PDD.h	522;"	d
QSCI_PDD_SetBaudRate	.\Static_Code\PDD\QSCI_PDD.h	120;"	d
QSCI_PDD_SetBreak	.\Static_Code\PDD\QSCI_PDD.h	484;"	d
QSCI_PDD_SetDataWidth	.\Static_Code\PDD\QSCI_PDD.h	262;"	d
QSCI_PDD_SetFractionalBaudRate	.\Static_Code\PDD\QSCI_PDD.h	149;"	d
QSCI_PDD_SetLoopMode	.\Static_Code\PDD\QSCI_PDD.h	214;"	d
QSCI_PDD_SetParity	.\Static_Code\PDD\QSCI_PDD.h	330;"	d
QSCI_PDD_SetRxFifoWatermark	.\Static_Code\PDD\QSCI_PDD.h	652;"	d
QSCI_PDD_SetRxTxPolarity	.\Static_Code\PDD\QSCI_PDD.h	308;"	d
QSCI_PDD_SetTxFifoWatermark	.\Static_Code\PDD\QSCI_PDD.h	606;"	d
QSCI_PDD_SetWakeupCondition	.\Static_Code\PDD\QSCI_PDD.h	285;"	d
QSCI_PDD_TX_DATA_EMPTY_FLAG	.\Static_Code\PDD\QSCI_PDD.h	51;"	d
QSCI_PDD_TX_DMA_REQUEST_FLAG	.\Static_Code\PDD\QSCI_PDD.h	61;"	d
QSCI_PDD_TX_FIFO_1_OR_LESS	.\Static_Code\PDD\QSCI_PDD.h	93;"	d
QSCI_PDD_TX_FIFO_2_OR_LESS	.\Static_Code\PDD\QSCI_PDD.h	94;"	d
QSCI_PDD_TX_FIFO_3_OR_LESS	.\Static_Code\PDD\QSCI_PDD.h	95;"	d
QSCI_PDD_TX_FIFO_EMPTY	.\Static_Code\PDD\QSCI_PDD.h	92;"	d
QSCI_PDD_TX_IDLE_FLAG	.\Static_Code\PDD\QSCI_PDD.h	52;"	d
QSCI_PDD_WIDTH_8	.\Static_Code\PDD\QSCI_PDD.h	71;"	d
QSCI_PDD_WIDTH_9	.\Static_Code\PDD\QSCI_PDD.h	72;"	d
QSCI_PDD_WriteBaudRateReg	.\Static_Code\PDD\QSCI_PDD.h	194;"	d
QSCI_PDD_WriteControl1Reg	.\Static_Code\PDD\QSCI_PDD.h	564;"	d
QSCI_PDD_WriteControl2Reg	.\Static_Code\PDD\QSCI_PDD.h	833;"	d
QSCI_PDD_WriteControl3Reg	.\Static_Code\PDD\QSCI_PDD.h	1077;"	d
QSCI_PDD_WriteDataReg	.\Static_Code\PDD\QSCI_PDD.h	1012;"	d
QSCI_PDD_WriteStatusReg	.\Static_Code\PDD\QSCI_PDD.h	892;"	d
QSCI_RATE_FRAC_SBR	.\Static_Code\IO_Map\MC56F82748.h	5308;"	d
QSCI_RATE_FRAC_SBR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5306;"	d
QSCI_RATE_FRAC_SBR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5307;"	d
QSCI_RATE_REG	.\Static_Code\IO_Map\MC56F82748.h	5284;"	d
QSCI_RATE_SBRL	.\Static_Code\IO_Map\MC56F82748.h	5311;"	d
QSCI_RATE_SBRL_MASK	.\Static_Code\IO_Map\MC56F82748.h	5309;"	d
QSCI_RATE_SBRL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5310;"	d
QSCI_STAT_FE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5381;"	d
QSCI_STAT_FE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5382;"	d
QSCI_STAT_LSE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5375;"	d
QSCI_STAT_LSE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5376;"	d
QSCI_STAT_NF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5383;"	d
QSCI_STAT_NF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5384;"	d
QSCI_STAT_OR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5385;"	d
QSCI_STAT_OR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5386;"	d
QSCI_STAT_PF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5379;"	d
QSCI_STAT_PF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5380;"	d
QSCI_STAT_RAF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5369;"	d
QSCI_STAT_RAF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5370;"	d
QSCI_STAT_RDMA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5371;"	d
QSCI_STAT_RDMA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5372;"	d
QSCI_STAT_RDRF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5389;"	d
QSCI_STAT_RDRF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5390;"	d
QSCI_STAT_REG	.\Static_Code\IO_Map\MC56F82748.h	5287;"	d
QSCI_STAT_RIDLE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5387;"	d
QSCI_STAT_RIDLE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5388;"	d
QSCI_STAT_RIEF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5377;"	d
QSCI_STAT_RIEF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5378;"	d
QSCI_STAT_TDMA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5373;"	d
QSCI_STAT_TDMA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5374;"	d
QSCI_STAT_TDRE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5393;"	d
QSCI_STAT_TDRE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5394;"	d
QSCI_STAT_TIDLE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5391;"	d
QSCI_STAT_TIDLE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5392;"	d
QSPI0_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	5662;"	d
QSPI0_Init	.\Static_Code\Peripherals\QSPI0_Init.c	/^void QSPI0_Init(void) {$/;"	f
QSPI0_SPCTL2	.\Static_Code\IO_Map\MC56F82748.h	5686;"	d
QSPI0_SPDRR	.\Static_Code\IO_Map\MC56F82748.h	5682;"	d
QSPI0_SPDSR	.\Static_Code\IO_Map\MC56F82748.h	5681;"	d
QSPI0_SPDTR	.\Static_Code\IO_Map\MC56F82748.h	5683;"	d
QSPI0_SPFIFO	.\Static_Code\IO_Map\MC56F82748.h	5684;"	d
QSPI0_SPSCR	.\Static_Code\IO_Map\MC56F82748.h	5680;"	d
QSPI0_SPWAIT	.\Static_Code\IO_Map\MC56F82748.h	5685;"	d
QSPI1_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	5664;"	d
QSPI1_Init	.\Static_Code\Peripherals\QSPI1_Init.c	/^void QSPI1_Init(void) {$/;"	f
QSPI1_SPCTL2	.\Static_Code\IO_Map\MC56F82748.h	5694;"	d
QSPI1_SPDRR	.\Static_Code\IO_Map\MC56F82748.h	5690;"	d
QSPI1_SPDSR	.\Static_Code\IO_Map\MC56F82748.h	5689;"	d
QSPI1_SPDTR	.\Static_Code\IO_Map\MC56F82748.h	5691;"	d
QSPI1_SPFIFO	.\Static_Code\IO_Map\MC56F82748.h	5692;"	d
QSPI1_SPSCR	.\Static_Code\IO_Map\MC56F82748.h	5688;"	d
QSPI1_SPWAIT	.\Static_Code\IO_Map\MC56F82748.h	5693;"	d
QSPI_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	5666;"	d
QSPI_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct QSPI_MemMap {$/;"	s
QSPI_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *QSPI_MemMapPtr;$/;"	t
QSPI_PDD_10_BITS	.\Static_Code\PDD\QSPI_PDD.h	102;"	d
QSPI_PDD_11_BITS	.\Static_Code\PDD\QSPI_PDD.h	103;"	d
QSPI_PDD_12_BITS	.\Static_Code\PDD\QSPI_PDD.h	104;"	d
QSPI_PDD_13_BITS	.\Static_Code\PDD\QSPI_PDD.h	105;"	d
QSPI_PDD_14_BITS	.\Static_Code\PDD\QSPI_PDD.h	106;"	d
QSPI_PDD_15_BITS	.\Static_Code\PDD\QSPI_PDD.h	107;"	d
QSPI_PDD_16_BITS	.\Static_Code\PDD\QSPI_PDD.h	108;"	d
QSPI_PDD_2_BITS	.\Static_Code\PDD\QSPI_PDD.h	94;"	d
QSPI_PDD_3_BITS	.\Static_Code\PDD\QSPI_PDD.h	95;"	d
QSPI_PDD_4_BITS	.\Static_Code\PDD\QSPI_PDD.h	96;"	d
QSPI_PDD_5_BITS	.\Static_Code\PDD\QSPI_PDD.h	97;"	d
QSPI_PDD_6_BITS	.\Static_Code\PDD\QSPI_PDD.h	98;"	d
QSPI_PDD_7_BITS	.\Static_Code\PDD\QSPI_PDD.h	99;"	d
QSPI_PDD_8_BITS	.\Static_Code\PDD\QSPI_PDD.h	100;"	d
QSPI_PDD_9_BITS	.\Static_Code\PDD\QSPI_PDD.h	101;"	d
QSPI_PDD_ACTIVE_HIGH	.\Static_Code\PDD\QSPI_PDD.h	74;"	d
QSPI_PDD_ACTIVE_LOW	.\Static_Code\PDD\QSPI_PDD.h	75;"	d
QSPI_PDD_BAUD_RATE_DIV_1024	.\Static_Code\PDD\QSPI_PDD.h	50;"	d
QSPI_PDD_BAUD_RATE_DIV_128	.\Static_Code\PDD\QSPI_PDD.h	47;"	d
QSPI_PDD_BAUD_RATE_DIV_16	.\Static_Code\PDD\QSPI_PDD.h	44;"	d
QSPI_PDD_BAUD_RATE_DIV_2	.\Static_Code\PDD\QSPI_PDD.h	41;"	d
QSPI_PDD_BAUD_RATE_DIV_2048	.\Static_Code\PDD\QSPI_PDD.h	51;"	d
QSPI_PDD_BAUD_RATE_DIV_256	.\Static_Code\PDD\QSPI_PDD.h	48;"	d
QSPI_PDD_BAUD_RATE_DIV_32	.\Static_Code\PDD\QSPI_PDD.h	45;"	d
QSPI_PDD_BAUD_RATE_DIV_4	.\Static_Code\PDD\QSPI_PDD.h	42;"	d
QSPI_PDD_BAUD_RATE_DIV_4096	.\Static_Code\PDD\QSPI_PDD.h	52;"	d
QSPI_PDD_BAUD_RATE_DIV_512	.\Static_Code\PDD\QSPI_PDD.h	49;"	d
QSPI_PDD_BAUD_RATE_DIV_64	.\Static_Code\PDD\QSPI_PDD.h	46;"	d
QSPI_PDD_BAUD_RATE_DIV_8	.\Static_Code\PDD\QSPI_PDD.h	43;"	d
QSPI_PDD_DisableInterruptMask	.\Static_Code\PDD\QSPI_PDD.h	214;"	d
QSPI_PDD_ERROR	.\Static_Code\PDD\QSPI_PDD.h	55;"	d
QSPI_PDD_EnableBaudDivisorTimes2	.\Static_Code\PDD\QSPI_PDD.h	508;"	d
QSPI_PDD_EnableDevice	.\Static_Code\PDD\QSPI_PDD.h	329;"	d
QSPI_PDD_EnableFaultMode	.\Static_Code\PDD\QSPI_PDD.h	236;"	d
QSPI_PDD_EnableFifoMode	.\Static_Code\PDD\QSPI_PDD.h	1016;"	d
QSPI_PDD_EnableInterruptMask	.\Static_Code\PDD\QSPI_PDD.h	194;"	d
QSPI_PDD_EnableReceiveDma	.\Static_Code\PDD\QSPI_PDD.h	484;"	d
QSPI_PDD_EnableSlaveSelectAutomaticMode	.\Static_Code\PDD\QSPI_PDD.h	600;"	d
QSPI_PDD_EnableSlaveSelectOpenDrainMode	.\Static_Code\PDD\QSPI_PDD.h	576;"	d
QSPI_PDD_EnableSlaveSelectOverrideMode	.\Static_Code\PDD\QSPI_PDD.h	672;"	d
QSPI_PDD_EnableSlaveSelectStrobeMode	.\Static_Code\PDD\QSPI_PDD.h	648;"	d
QSPI_PDD_EnableStopHoldOffMode	.\Static_Code\PDD\QSPI_PDD.h	1162;"	d
QSPI_PDD_EnableTransmitDma	.\Static_Code\PDD\QSPI_PDD.h	460;"	d
QSPI_PDD_EnableWiredOrMode	.\Static_Code\PDD\QSPI_PDD.h	436;"	d
QSPI_PDD_FIRST_EDGE	.\Static_Code\PDD\QSPI_PDD.h	78;"	d
QSPI_PDD_GetRxFifoLevel	.\Static_Code\PDD\QSPI_PDD.h	940;"	d
QSPI_PDD_GetSlaveSelectPinValue	.\Static_Code\PDD\QSPI_PDD.h	530;"	d
QSPI_PDD_GetTxFifoLevel	.\Static_Code\PDD\QSPI_PDD.h	919;"	d
QSPI_PDD_GetWaitDelay	.\Static_Code\PDD\QSPI_PDD.h	1076;"	d
QSPI_PDD_GetWordLength	.\Static_Code\PDD\QSPI_PDD.h	720;"	d
QSPI_PDD_H_	.\Static_Code\PDD\QSPI_PDD.h	9;"	d
QSPI_PDD_LSB_FIRST	.\Static_Code\PDD\QSPI_PDD.h	66;"	d
QSPI_PDD_MASTER_MODE	.\Static_Code\PDD\QSPI_PDD.h	70;"	d
QSPI_PDD_MASTER_MODE_FAULT_FLAG	.\Static_Code\PDD\QSPI_PDD.h	62;"	d
QSPI_PDD_MSB_FIRST	.\Static_Code\PDD\QSPI_PDD.h	67;"	d
QSPI_PDD_RX_BUFFER_FULL	.\Static_Code\PDD\QSPI_PDD.h	56;"	d
QSPI_PDD_RX_BUFFER_FULL_FLAG	.\Static_Code\PDD\QSPI_PDD.h	60;"	d
QSPI_PDD_RX_BUFFER_OVERFLOW_FLAG	.\Static_Code\PDD\QSPI_PDD.h	61;"	d
QSPI_PDD_RX_FIFO_1_OR_MORE	.\Static_Code\PDD\QSPI_PDD.h	117;"	d
QSPI_PDD_RX_FIFO_2_OR_MORE	.\Static_Code\PDD\QSPI_PDD.h	118;"	d
QSPI_PDD_RX_FIFO_3_OR_MORE	.\Static_Code\PDD\QSPI_PDD.h	119;"	d
QSPI_PDD_RX_FIFO_4_OR_MORE	.\Static_Code\PDD\QSPI_PDD.h	120;"	d
QSPI_PDD_ReadControl2Reg	.\Static_Code\PDD\QSPI_PDD.h	1183;"	d
QSPI_PDD_ReadData16bits	.\Static_Code\PDD\QSPI_PDD.h	821;"	d
QSPI_PDD_ReadData8bits	.\Static_Code\PDD\QSPI_PDD.h	802;"	d
QSPI_PDD_ReadDataReceiveReg	.\Static_Code\PDD\QSPI_PDD.h	840;"	d
QSPI_PDD_ReadDataSizeAndControlReg	.\Static_Code\PDD\QSPI_PDD.h	763;"	d
QSPI_PDD_ReadFifoControlReg	.\Static_Code\PDD\QSPI_PDD.h	1037;"	d
QSPI_PDD_ReadStatusAndControlReg	.\Static_Code\PDD\QSPI_PDD.h	394;"	d
QSPI_PDD_ReadStatusFlags	.\Static_Code\PDD\QSPI_PDD.h	350;"	d
QSPI_PDD_ReadWordDelayReg	.\Static_Code\PDD\QSPI_PDD.h	1120;"	d
QSPI_PDD_SECOND_EDGE	.\Static_Code\PDD\QSPI_PDD.h	79;"	d
QSPI_PDD_SLAVE_MODE	.\Static_Code\PDD\QSPI_PDD.h	71;"	d
QSPI_PDD_SS_AS_INPUT	.\Static_Code\PDD\QSPI_PDD.h	90;"	d
QSPI_PDD_SS_AS_OUTPUT	.\Static_Code\PDD\QSPI_PDD.h	91;"	d
QSPI_PDD_SS_IN_HIGH	.\Static_Code\PDD\QSPI_PDD.h	83;"	d
QSPI_PDD_SS_IN_LOW	.\Static_Code\PDD\QSPI_PDD.h	82;"	d
QSPI_PDD_SS_TO_HIGH	.\Static_Code\PDD\QSPI_PDD.h	86;"	d
QSPI_PDD_SS_TO_LOW	.\Static_Code\PDD\QSPI_PDD.h	87;"	d
QSPI_PDD_SetBaudRateDivisor	.\Static_Code\PDD\QSPI_PDD.h	139;"	d
QSPI_PDD_SetClockPhase	.\Static_Code\PDD\QSPI_PDD.h	305;"	d
QSPI_PDD_SetClockPolarity	.\Static_Code\PDD\QSPI_PDD.h	282;"	d
QSPI_PDD_SetDataFeaturesReg	.\Static_Code\PDD\QSPI_PDD.h	371;"	d
QSPI_PDD_SetDataShiftOrder	.\Static_Code\PDD\QSPI_PDD.h	172;"	d
QSPI_PDD_SetMasterSlaveMode	.\Static_Code\PDD\QSPI_PDD.h	259;"	d
QSPI_PDD_SetRxFifoWatermark	.\Static_Code\PDD\QSPI_PDD.h	990;"	d
QSPI_PDD_SetSlaveSelectPinDataDirection	.\Static_Code\PDD\QSPI_PDD.h	624;"	d
QSPI_PDD_SetSlaveSelectPinLevel	.\Static_Code\PDD\QSPI_PDD.h	552;"	d
QSPI_PDD_SetTxFifoWatermark	.\Static_Code\PDD\QSPI_PDD.h	964;"	d
QSPI_PDD_SetWaitDelay	.\Static_Code\PDD\QSPI_PDD.h	1097;"	d
QSPI_PDD_SetWordLength	.\Static_Code\PDD\QSPI_PDD.h	696;"	d
QSPI_PDD_SetWordLengthAndStrobeReg	.\Static_Code\PDD\QSPI_PDD.h	740;"	d
QSPI_PDD_TX_BUFFER_EMPTY	.\Static_Code\PDD\QSPI_PDD.h	57;"	d
QSPI_PDD_TX_BUFFER_EMPTY_FLAG	.\Static_Code\PDD\QSPI_PDD.h	63;"	d
QSPI_PDD_TX_FIFO_1_OR_LESS	.\Static_Code\PDD\QSPI_PDD.h	112;"	d
QSPI_PDD_TX_FIFO_2_OR_LESS	.\Static_Code\PDD\QSPI_PDD.h	113;"	d
QSPI_PDD_TX_FIFO_3_OR_LESS	.\Static_Code\PDD\QSPI_PDD.h	114;"	d
QSPI_PDD_TX_FIFO_EMPTY	.\Static_Code\PDD\QSPI_PDD.h	111;"	d
QSPI_PDD_WriteControl2Reg	.\Static_Code\PDD\QSPI_PDD.h	1203;"	d
QSPI_PDD_WriteData16Bits	.\Static_Code\PDD\QSPI_PDD.h	880;"	d
QSPI_PDD_WriteData8Bits	.\Static_Code\PDD\QSPI_PDD.h	860;"	d
QSPI_PDD_WriteDataSizeAndControlReg	.\Static_Code\PDD\QSPI_PDD.h	783;"	d
QSPI_PDD_WriteDataTransmitReg	.\Static_Code\PDD\QSPI_PDD.h	900;"	d
QSPI_PDD_WriteFifoControlReg	.\Static_Code\PDD\QSPI_PDD.h	1057;"	d
QSPI_PDD_WriteStatusAndControlReg	.\Static_Code\PDD\QSPI_PDD.h	414;"	d
QSPI_PDD_WriteWordDelayReg	.\Static_Code\PDD\QSPI_PDD.h	1140;"	d
QSPI_SPCTL2_REG	.\Static_Code\IO_Map\MC56F82748.h	5492;"	d
QSPI_SPCTL2_SHEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5652;"	d
QSPI_SPCTL2_SHEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5653;"	d
QSPI_SPDRR_R0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5567;"	d
QSPI_SPDRR_R0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5568;"	d
QSPI_SPDRR_R10_MASK	.\Static_Code\IO_Map\MC56F82748.h	5587;"	d
QSPI_SPDRR_R10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5588;"	d
QSPI_SPDRR_R11_MASK	.\Static_Code\IO_Map\MC56F82748.h	5589;"	d
QSPI_SPDRR_R11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5590;"	d
QSPI_SPDRR_R12_MASK	.\Static_Code\IO_Map\MC56F82748.h	5591;"	d
QSPI_SPDRR_R12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5592;"	d
QSPI_SPDRR_R13_MASK	.\Static_Code\IO_Map\MC56F82748.h	5593;"	d
QSPI_SPDRR_R13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5594;"	d
QSPI_SPDRR_R14_MASK	.\Static_Code\IO_Map\MC56F82748.h	5595;"	d
QSPI_SPDRR_R14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5596;"	d
QSPI_SPDRR_R15_MASK	.\Static_Code\IO_Map\MC56F82748.h	5597;"	d
QSPI_SPDRR_R15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5598;"	d
QSPI_SPDRR_R1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5569;"	d
QSPI_SPDRR_R1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5570;"	d
QSPI_SPDRR_R2_MASK	.\Static_Code\IO_Map\MC56F82748.h	5571;"	d
QSPI_SPDRR_R2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5572;"	d
QSPI_SPDRR_R3_MASK	.\Static_Code\IO_Map\MC56F82748.h	5573;"	d
QSPI_SPDRR_R3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5574;"	d
QSPI_SPDRR_R4_MASK	.\Static_Code\IO_Map\MC56F82748.h	5575;"	d
QSPI_SPDRR_R4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5576;"	d
QSPI_SPDRR_R5_MASK	.\Static_Code\IO_Map\MC56F82748.h	5577;"	d
QSPI_SPDRR_R5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5578;"	d
QSPI_SPDRR_R6_MASK	.\Static_Code\IO_Map\MC56F82748.h	5579;"	d
QSPI_SPDRR_R6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5580;"	d
QSPI_SPDRR_R7_MASK	.\Static_Code\IO_Map\MC56F82748.h	5581;"	d
QSPI_SPDRR_R7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5582;"	d
QSPI_SPDRR_R8_MASK	.\Static_Code\IO_Map\MC56F82748.h	5583;"	d
QSPI_SPDRR_R8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5584;"	d
QSPI_SPDRR_R9_MASK	.\Static_Code\IO_Map\MC56F82748.h	5585;"	d
QSPI_SPDRR_R9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5586;"	d
QSPI_SPDRR_REG	.\Static_Code\IO_Map\MC56F82748.h	5488;"	d
QSPI_SPDSR_BD2X_MASK	.\Static_Code\IO_Map\MC56F82748.h	5558;"	d
QSPI_SPDSR_BD2X_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5559;"	d
QSPI_SPDSR_DS	.\Static_Code\IO_Map\MC56F82748.h	5541;"	d
QSPI_SPDSR_DS_MASK	.\Static_Code\IO_Map\MC56F82748.h	5539;"	d
QSPI_SPDSR_DS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5540;"	d
QSPI_SPDSR_RDMAEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5560;"	d
QSPI_SPDSR_RDMAEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5561;"	d
QSPI_SPDSR_REG	.\Static_Code\IO_Map\MC56F82748.h	5487;"	d
QSPI_SPDSR_SPR3_MASK	.\Static_Code\IO_Map\MC56F82748.h	5542;"	d
QSPI_SPDSR_SPR3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5543;"	d
QSPI_SPDSR_SSB_AUTO_MASK	.\Static_Code\IO_Map\MC56F82748.h	5550;"	d
QSPI_SPDSR_SSB_AUTO_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5551;"	d
QSPI_SPDSR_SSB_DATA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5554;"	d
QSPI_SPDSR_SSB_DATA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5555;"	d
QSPI_SPDSR_SSB_DDR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5548;"	d
QSPI_SPDSR_SSB_DDR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5549;"	d
QSPI_SPDSR_SSB_IN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5556;"	d
QSPI_SPDSR_SSB_IN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5557;"	d
QSPI_SPDSR_SSB_ODM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5552;"	d
QSPI_SPDSR_SSB_ODM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5553;"	d
QSPI_SPDSR_SSB_OVER_MASK	.\Static_Code\IO_Map\MC56F82748.h	5544;"	d
QSPI_SPDSR_SSB_OVER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5545;"	d
QSPI_SPDSR_SSB_STRB_MASK	.\Static_Code\IO_Map\MC56F82748.h	5546;"	d
QSPI_SPDSR_SSB_STRB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5547;"	d
QSPI_SPDSR_TDMAEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5562;"	d
QSPI_SPDSR_TDMAEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5563;"	d
QSPI_SPDSR_WOM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5564;"	d
QSPI_SPDSR_WOM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5565;"	d
QSPI_SPDTR_REG	.\Static_Code\IO_Map\MC56F82748.h	5489;"	d
QSPI_SPDTR_T0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5600;"	d
QSPI_SPDTR_T0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5601;"	d
QSPI_SPDTR_T10_MASK	.\Static_Code\IO_Map\MC56F82748.h	5620;"	d
QSPI_SPDTR_T10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5621;"	d
QSPI_SPDTR_T11_MASK	.\Static_Code\IO_Map\MC56F82748.h	5622;"	d
QSPI_SPDTR_T11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5623;"	d
QSPI_SPDTR_T12_MASK	.\Static_Code\IO_Map\MC56F82748.h	5624;"	d
QSPI_SPDTR_T12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5625;"	d
QSPI_SPDTR_T13_MASK	.\Static_Code\IO_Map\MC56F82748.h	5626;"	d
QSPI_SPDTR_T13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5627;"	d
QSPI_SPDTR_T14_MASK	.\Static_Code\IO_Map\MC56F82748.h	5628;"	d
QSPI_SPDTR_T14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5629;"	d
QSPI_SPDTR_T15_MASK	.\Static_Code\IO_Map\MC56F82748.h	5630;"	d
QSPI_SPDTR_T15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5631;"	d
QSPI_SPDTR_T1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5602;"	d
QSPI_SPDTR_T1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5603;"	d
QSPI_SPDTR_T2_MASK	.\Static_Code\IO_Map\MC56F82748.h	5604;"	d
QSPI_SPDTR_T2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5605;"	d
QSPI_SPDTR_T3_MASK	.\Static_Code\IO_Map\MC56F82748.h	5606;"	d
QSPI_SPDTR_T3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5607;"	d
QSPI_SPDTR_T4_MASK	.\Static_Code\IO_Map\MC56F82748.h	5608;"	d
QSPI_SPDTR_T4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5609;"	d
QSPI_SPDTR_T5_MASK	.\Static_Code\IO_Map\MC56F82748.h	5610;"	d
QSPI_SPDTR_T5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5611;"	d
QSPI_SPDTR_T6_MASK	.\Static_Code\IO_Map\MC56F82748.h	5612;"	d
QSPI_SPDTR_T6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5613;"	d
QSPI_SPDTR_T7_MASK	.\Static_Code\IO_Map\MC56F82748.h	5614;"	d
QSPI_SPDTR_T7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5615;"	d
QSPI_SPDTR_T8_MASK	.\Static_Code\IO_Map\MC56F82748.h	5616;"	d
QSPI_SPDTR_T8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5617;"	d
QSPI_SPDTR_T9_MASK	.\Static_Code\IO_Map\MC56F82748.h	5618;"	d
QSPI_SPDTR_T9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5619;"	d
QSPI_SPFIFO_FIFO_ENA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5633;"	d
QSPI_SPFIFO_FIFO_ENA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5634;"	d
QSPI_SPFIFO_REG	.\Static_Code\IO_Map\MC56F82748.h	5490;"	d
QSPI_SPFIFO_RFCNT	.\Static_Code\IO_Map\MC56F82748.h	5643;"	d
QSPI_SPFIFO_RFCNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5641;"	d
QSPI_SPFIFO_RFCNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5642;"	d
QSPI_SPFIFO_RFWM	.\Static_Code\IO_Map\MC56F82748.h	5637;"	d
QSPI_SPFIFO_RFWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5635;"	d
QSPI_SPFIFO_RFWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5636;"	d
QSPI_SPFIFO_TFCNT	.\Static_Code\IO_Map\MC56F82748.h	5646;"	d
QSPI_SPFIFO_TFCNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5644;"	d
QSPI_SPFIFO_TFCNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5645;"	d
QSPI_SPFIFO_TFWM	.\Static_Code\IO_Map\MC56F82748.h	5640;"	d
QSPI_SPFIFO_TFWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5638;"	d
QSPI_SPFIFO_TFWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5639;"	d
QSPI_SPSCR_CPHA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5521;"	d
QSPI_SPSCR_CPHA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5522;"	d
QSPI_SPSCR_CPOL_MASK	.\Static_Code\IO_Map\MC56F82748.h	5523;"	d
QSPI_SPSCR_CPOL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5524;"	d
QSPI_SPSCR_DSO_MASK	.\Static_Code\IO_Map\MC56F82748.h	5533;"	d
QSPI_SPSCR_DSO_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5534;"	d
QSPI_SPSCR_ERRIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5531;"	d
QSPI_SPSCR_ERRIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5532;"	d
QSPI_SPSCR_MODFEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5529;"	d
QSPI_SPSCR_MODFEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5530;"	d
QSPI_SPSCR_MODF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5511;"	d
QSPI_SPSCR_MODF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5512;"	d
QSPI_SPSCR_OVRF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5513;"	d
QSPI_SPSCR_OVRF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5514;"	d
QSPI_SPSCR_REG	.\Static_Code\IO_Map\MC56F82748.h	5486;"	d
QSPI_SPSCR_SPE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5519;"	d
QSPI_SPSCR_SPE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5520;"	d
QSPI_SPSCR_SPMSTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5525;"	d
QSPI_SPSCR_SPMSTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5526;"	d
QSPI_SPSCR_SPR	.\Static_Code\IO_Map\MC56F82748.h	5537;"	d
QSPI_SPSCR_SPRF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5515;"	d
QSPI_SPSCR_SPRF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5516;"	d
QSPI_SPSCR_SPRIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5527;"	d
QSPI_SPSCR_SPRIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5528;"	d
QSPI_SPSCR_SPR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5535;"	d
QSPI_SPSCR_SPR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5536;"	d
QSPI_SPSCR_SPTE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5509;"	d
QSPI_SPSCR_SPTE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5510;"	d
QSPI_SPSCR_SPTIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5517;"	d
QSPI_SPSCR_SPTIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5518;"	d
QSPI_SPWAIT_REG	.\Static_Code\IO_Map\MC56F82748.h	5491;"	d
QSPI_SPWAIT_WAIT	.\Static_Code\IO_Map\MC56F82748.h	5650;"	d
QSPI_SPWAIT_WAIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5648;"	d
QSPI_SPWAIT_WAIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5649;"	d
R0	.\Static_Code\System\CPU_Init.h	/^    uint16_t* R0;                      \/* Shadow register R0. *\/$/;"	m	struct:__anon63
R1	.\Static_Code\System\CPU_Init.h	/^    uint16_t* R1;                      \/* Shadow register R1. *\/$/;"	m	struct:__anon63
R2	.\Static_Code\System\CPU_Init.h	/^    uint16_t* R2;                      \/* Shadow register R2. In InitShadowRegs() this register is used to index through TShadowRegs so is placed as last struct item *\/$/;"	m	struct:__anon63
R3	.\Static_Code\System\CPU_Init.h	/^    uint16_t* R3;                      \/* Shadow register R3. *\/$/;"	m	struct:__anon63
R4	.\Static_Code\System\CPU_Init.h	/^    uint16_t* R4;                      \/* Shadow register R4. *\/$/;"	m	struct:__anon63
R5	.\Static_Code\System\CPU_Init.h	/^    uint16_t* R5;                      \/* Shadow register R5. *\/$/;"	m	struct:__anon63
RA	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RA;                                     \/**< I2C Range Address register, offset: 0x7 *\/$/;"	m	struct:I2C_MemMap
RATE	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RATE;                                   \/**< QSCI Baud Rate Register, offset: 0x0 *\/$/;"	m	struct:QSCI_MemMap
RAWDATA	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RAWDATA;                                \/**< GPIO Raw Data Register, offset: 0xA *\/$/;"	m	struct:GPIO_MemMap
RDY	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RDY;                                    \/**< ADC Ready Register, offset: 0xA *\/$/;"	m	struct:ADC_MemMap
RDY2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RDY2;                                   \/**< ADC Ready Register 2, offset: 0x5B *\/$/;"	m	struct:ADC_MemMap
REQC	.\Static_Code\IO_Map\MC56F82748.h	/^    uint32_t REQC;                                   \/**< DMA Request Control Register, offset: 0x0 *\/$/;"	m	union:DMA_MemMap::__anon56
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RESERVED_0[1];$/;"	m	struct:PWM_MemMap::__anon59
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RESERVED_0[2];$/;"	m	struct:TMR_MemMap::__anon61
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[124];$/;"	m	struct:FMC_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[126];$/;"	m	struct:DMA_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[1];$/;"	m	struct:CAN_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[1];$/;"	m	struct:INTC_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[1];$/;"	m	struct:OCCS_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[2];$/;"	m	struct:ADC_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_0[4];$/;"	m	struct:SIM_MemMap
RESERVED_0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t RESERVED_0[8];$/;"	m	struct:MCM_MemMap
RESERVED_1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RESERVED_1[4];$/;"	m	struct:PWM_MemMap::__anon59
RESERVED_1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_1[1];$/;"	m	struct:CAN_MemMap
RESERVED_1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_1[1];$/;"	m	struct:SIM_MemMap
RESERVED_1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_1[96];$/;"	m	struct:FMC_MemMap
RESERVED_1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t RESERVED_1[4];$/;"	m	struct:MCM_MemMap
RESERVED_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_2[1];$/;"	m	struct:SIM_MemMap
RESERVED_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint8_t RESERVED_2[4];$/;"	m	struct:MCM_MemMap
RESERVED_3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_3[1];$/;"	m	struct:SIM_MemMap
RESERVED_4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_4[2];$/;"	m	struct:SIM_MemMap
RESERVED_5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_5[3];$/;"	m	struct:SIM_MemMap
RESERVED_6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RESERVED_6[23];$/;"	m	struct:SIM_MemMap
RFLG	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RFLG;                                   \/**< MSCAN Receiver Flag Register, offset: 0x4 *\/$/;"	m	struct:CAN_MemMap
RIER	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RIER;                                   \/**< MSCAN Receiver Interrupt Enable Register, offset: 0x5 *\/$/;"	m	struct:CAN_MemMap
RPCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t RPCR;                                   \/**< Resource Protection Control Register, offset: 0x20 *\/$/;"	m	struct:MCM_MemMap
RSLT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RSLT[16];                               \/**< ADC Result Registers with sign extension, array offset: 0xE, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
RSLT_2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RSLT_2[4];                              \/**< ADC Result Registers 2 with sign extension, array offset: 0x5F, array step: 0x1 *\/$/;"	m	struct:ADC_MemMap
RSTAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RSTAT;                                  \/**< Reset Status Register, offset: 0x1 *\/$/;"	m	struct:SIM_MemMap
RSTSRC_COP_CPU	.\Static_Code\System\PE_Const.h	18;"	d
RSTSRC_COP_LOR	.\Static_Code\System\PE_Const.h	17;"	d
RSTSRC_COP_WINDOW	.\Static_Code\System\PE_Const.h	19;"	d
RSTSRC_PIN	.\Static_Code\System\PE_Const.h	16;"	d
RSTSRC_POR	.\Static_Code\System\PE_Const.h	15;"	d
RSTSRC_SWR	.\Static_Code\System\PE_Const.h	20;"	d
RXERR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXERR;                                  \/**< MSCAN Receive Error Counter Register, offset: 0xE *\/$/;"	m	struct:CAN_MemMap
RXFG_DLR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXFG_DLR;                               \/**< MSCAN Receive Buffer Data Length Register, offset: 0x2C *\/$/;"	m	struct:CAN_MemMap
RXFG_DSR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXFG_DSR[8];                            \/**< Receive Buffer Data Segment Registers, array offset: 0x24, array step: 0x1 *\/$/;"	m	struct:CAN_MemMap
RXFG_IDR0_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RXFG_IDR0_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 0 - Extended Identifer Mapping, offset: 0x20 *\/$/;"	m	union:CAN_MemMap::__anon48
RXFG_IDR0_STD	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RXFG_IDR0_STD;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 0 - Standard Identifer Mapping, offset: 0x20 *\/$/;"	m	union:CAN_MemMap::__anon48
RXFG_IDR1_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RXFG_IDR1_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 1 - Extended Identifer Mapping, offset: 0x21 *\/$/;"	m	union:CAN_MemMap::__anon49
RXFG_IDR1_STD	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t RXFG_IDR1_STD;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 1 - Standard Identifier Mapping, offset: 0x21 *\/$/;"	m	union:CAN_MemMap::__anon49
RXFG_IDR2_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXFG_IDR2_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 2 - Extended Identifer Mapping, offset: 0x22 *\/$/;"	m	struct:CAN_MemMap
RXFG_IDR3_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXFG_IDR3_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 3 - Extended Identifier Mapping, offset: 0x23 *\/$/;"	m	struct:CAN_MemMap
RXFG_TSRH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXFG_TSRH;                              \/**< Receive Buffer Time Stamp Register - High Byte, offset: 0x2E *\/$/;"	m	struct:CAN_MemMap
RXFG_TSRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t RXFG_TSRL;                              \/**< Receive Buffer Time Stamp Register - Low Byte, offset: 0x2F *\/$/;"	m	struct:CAN_MemMap
R_MODE	.\Project_Settings\Startup_Code\56F83x_init.asm	/^R_MODE                                                           EQU  $0020$/;"	d
ReceivedBreaks	.\Generated_Code\PE_LDD.h	/^  uint32_t ReceivedBreaks;             \/* Number of received break characters *\/$/;"	m	struct:__anon19
ReceivedChars	.\Generated_Code\PE_LDD.h	/^  uint32_t ReceivedChars;              \/* Number of received characters *\/$/;"	m	struct:__anon19
Reg32bit	.\Static_Code\System\PE_Types.h	/^        Word32 Reg32bit;$/;"	m	union:__anon67
RegParts	.\Static_Code\System\PE_Types.h	/^        } RegParts;$/;"	m	union:__anon67	typeref:struct:__anon67::__anon68
Reserved	.\Static_Code\System\PE_Types.h	/^        UWord16 Reserved :13;$/;"	m	struct:__anon74
ResultXORed	.\Generated_Code\PE_LDD.h	/^  bool ResultXORed;                    \/* Result XORed? *\/$/;"	m	struct:__anon13
RevolutionHoldReg	.\Static_Code\System\PE_Types.h	/^        union { Word16 RevolutionHoldReg;$/;"	m	union:__anon69::__anon71
RevolutionScale	.\Static_Code\System\PE_Types.h	/^        UWord16 RevolutionScale;$/;"	m	struct:__anon73
RxChars	.\Generated_Code\PE_LDD.h	/^  uint32_t RxChars;                    \/* Number of received characters *\/$/;"	m	struct:__anon26
RxChars	.\Generated_Code\PE_LDD.h	/^  uint32_t RxChars;                    \/* Number of received characters *\/$/;"	m	struct:__anon27
RxFrames	.\Generated_Code\PE_LDD.h	/^  uint32_t RxFrames;                   \/* Received frame counter *\/$/;"	m	struct:__anon40
RxOverrun	.\Generated_Code\PE_LDD.h	/^  uint32_t RxOverrun;                  \/* Receiver FIFO overrun counter *\/$/;"	m	struct:__anon40
RxOverruns	.\Generated_Code\PE_LDD.h	/^  uint32_t RxOverruns;                 \/* Number of receiver overruns, which have occured *\/ $/;"	m	struct:__anon26
RxOverruns	.\Generated_Code\PE_LDD.h	/^  uint32_t RxOverruns;                 \/* Number of receiver overruns, which have occured *\/$/;"	m	struct:__anon27
RxParityErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t RxParityErrors;             \/* Number of receiver parity errors, which have occured *\/  $/;"	m	struct:__anon26
RxParityErrors	.\Generated_Code\PE_LDD.h	/^  uint32_t RxParityErrors;             \/* Number of receiver parity errors, which have occured *\/$/;"	m	struct:__anon27
RxWarnings	.\Generated_Code\PE_LDD.h	/^  uint32_t RxWarnings;                 \/* Reception warning counter *\/$/;"	m	struct:__anon40
S	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t S;                                      \/**< I2C Status register, offset: 0x3 *\/$/;"	m	struct:I2C_MemMap
S0090000000044415441DC	.\FLASH_SDM\ramISR.elf.x.S	/^S0090000000044415441DC$/;"	l
S00C0000000050524F4752414DDB	.\FLASH_SDM\ramISR.elf.p.S	/^S00C0000000050524F4752414DDB$/;"	l
S0110000000050524F4752414D264441544196	.\FLASH_SDM\ramISR.elf.S	/^S0110000000050524F4752414D264441544196$/;"	l
S329000004C204E73FD818E412E600004082001018E441E20000408401003BF818E500E700E709E7000076	.\FLASH_SDM\ramISR.elf.S	/^S329000004C204E73FD818E412E600004082001018E441E20000408401003BF818E500E700E709E7000076$/;"	l
S329000004C204E73FD818E412E600004082001018E441E20000408401003BF818E500E700E709E7000076	.\FLASH_SDM\ramISR.elf.p.S	/^S329000004C204E73FD818E412E600004082001018E441E20000408401003BF818E500E700E709E7000076$/;"	l
S3A10000047480E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEB890403F400E700E700E701D400E781E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEBA0046B8400E700E700E701D400E781E8088F16A300E700E71AE4120000001BE4C204000019E400F0000030E00AEBBA046B8400E700E700E7618400E700E700E780E580EA80EB54E26C0201E77EA939	.\FLASH_SDM\ramISR.elf.S	/^S3A10000047480E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEB890403F400E700E700E701D400E781E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEBA0046B8400E700E700E701D400E781E8088F16A300E700E71AE4120000001BE4C204000019E400F0000030E00AEBBA046B8400E700E700E7618400E700E700E780E580EA80EB54E26C0201E77EA939$/;"	l
S3A10000047480E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEB890403F400E700E700E701D400E781E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEBA0046B8400E700E700E701D400E781E8088F16A300E700E71AE4120000001BE4C204000019E400F0000030E00AEBBA046B8400E700E700E7618400E700E700E780E580EA80EB54E26C0201E77EA939	.\FLASH_SDM\ramISR.elf.p.S	/^S3A10000047480E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEB890403F400E700E700E701D400E781E8088F13A300E700E71AE4400000001BE4E604000019E41200000030E00AEBA0046B8400E700E700E701D400E781E8088F16A300E700E71AE4120000001BE4C204000019E400F0000030E00AEBBA046B8400E700E700E7618400E700E700E780E580EA80EB54E26C0201E77EA939$/;"	l
S3A9000004D400000000000000000000000000000000000000000000000000000000000000000000000000000100020003000400050006000700080009000A000B000C000D000E000F0010001100120013001400150016001700180019001A001B001C001D001E001F0020002100220023002400250026002700280029002A002B002C002D002E002F0030003100320033003400350036003700380039003A003B003C003D003E003F009E	.\FLASH_SDM\ramISR.elf.S	/^S3A9000004D400000000000000000000000000000000000000000000000000000000000000000000000000000100020003000400050006000700080009000A000B000C000D000E000F0010001100120013001400150016001700180019001A001B001C001D001E001F0020002100220023002400250026002700280029002A002B002C002D002E002F0030003100320033003400350036003700380039003A003B003C003D003E003F009E$/;"	l
S3A9000004D400000000000000000000000000000000000000000000000000000000000000000000000000000100020003000400050006000700080009000A000B000C000D000E000F0010001100120013001400150016001700180019001A001B001C001D001E001F0020002100220023002400250026002700280029002A002B002C002D002E002F0030003100320033003400350036003700380039003A003B003C003D003E003F009E	.\FLASH_SDM\ramISR.elf.p.S	/^S3A9000004D400000000000000000000000000000000000000000000000000000000000000000000000000000100020003000400050006000700080009000A000B000C000D000E000F0010001100120013001400150016001700180019001A001B001C001D001E001F0020002100220023002400250026002700280029002A002B002C002D002E002F0030003100320033003400350036003700380039003A003B003C003D003E003F009E$/;"	l
S3AD0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000052	.\FLASH_SDM\ramISR.elf.x.S	/^S3AD0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000052$/;"	l
S3AD0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050	.\FLASH_SDM\ramISR.elf.S	/^S3AD0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050$/;"	l
S3C90000007C54E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E200F054E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0344	.\FLASH_SDM\ramISR.elf.S	/^S3C90000007C54E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E200F054E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0344$/;"	l
S3C90000007C54E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E200F054E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0344	.\FLASH_SDM\ramISR.elf.p.S	/^S3C90000007C54E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E200F054E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0344$/;"	l
S3FD0000000054E1780354E1780354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E037E	.\FLASH_SDM\ramISR.elf.S	/^S3FD0000000054E1780354E1780354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E037E$/;"	l
S3FD0000000054E1780354E1780354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E037E	.\FLASH_SDM\ramISR.elf.p.S	/^S3FD0000000054E1780354E1780354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E0354E26E037E$/;"	l
S3FD0000020818E40CE400004082040019E443E2000018E443E2000014F04187FEFF887882E0197815D018E44DE200004080010018E408E30000408000CF19E409E3000018E409E3000014F14087FFCB18785083000815D019E40FE4000018E40FE4000014F140878FFF18785083800015D018E40CE400004080040008E780EA54E2480208E77B827F9A488756001FD81FF97FB815D818E40CE400004082040018E443E200004080010018E441E200004080010018E442E20000408201001FF820807CD855001FF822807E9F08E754E2FD0318E408E200007CF0120014D079A918E4C4E6000080431111100018E413E600004086000018E4C6E60000408682	.\FLASH_SDM\ramISR.elf.S	/^S3FD0000020818E40CE400004082040019E443E2000018E443E2000014F04187FEFF887882E0197815D018E44DE200004080010018E408E30000408000CF19E409E3000018E409E3000014F14087FFCB18785083000815D019E40FE4000018E40FE4000014F140878FFF18785083800015D018E40CE400004080040008E780EA54E2480208E77B827F9A488756001FD81FF97FB815D818E40CE400004082040018E443E200004080010018E441E200004080010018E442E20000408201001FF820807CD855001FF822807E9F08E754E2FD0318E408E200007CF0120014D079A918E4C4E6000080431111100018E413E600004086000018E4C6E60000408682$/;"	l
S3FD0000020818E40CE400004082040019E443E2000018E443E2000014F04187FEFF887882E0197815D018E44DE200004080010018E408E30000408000CF19E409E3000018E409E3000014F14087FFCB18785083000815D019E40FE4000018E40FE4000014F140878FFF18785083800015D018E40CE400004080040008E780EA54E2480208E77B827F9A488756001FD81FF97FB815D818E40CE400004082040018E443E200004080010018E441E200004080010018E442E20000408201001FF820807CD855001FF822807E9F08E754E2FD0318E408E200007CF0120014D079A918E4C4E6000080431111100018E413E600004086000018E4C6E60000408682	.\FLASH_SDM\ramISR.elf.p.S	/^S3FD0000020818E40CE400004082040019E443E2000018E443E2000014F04187FEFF887882E0197815D018E44DE200004080010018E408E30000408000CF19E409E3000018E409E3000014F14087FFCB18785083000815D019E40FE4000018E40FE4000014F140878FFF18785083800015D018E40CE400004080040008E780EA54E2480208E77B827F9A488756001FD81FF97FB815D818E40CE400004082040018E443E200004080010018E441E200004080010018E442E20000408201001FF820807CD855001FF822807E9F08E754E2FD0318E408E200007CF0120014D079A918E4C4E6000080431111100018E413E600004086000018E4C6E60000408682$/;"	l
S3FD00000284000018E4CAE600004086000018E411E600004086000018E401E600004086010018E402E600004086008018E403E600004086000418E415E600004086000018E405E600004086000018E407E600004086F40118E409E600004086010018E40BE600004086FA0018E40DE600004086000018E40FE600004086000018E406E600004086000018E408E600004086000018E40AE600004086000018E40CE600004086000018E40EE600004086000018E410E600004086040118E416E600004086F0FF18E417E600004086F0FF18E418E600004086000018E419E600004086000018E41BE600004086000018E41DE600004086000018E41FE6000059	.\FLASH_SDM\ramISR.elf.S	/^S3FD00000284000018E4CAE600004086000018E411E600004086000018E401E600004086010018E402E600004086008018E403E600004086000418E415E600004086000018E405E600004086000018E407E600004086F40118E409E600004086010018E40BE600004086FA0018E40DE600004086000018E40FE600004086000018E406E600004086000018E408E600004086000018E40AE600004086000018E40CE600004086000018E40EE600004086000018E410E600004086040118E416E600004086F0FF18E417E600004086F0FF18E418E600004086000018E419E600004086000018E41BE600004086000018E41DE600004086000018E41FE6000059$/;"	l
S3FD00000284000018E4CAE600004086000018E411E600004086000018E401E600004086010018E402E600004086008018E403E600004086000418E415E600004086000018E405E600004086000018E407E600004086F40118E409E600004086010018E40BE600004086FA0018E40DE600004086000018E40FE600004086000018E406E600004086000018E408E600004086000018E40AE600004086000018E40CE600004086000018E40EE600004086000018E410E600004086040118E416E600004086F0FF18E417E600004086F0FF18E418E600004086000018E419E600004086000018E41BE600004086000018E41DE600004086000018E41FE6000059	.\FLASH_SDM\ramISR.elf.p.S	/^S3FD00000284000018E4CAE600004086000018E411E600004086000018E401E600004086010018E402E600004086008018E403E600004086000418E415E600004086000018E405E600004086000018E407E600004086F40118E409E600004086010018E40BE600004086FA0018E40DE600004086000018E40FE600004086000018E406E600004086000018E408E600004086000018E40AE600004086000018E40CE600004086000018E40EE600004086000018E410E600004086040118E416E600004086F0FF18E417E600004086F0FF18E418E600004086000018E419E600004086000018E41BE600004086000018E41DE600004086000018E41FE6000059$/;"	l
S3FD000003004086000018E4C8E600004086000018E4CCE600004086000018E4C1E60000408011F118E4C2E60000408003FF18E4C3E6000040800F0018E4C5E600004086000018E4C0E60000804311F1000118E41AE600004086000018E41CE600004086000018E41EE600004086000018E4C4E6000080430F1F010018E4CBE6000040860F0F18E4C7E6000040860F0F18E4C6E600004086000018E4CAE600004086000018E4C4E600004082000118E412E600004086FF3F18E413E600004086001018E414E600004086000018E4C9E600004086000018E4CDE600004086000008E704E701E77E9F18E500E700E709E754E2750208E718E423E4000014F054	.\FLASH_SDM\ramISR.elf.S	/^S3FD000003004086000018E4C8E600004086000018E4CCE600004086000018E4C1E60000408011F118E4C2E60000408003FF18E4C3E6000040800F0018E4C5E600004086000018E4C0E60000804311F1000118E41AE600004086000018E41CE600004086000018E41EE600004086000018E4C4E6000080430F1F010018E4CBE6000040860F0F18E4C7E6000040860F0F18E4C6E600004086000018E4CAE600004086000018E4C4E600004082000118E412E600004086FF3F18E413E600004086001018E414E600004086000018E4C9E600004086000018E4CDE600004086000008E704E701E77E9F18E500E700E709E754E2750208E718E423E4000014F054$/;"	l
S3FD000003004086000018E4C8E600004086000018E4CCE600004086000018E4C1E60000408011F118E4C2E60000408003FF18E4C3E6000040800F0018E4C5E600004086000018E4C0E60000804311F1000118E41AE600004086000018E41CE600004086000018E41EE600004086000018E4C4E6000080430F1F010018E4CBE6000040860F0F18E4C7E6000040860F0F18E4C6E600004086000018E4CAE600004086000018E4C4E600004082000118E412E600004086FF3F18E413E600004086001018E414E600004086000018E4C9E600004086000018E4CDE600004086000008E704E701E77E9F18E500E700E709E754E2750208E718E423E4000014F054	.\FLASH_SDM\ramISR.elf.p.S	/^S3FD000003004086000018E4C8E600004086000018E4CCE600004086000018E4C1E60000408011F118E4C2E60000408003FF18E4C3E6000040800F0018E4C5E600004086000018E4C0E60000804311F1000118E41AE600004086000018E41CE600004086000018E41EE600004086000018E4C4E6000080430F1F010018E4CBE6000040860F0F18E4C7E6000040860F0F18E4C6E600004086000018E4CAE600004086000018E4C4E600004082000118E412E600004086FF3F18E413E600004086001018E414E600004086000018E4C9E600004086000018E4CDE600004086000008E704E701E77E9F18E500E700E709E754E2750208E718E423E4000014F054$/;"	l
S3FD0000037C508900010CA000E700E718E423E400004082040018E400E400004082100018E420E300004086000319E4B4E2000018E4B4E2000014F0458700FC887A18E42CE4000014F04187FF0388784087FF03187850830004597815D018E4B4E200004080008018E4B0E2000040800C0019E4B0E2000018E4B0E2000014F14087EFFF18785083800015D018E4B1E2000080437F0F31007DDF2C0011A97DDF2C0018E4B2E2000014F05089200077A100E700E77DF02C00434401007DD02C007DF02C00435C01006CA100E700E718E4B0E200004082010019E4B0E2000018E4B0E2000014F14087FF07187815D018E40BE400004086000418E4B8E2000072	.\FLASH_SDM\ramISR.elf.S	/^S3FD0000037C508900010CA000E700E718E423E400004082040018E400E400004082100018E420E300004086000319E4B4E2000018E4B4E2000014F0458700FC887A18E42CE4000014F04187FF0388784087FF03187850830004597815D018E4B4E200004080008018E4B0E2000040800C0019E4B0E2000018E4B0E2000014F14087EFFF18785083800015D018E4B1E2000080437F0F31007DDF2C0011A97DDF2C0018E4B2E2000014F05089200077A100E700E77DF02C00434401007DD02C007DF02C00435C01006CA100E700E718E4B0E200004082010019E4B0E2000018E4B0E2000014F14087FF07187815D018E40BE400004086000418E4B8E2000072$/;"	l
S3FD0000037C508900010CA000E700E718E423E400004082040018E400E400004082100018E420E300004086000319E4B4E2000018E4B4E2000014F0458700FC887A18E42CE4000014F04187FF0388784087FF03187850830004597815D018E4B4E200004080008018E4B0E2000040800C0019E4B0E2000018E4B0E2000014F14087EFFF18785083800015D018E4B1E2000080437F0F31007DDF2C0011A97DDF2C0018E4B2E2000014F05089200077A100E700E77DF02C00434401007DD02C007DF02C00435C01006CA100E700E718E4B0E200004082010019E4B0E2000018E4B0E2000014F14087FF07187815D018E40BE400004086000418E4B8E2000072	.\FLASH_SDM\ramISR.elf.p.S	/^S3FD0000037C508900010CA000E700E718E423E400004082040018E400E400004082100018E420E300004086000319E4B4E2000018E4B4E2000014F0458700FC887A18E42CE4000014F04187FF0388784087FF03187850830004597815D018E4B4E200004080008018E4B0E2000040800C0019E4B0E2000018E4B0E2000014F14087EFFF18785083800015D018E4B1E2000080437F0F31007DDF2C0011A97DDF2C0018E4B2E2000014F05089200077A100E700E77DF02C00434401007DD02C007DF02C00435C01006CA100E700E718E4B0E200004082010019E4B0E2000018E4B0E2000014F14087FF07187815D018E40BE400004086000418E4B8E2000072$/;"	l
S3FD000003F84086000054E1450408E706E700E700E708E4000009E400000AE400000BE400000CE400000DE400000EE400005987FFFF5A87FFFF00E700E706E719E4A0E2000018E42DE4000014F0418700F08878408700F0187815D018E433E200004082100018E433E200004082010018E433E200004082020018E433E200004082040018E433E200004082080054E2080254E2750354E244025D81000308E75C83008000E700E75C81B001FFE4848A9B8F9B8F00E700E718E45C010000488D010002A000E770812B8180E900E71FD97B811FD97B8208E4FFFF3FD81FE57B8214E71AE40600000019E45400000080E400E730E00AEB720400E701D400E715	.\FLASH_SDM\ramISR.elf.S	/^S3FD000003F84086000054E1450408E706E700E700E708E4000009E400000AE400000BE400000CE400000DE400000EE400005987FFFF5A87FFFF00E700E706E719E4A0E2000018E42DE4000014F0418700F08878408700F0187815D018E433E200004082100018E433E200004082010018E433E200004082020018E433E200004082040018E433E200004082080054E2080254E2750354E244025D81000308E75C83008000E700E75C81B001FFE4848A9B8F9B8F00E700E718E45C010000488D010002A000E770812B8180E900E71FD97B811FD97B8208E4FFFF3FD81FE57B8214E71AE40600000019E45400000080E400E730E00AEB720400E701D400E715$/;"	l
S3FD000003F84086000054E1450408E706E700E700E708E4000009E400000AE400000BE400000CE400000DE400000EE400005987FFFF5A87FFFF00E700E706E719E4A0E2000018E42DE4000014F0418700F08878408700F0187815D018E433E200004082100018E433E200004082010018E433E200004082020018E433E200004082040018E433E200004082080054E2080254E2750354E244025D81000308E75C83008000E700E75C81B001FFE4848A9B8F9B8F00E700E718E45C010000488D010002A000E770812B8180E900E71FD97B811FD97B8208E4FFFF3FD81FE57B8214E71AE40600000019E45400000080E400E730E00AEB720400E701D400E715	.\FLASH_SDM\ramISR.elf.p.S	/^S3FD000003F84086000054E1450408E706E700E700E708E4000009E400000AE400000BE400000CE400000DE400000EE400005987FFFF5A87FFFF00E700E706E719E4A0E2000018E42DE4000014F0418700F08878408700F0187815D018E433E200004082100018E433E200004082010018E433E200004082020018E433E200004082040018E433E200004082080054E2080254E2750354E244025D81000308E75C83008000E700E75C81B001FFE4848A9B8F9B8F00E700E718E45C010000488D010002A000E770812B8180E900E71FD97B811FD97B8208E4FFFF3FD81FE57B8214E71AE40600000019E45400000080E400E730E00AEB720400E701D400E715$/;"	l
S705000003787F	.\FLASH_SDM\ramISR.elf.S	/^S705000003787F$/;"	l
S705000003787F	.\FLASH_SDM\ramISR.elf.p.S	/^S705000003787F$/;"	l
S705000003787F	.\FLASH_SDM\ramISR.elf.x.S	/^S705000003787F$/;"	l
SAR	.\Static_Code\IO_Map\MC56F82748.h	/^    uint32_t SAR;                                    \/**< Source Address Register, array offset: 0x80, array step: 0x8 *\/$/;"	m	struct:DMA_MemMap::__anon57
SA_MODE	.\Project_Settings\Startup_Code\56F83x_init.asm	/^SA_MODE                                                          EQU  $0010$/;"	d
SCHLTEN	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCHLTEN;                                \/**< ADC Scan Halted Interrupt Enable Register, offset: 0x55 *\/$/;"	m	struct:ADC_MemMap
SCHLTEN2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCHLTEN2;                               \/**< ADC Scan Halted Interrupt Enable Register 2, offset: 0x71 *\/$/;"	m	struct:ADC_MemMap
SCLLowTimeout	.\Generated_Code\PE_LDD.h	/^  uint32_t SCLLowTimeout;              \/* Number of SCL low timeout occur. *\/$/;"	m	struct:__anon25
SCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR;                                    \/**< CMP Status and Control Register, offset: 0x3 *\/$/;"	m	struct:CMP_MemMap
SCR0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR0;                                   \/**< Software Control Register, offset: 0x45 *\/$/;"	m	struct:SIM_MemMap
SCR1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR1;                                   \/**< Software Control Register 1, offset: 0x46 *\/$/;"	m	struct:SIM_MemMap
SCR2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR2;                                   \/**< Software Control Register 2, offset: 0x47 *\/$/;"	m	struct:SIM_MemMap
SCR3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR3;                                   \/**< Software Control Register 3, offset: 0x48 *\/$/;"	m	struct:SIM_MemMap
SCR4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR4;                                   \/**< Software Control Register 4, offset: 0x49 *\/$/;"	m	struct:SIM_MemMap
SCR5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR5;                                   \/**< Software Control Register, offset: 0x4A *\/$/;"	m	struct:SIM_MemMap
SCR6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR6;                                   \/**< Software Control Register 5, offset: 0x4B *\/$/;"	m	struct:SIM_MemMap
SCR7	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCR7;                                   \/**< Software Control Register 6, offset: 0x4C *\/$/;"	m	struct:SIM_MemMap
SCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t SCTRL;                                  \/**< Timer Channel Status and Control Register, array offset: 0x7, array step: 0x10 *\/$/;"	m	struct:TMR_MemMap::__anon61
SCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCTRL;                                  \/**< ADC Scan Control Register, offset: 0x52 *\/$/;"	m	struct:ADC_MemMap
SCTRL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SCTRL2;                                 \/**< ADC Scan Control Register 2, offset: 0x70 *\/$/;"	m	struct:ADC_MemMap
SD0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SD0;                                    \/**< STOP Disable Register 0, offset: 0x10 *\/$/;"	m	struct:SIM_MemMap
SD1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SD1;                                    \/**< Peripheral Clock STOP Disable Register 1, offset: 0x11 *\/$/;"	m	struct:SIM_MemMap
SD2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SD2;                                    \/**< Peripheral Clock STOP Disable Register 2, offset: 0x12 *\/$/;"	m	struct:SIM_MemMap
SD3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SD3;                                    \/**< Peripheral Clock STOP Disable Register 3, offset: 0x13 *\/$/;"	m	struct:SIM_MemMap
SDALowTimeout	.\Generated_Code\PE_LDD.h	/^  uint32_t SDALowTimeout;              \/* Number of SCL low timeout occur. *\/$/;"	m	struct:__anon25
SDIS	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SDIS;                                   \/**< ADC Sample Disable Register, offset: 0x8 *\/$/;"	m	struct:ADC_MemMap
SDIS2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SDIS2;                                  \/**< ADC Sample Disable Register 2, offset: 0x5A *\/$/;"	m	struct:ADC_MemMap
SEL0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL0;                                   \/**< Crossbar A Select Register 0, offset: 0x0 *\/$/;"	m	struct:XBARA_MemMap
SEL0	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL0;                                   \/**< Crossbar B Select Register 0, offset: 0x0 *\/$/;"	m	struct:XBARB_MemMap
SEL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL1;                                   \/**< Crossbar A Select Register 1, offset: 0x1 *\/$/;"	m	struct:XBARA_MemMap
SEL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL1;                                   \/**< Crossbar B Select Register 1, offset: 0x1 *\/$/;"	m	struct:XBARB_MemMap
SEL10	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL10;                                  \/**< Crossbar A Select Register 10, offset: 0xA *\/$/;"	m	struct:XBARA_MemMap
SEL11	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL11;                                  \/**< Crossbar A Select Register 11, offset: 0xB *\/$/;"	m	struct:XBARA_MemMap
SEL12	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL12;                                  \/**< Crossbar A Select Register 12, offset: 0xC *\/$/;"	m	struct:XBARA_MemMap
SEL13	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL13;                                  \/**< Crossbar A Select Register 13, offset: 0xD *\/$/;"	m	struct:XBARA_MemMap
SEL14	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL14;                                  \/**< Crossbar A Select Register 14, offset: 0xE *\/$/;"	m	struct:XBARA_MemMap
SEL15	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL15;                                  \/**< Crossbar A Select Register 15, offset: 0xF *\/$/;"	m	struct:XBARA_MemMap
SEL16	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL16;                                  \/**< Crossbar A Select Register 16, offset: 0x10 *\/$/;"	m	struct:XBARA_MemMap
SEL17	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL17;                                  \/**< Crossbar A Select Register 17, offset: 0x11 *\/$/;"	m	struct:XBARA_MemMap
SEL18	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL18;                                  \/**< Crossbar A Select Register 18, offset: 0x12 *\/$/;"	m	struct:XBARA_MemMap
SEL19	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL19;                                  \/**< Crossbar A Select Register 19, offset: 0x13 *\/$/;"	m	struct:XBARA_MemMap
SEL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL2;                                   \/**< Crossbar A Select Register 2, offset: 0x2 *\/$/;"	m	struct:XBARA_MemMap
SEL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL2;                                   \/**< Crossbar B Select Register 2, offset: 0x2 *\/$/;"	m	struct:XBARB_MemMap
SEL20	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL20;                                  \/**< Crossbar A Select Register 20, offset: 0x14 *\/$/;"	m	struct:XBARA_MemMap
SEL3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL3;                                   \/**< Crossbar A Select Register 3, offset: 0x3 *\/$/;"	m	struct:XBARA_MemMap
SEL3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL3;                                   \/**< Crossbar B Select Register 3, offset: 0x3 *\/$/;"	m	struct:XBARB_MemMap
SEL4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL4;                                   \/**< Crossbar A Select Register 4, offset: 0x4 *\/$/;"	m	struct:XBARA_MemMap
SEL4	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL4;                                   \/**< Crossbar B Select Register 4, offset: 0x4 *\/$/;"	m	struct:XBARB_MemMap
SEL5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL5;                                   \/**< Crossbar A Select Register 5, offset: 0x5 *\/$/;"	m	struct:XBARA_MemMap
SEL5	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL5;                                   \/**< Crossbar B Select Register 5, offset: 0x5 *\/$/;"	m	struct:XBARB_MemMap
SEL6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL6;                                   \/**< Crossbar A Select Register 6, offset: 0x6 *\/$/;"	m	struct:XBARA_MemMap
SEL6	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL6;                                   \/**< Crossbar B Select Register 6, offset: 0x6 *\/$/;"	m	struct:XBARB_MemMap
SEL7	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL7;                                   \/**< Crossbar A Select Register 7, offset: 0x7 *\/$/;"	m	struct:XBARA_MemMap
SEL7	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL7;                                   \/**< Crossbar B Select Register 7, offset: 0x7 *\/$/;"	m	struct:XBARB_MemMap
SEL8	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL8;                                   \/**< Crossbar A Select Register 8, offset: 0x8 *\/$/;"	m	struct:XBARA_MemMap
SEL9	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SEL9;                                   \/**< Crossbar A Select Register 9, offset: 0x9 *\/$/;"	m	struct:XBARA_MemMap
SERV	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SERV;                                   \/**< Service Register, offset: 0x1 *\/$/;"	m	struct:EWM_MemMap
SIM_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	6266;"	d
SIM_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	6268;"	d
SIM_CLKOUT	.\Static_Code\IO_Map\MC56F82748.h	6287;"	d
SIM_CLKOUT_CLKDIS0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5882;"	d
SIM_CLKOUT_CLKDIS0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5883;"	d
SIM_CLKOUT_CLKDIS1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5887;"	d
SIM_CLKOUT_CLKDIS1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5888;"	d
SIM_CLKOUT_CLKODIV	.\Static_Code\IO_Map\MC56F82748.h	5891;"	d
SIM_CLKOUT_CLKODIV_MASK	.\Static_Code\IO_Map\MC56F82748.h	5889;"	d
SIM_CLKOUT_CLKODIV_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5890;"	d
SIM_CLKOUT_CLKOSEL0	.\Static_Code\IO_Map\MC56F82748.h	5881;"	d
SIM_CLKOUT_CLKOSEL0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5879;"	d
SIM_CLKOUT_CLKOSEL0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5880;"	d
SIM_CLKOUT_CLKOSEL1	.\Static_Code\IO_Map\MC56F82748.h	5886;"	d
SIM_CLKOUT_CLKOSEL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5884;"	d
SIM_CLKOUT_CLKOSEL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5885;"	d
SIM_CLKOUT_REG	.\Static_Code\IO_Map\MC56F82748.h	5784;"	d
SIM_CTRL	.\Static_Code\IO_Map\MC56F82748.h	6282;"	d
SIM_CTRL_DMAEbl	.\Static_Code\IO_Map\MC56F82748.h	5849;"	d
SIM_CTRL_DMAEbl_MASK	.\Static_Code\IO_Map\MC56F82748.h	5847;"	d
SIM_CTRL_DMAEbl_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5848;"	d
SIM_CTRL_OnceEbl_MASK	.\Static_Code\IO_Map\MC56F82748.h	5845;"	d
SIM_CTRL_OnceEbl_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5846;"	d
SIM_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	5779;"	d
SIM_CTRL_RST_FILT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5850;"	d
SIM_CTRL_RST_FILT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5851;"	d
SIM_CTRL_STOP_disable	.\Static_Code\IO_Map\MC56F82748.h	5842;"	d
SIM_CTRL_STOP_disable_MASK	.\Static_Code\IO_Map\MC56F82748.h	5840;"	d
SIM_CTRL_STOP_disable_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5841;"	d
SIM_CTRL_SWRst_MASK	.\Static_Code\IO_Map\MC56F82748.h	5843;"	d
SIM_CTRL_SWRst_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5844;"	d
SIM_CTRL_WAIT_disable	.\Static_Code\IO_Map\MC56F82748.h	5839;"	d
SIM_CTRL_WAIT_disable_MASK	.\Static_Code\IO_Map\MC56F82748.h	5837;"	d
SIM_CTRL_WAIT_disable_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5838;"	d
SIM_GPSAL	.\Static_Code\IO_Map\MC56F82748.h	6300;"	d
SIM_GPSAL_A0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6053;"	d
SIM_GPSAL_A0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6054;"	d
SIM_GPSAL_REG	.\Static_Code\IO_Map\MC56F82748.h	5797;"	d
SIM_GPSBL	.\Static_Code\IO_Map\MC56F82748.h	6301;"	d
SIM_GPSBL_B1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6056;"	d
SIM_GPSBL_B1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6057;"	d
SIM_GPSBL_REG	.\Static_Code\IO_Map\MC56F82748.h	5798;"	d
SIM_GPSCH	.\Static_Code\IO_Map\MC56F82748.h	6303;"	d
SIM_GPSCH_C10	.\Static_Code\IO_Map\MC56F82748.h	6087;"	d
SIM_GPSCH_C10_MASK	.\Static_Code\IO_Map\MC56F82748.h	6085;"	d
SIM_GPSCH_C10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6086;"	d
SIM_GPSCH_C11	.\Static_Code\IO_Map\MC56F82748.h	6090;"	d
SIM_GPSCH_C11_MASK	.\Static_Code\IO_Map\MC56F82748.h	6088;"	d
SIM_GPSCH_C11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6089;"	d
SIM_GPSCH_C12	.\Static_Code\IO_Map\MC56F82748.h	6093;"	d
SIM_GPSCH_C12_MASK	.\Static_Code\IO_Map\MC56F82748.h	6091;"	d
SIM_GPSCH_C12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6092;"	d
SIM_GPSCH_C13	.\Static_Code\IO_Map\MC56F82748.h	6096;"	d
SIM_GPSCH_C13_MASK	.\Static_Code\IO_Map\MC56F82748.h	6094;"	d
SIM_GPSCH_C13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6095;"	d
SIM_GPSCH_C14	.\Static_Code\IO_Map\MC56F82748.h	6099;"	d
SIM_GPSCH_C14_MASK	.\Static_Code\IO_Map\MC56F82748.h	6097;"	d
SIM_GPSCH_C14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6098;"	d
SIM_GPSCH_C15	.\Static_Code\IO_Map\MC56F82748.h	6102;"	d
SIM_GPSCH_C15_MASK	.\Static_Code\IO_Map\MC56F82748.h	6100;"	d
SIM_GPSCH_C15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6101;"	d
SIM_GPSCH_C8	.\Static_Code\IO_Map\MC56F82748.h	6081;"	d
SIM_GPSCH_C8_MASK	.\Static_Code\IO_Map\MC56F82748.h	6079;"	d
SIM_GPSCH_C8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6080;"	d
SIM_GPSCH_C9	.\Static_Code\IO_Map\MC56F82748.h	6084;"	d
SIM_GPSCH_C9_MASK	.\Static_Code\IO_Map\MC56F82748.h	6082;"	d
SIM_GPSCH_C9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6083;"	d
SIM_GPSCH_REG	.\Static_Code\IO_Map\MC56F82748.h	5800;"	d
SIM_GPSCL	.\Static_Code\IO_Map\MC56F82748.h	6302;"	d
SIM_GPSCL_C0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6059;"	d
SIM_GPSCL_C0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6060;"	d
SIM_GPSCL_C2	.\Static_Code\IO_Map\MC56F82748.h	6063;"	d
SIM_GPSCL_C2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6061;"	d
SIM_GPSCL_C2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6062;"	d
SIM_GPSCL_C3	.\Static_Code\IO_Map\MC56F82748.h	6066;"	d
SIM_GPSCL_C3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6064;"	d
SIM_GPSCL_C3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6065;"	d
SIM_GPSCL_C4	.\Static_Code\IO_Map\MC56F82748.h	6069;"	d
SIM_GPSCL_C4_MASK	.\Static_Code\IO_Map\MC56F82748.h	6067;"	d
SIM_GPSCL_C4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6068;"	d
SIM_GPSCL_C5_MASK	.\Static_Code\IO_Map\MC56F82748.h	6070;"	d
SIM_GPSCL_C5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6071;"	d
SIM_GPSCL_C6	.\Static_Code\IO_Map\MC56F82748.h	6074;"	d
SIM_GPSCL_C6_MASK	.\Static_Code\IO_Map\MC56F82748.h	6072;"	d
SIM_GPSCL_C6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6073;"	d
SIM_GPSCL_C7	.\Static_Code\IO_Map\MC56F82748.h	6077;"	d
SIM_GPSCL_C7_MASK	.\Static_Code\IO_Map\MC56F82748.h	6075;"	d
SIM_GPSCL_C7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6076;"	d
SIM_GPSCL_REG	.\Static_Code\IO_Map\MC56F82748.h	5799;"	d
SIM_GPSEL	.\Static_Code\IO_Map\MC56F82748.h	6304;"	d
SIM_GPSEL_E4_MASK	.\Static_Code\IO_Map\MC56F82748.h	6104;"	d
SIM_GPSEL_E4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6105;"	d
SIM_GPSEL_E5_MASK	.\Static_Code\IO_Map\MC56F82748.h	6106;"	d
SIM_GPSEL_E5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6107;"	d
SIM_GPSEL_E6_MASK	.\Static_Code\IO_Map\MC56F82748.h	6108;"	d
SIM_GPSEL_E6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6109;"	d
SIM_GPSEL_E7_MASK	.\Static_Code\IO_Map\MC56F82748.h	6110;"	d
SIM_GPSEL_E7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6111;"	d
SIM_GPSEL_REG	.\Static_Code\IO_Map\MC56F82748.h	5801;"	d
SIM_GPSFH	.\Static_Code\IO_Map\MC56F82748.h	6306;"	d
SIM_GPSFH_F8	.\Static_Code\IO_Map\MC56F82748.h	6140;"	d
SIM_GPSFH_F8_MASK	.\Static_Code\IO_Map\MC56F82748.h	6138;"	d
SIM_GPSFH_F8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6139;"	d
SIM_GPSFH_REG	.\Static_Code\IO_Map\MC56F82748.h	5803;"	d
SIM_GPSFL	.\Static_Code\IO_Map\MC56F82748.h	6305;"	d
SIM_GPSFL_F0	.\Static_Code\IO_Map\MC56F82748.h	6115;"	d
SIM_GPSFL_F0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6113;"	d
SIM_GPSFL_F0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6114;"	d
SIM_GPSFL_F1	.\Static_Code\IO_Map\MC56F82748.h	6118;"	d
SIM_GPSFL_F1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6116;"	d
SIM_GPSFL_F1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6117;"	d
SIM_GPSFL_F2	.\Static_Code\IO_Map\MC56F82748.h	6121;"	d
SIM_GPSFL_F2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6119;"	d
SIM_GPSFL_F2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6120;"	d
SIM_GPSFL_F3	.\Static_Code\IO_Map\MC56F82748.h	6124;"	d
SIM_GPSFL_F3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6122;"	d
SIM_GPSFL_F3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6123;"	d
SIM_GPSFL_F4	.\Static_Code\IO_Map\MC56F82748.h	6127;"	d
SIM_GPSFL_F4_MASK	.\Static_Code\IO_Map\MC56F82748.h	6125;"	d
SIM_GPSFL_F4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6126;"	d
SIM_GPSFL_F5	.\Static_Code\IO_Map\MC56F82748.h	6130;"	d
SIM_GPSFL_F5_MASK	.\Static_Code\IO_Map\MC56F82748.h	6128;"	d
SIM_GPSFL_F5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6129;"	d
SIM_GPSFL_F6	.\Static_Code\IO_Map\MC56F82748.h	6133;"	d
SIM_GPSFL_F6_MASK	.\Static_Code\IO_Map\MC56F82748.h	6131;"	d
SIM_GPSFL_F6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6132;"	d
SIM_GPSFL_F7	.\Static_Code\IO_Map\MC56F82748.h	6136;"	d
SIM_GPSFL_F7_MASK	.\Static_Code\IO_Map\MC56F82748.h	6134;"	d
SIM_GPSFL_F7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6135;"	d
SIM_GPSFL_REG	.\Static_Code\IO_Map\MC56F82748.h	5802;"	d
SIM_IOSAHI	.\Static_Code\IO_Map\MC56F82748.h	6297;"	d
SIM_IOSAHI_ISAL	.\Static_Code\IO_Map\MC56F82748.h	6034;"	d
SIM_IOSAHI_ISAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	6032;"	d
SIM_IOSAHI_ISAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6033;"	d
SIM_IOSAHI_REG	.\Static_Code\IO_Map\MC56F82748.h	5794;"	d
SIM_IOSALO	.\Static_Code\IO_Map\MC56F82748.h	6298;"	d
SIM_IOSALO_ISAL	.\Static_Code\IO_Map\MC56F82748.h	6038;"	d
SIM_IOSALO_ISAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	6036;"	d
SIM_IOSALO_ISAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6037;"	d
SIM_IOSALO_REG	.\Static_Code\IO_Map\MC56F82748.h	5795;"	d
SIM_IPSn	.\Static_Code\IO_Map\MC56F82748.h	6307;"	d
SIM_IPSn_REG	.\Static_Code\IO_Map\MC56F82748.h	5804;"	d
SIM_IPSn_SCI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6142;"	d
SIM_IPSn_SCI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6143;"	d
SIM_IPSn_SCI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6144;"	d
SIM_IPSn_SCI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6145;"	d
SIM_IPSn_TA0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6146;"	d
SIM_IPSn_TA0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6147;"	d
SIM_IPSn_TA1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6148;"	d
SIM_IPSn_TA1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6149;"	d
SIM_IPSn_TA2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6150;"	d
SIM_IPSn_TA2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6151;"	d
SIM_IPSn_TA3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6152;"	d
SIM_IPSn_TA3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6153;"	d
SIM_Init	.\Static_Code\Peripherals\SIM_Init.c	/^void SIM_Init(void) {$/;"	f
SIM_LSHID	.\Static_Code\IO_Map\MC56F82748.h	6285;"	d
SIM_LSHID_REG	.\Static_Code\IO_Map\MC56F82748.h	5782;"	d
SIM_MISC0	.\Static_Code\IO_Map\MC56F82748.h	6308;"	d
SIM_MISC0_ADC_SCTRL_MASK	.\Static_Code\IO_Map\MC56F82748.h	6161;"	d
SIM_MISC0_ADC_SCTRL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6162;"	d
SIM_MISC0_CLKINSEL_MASK	.\Static_Code\IO_Map\MC56F82748.h	6157;"	d
SIM_MISC0_CLKINSEL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6158;"	d
SIM_MISC0_FAST_MODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6159;"	d
SIM_MISC0_FAST_MODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6160;"	d
SIM_MISC0_MODE_STAT_MASK	.\Static_Code\IO_Map\MC56F82748.h	6163;"	d
SIM_MISC0_MODE_STAT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6164;"	d
SIM_MISC0_PIT_MSTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	6155;"	d
SIM_MISC0_PIT_MSTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6156;"	d
SIM_MISC0_REG	.\Static_Code\IO_Map\MC56F82748.h	5805;"	d
SIM_MSHID	.\Static_Code\IO_Map\MC56F82748.h	6284;"	d
SIM_MSHID_REG	.\Static_Code\IO_Map\MC56F82748.h	5781;"	d
SIM_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct SIM_MemMap {$/;"	s
SIM_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *SIM_MemMapPtr;$/;"	t
SIM_NVMOPT2H	.\Static_Code\IO_Map\MC56F82748.h	6314;"	d
SIM_NVMOPT2H_REG	.\Static_Code\IO_Map\MC56F82748.h	5811;"	d
SIM_NVMOPT2H_ROSC_8M_FTRIM	.\Static_Code\IO_Map\MC56F82748.h	6215;"	d
SIM_NVMOPT2H_ROSC_8M_FTRIM_MASK	.\Static_Code\IO_Map\MC56F82748.h	6213;"	d
SIM_NVMOPT2H_ROSC_8M_FTRIM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6214;"	d
SIM_NVMOPT2H_ROSC_8M_TTRIM	.\Static_Code\IO_Map\MC56F82748.h	6218;"	d
SIM_NVMOPT2H_ROSC_8M_TTRIM_MASK	.\Static_Code\IO_Map\MC56F82748.h	6216;"	d
SIM_NVMOPT2H_ROSC_8M_TTRIM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6217;"	d
SIM_NVMOPT2L	.\Static_Code\IO_Map\MC56F82748.h	6315;"	d
SIM_NVMOPT2L_PMC_BGTRIM	.\Static_Code\IO_Map\MC56F82748.h	6225;"	d
SIM_NVMOPT2L_PMC_BGTRIM_MASK	.\Static_Code\IO_Map\MC56F82748.h	6223;"	d
SIM_NVMOPT2L_PMC_BGTRIM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6224;"	d
SIM_NVMOPT2L_REG	.\Static_Code\IO_Map\MC56F82748.h	5812;"	d
SIM_NVMOPT2L_ROSC_200K_FTRIM	.\Static_Code\IO_Map\MC56F82748.h	6222;"	d
SIM_NVMOPT2L_ROSC_200K_FTRIM_MASK	.\Static_Code\IO_Map\MC56F82748.h	6220;"	d
SIM_NVMOPT2L_ROSC_200K_FTRIM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6221;"	d
SIM_PCE0	.\Static_Code\IO_Map\MC56F82748.h	6289;"	d
SIM_PCE0_GPIOA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5914;"	d
SIM_PCE0_GPIOA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5915;"	d
SIM_PCE0_GPIOB_MASK	.\Static_Code\IO_Map\MC56F82748.h	5912;"	d
SIM_PCE0_GPIOB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5913;"	d
SIM_PCE0_GPIOC_MASK	.\Static_Code\IO_Map\MC56F82748.h	5910;"	d
SIM_PCE0_GPIOC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5911;"	d
SIM_PCE0_GPIOD_MASK	.\Static_Code\IO_Map\MC56F82748.h	5908;"	d
SIM_PCE0_GPIOD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5909;"	d
SIM_PCE0_GPIOE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5906;"	d
SIM_PCE0_GPIOE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5907;"	d
SIM_PCE0_GPIOF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5904;"	d
SIM_PCE0_GPIOF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5905;"	d
SIM_PCE0_REG	.\Static_Code\IO_Map\MC56F82748.h	5786;"	d
SIM_PCE0_TA0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5922;"	d
SIM_PCE0_TA0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5923;"	d
SIM_PCE0_TA1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5920;"	d
SIM_PCE0_TA1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5921;"	d
SIM_PCE0_TA2_MASK	.\Static_Code\IO_Map\MC56F82748.h	5918;"	d
SIM_PCE0_TA2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5919;"	d
SIM_PCE0_TA3_MASK	.\Static_Code\IO_Map\MC56F82748.h	5916;"	d
SIM_PCE0_TA3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5917;"	d
SIM_PCE1	.\Static_Code\IO_Map\MC56F82748.h	6290;"	d
SIM_PCE1_DACA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5937;"	d
SIM_PCE1_DACA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5938;"	d
SIM_PCE1_DACB_MASK	.\Static_Code\IO_Map\MC56F82748.h	5939;"	d
SIM_PCE1_DACB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5940;"	d
SIM_PCE1_IIC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5927;"	d
SIM_PCE1_IIC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5928;"	d
SIM_PCE1_MSCAN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5925;"	d
SIM_PCE1_MSCAN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5926;"	d
SIM_PCE1_QSPI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5931;"	d
SIM_PCE1_QSPI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5932;"	d
SIM_PCE1_QSPI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5929;"	d
SIM_PCE1_QSPI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5930;"	d
SIM_PCE1_REG	.\Static_Code\IO_Map\MC56F82748.h	5787;"	d
SIM_PCE1_SCI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5935;"	d
SIM_PCE1_SCI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5936;"	d
SIM_PCE1_SCI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5933;"	d
SIM_PCE1_SCI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5934;"	d
SIM_PCE2	.\Static_Code\IO_Map\MC56F82748.h	6291;"	d
SIM_PCE2_CMPA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5956;"	d
SIM_PCE2_CMPA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5957;"	d
SIM_PCE2_CMPB_MASK	.\Static_Code\IO_Map\MC56F82748.h	5954;"	d
SIM_PCE2_CMPB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5955;"	d
SIM_PCE2_CMPC_MASK	.\Static_Code\IO_Map\MC56F82748.h	5952;"	d
SIM_PCE2_CMPC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5953;"	d
SIM_PCE2_CMPD_MASK	.\Static_Code\IO_Map\MC56F82748.h	5950;"	d
SIM_PCE2_CMPD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5951;"	d
SIM_PCE2_CRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	5946;"	d
SIM_PCE2_CRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5947;"	d
SIM_PCE2_CYCADC_MASK	.\Static_Code\IO_Map\MC56F82748.h	5948;"	d
SIM_PCE2_CYCADC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5949;"	d
SIM_PCE2_PIT0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5944;"	d
SIM_PCE2_PIT0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5945;"	d
SIM_PCE2_PIT1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5942;"	d
SIM_PCE2_PIT1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5943;"	d
SIM_PCE2_REG	.\Static_Code\IO_Map\MC56F82748.h	5788;"	d
SIM_PCE3	.\Static_Code\IO_Map\MC56F82748.h	6292;"	d
SIM_PCE3_PWMACH0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5965;"	d
SIM_PCE3_PWMACH0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5966;"	d
SIM_PCE3_PWMACH1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5963;"	d
SIM_PCE3_PWMACH1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5964;"	d
SIM_PCE3_PWMACH2_MASK	.\Static_Code\IO_Map\MC56F82748.h	5961;"	d
SIM_PCE3_PWMACH2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5962;"	d
SIM_PCE3_PWMACH3_MASK	.\Static_Code\IO_Map\MC56F82748.h	5959;"	d
SIM_PCE3_PWMACH3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5960;"	d
SIM_PCE3_REG	.\Static_Code\IO_Map\MC56F82748.h	5789;"	d
SIM_PCR	.\Static_Code\IO_Map\MC56F82748.h	6288;"	d
SIM_PCR_IIC_FILT_MASK	.\Static_Code\IO_Map\MC56F82748.h	5893;"	d
SIM_PCR_IIC_FILT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5894;"	d
SIM_PCR_PWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	5895;"	d
SIM_PCR_PWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5896;"	d
SIM_PCR_REG	.\Static_Code\IO_Map\MC56F82748.h	5785;"	d
SIM_PCR_SCI0_CR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5901;"	d
SIM_PCR_SCI0_CR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5902;"	d
SIM_PCR_SCI1_CR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5899;"	d
SIM_PCR_SCI1_CR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5900;"	d
SIM_PCR_TMR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5897;"	d
SIM_PCR_TMR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5898;"	d
SIM_PDD_CLOCK_GATE_CMPA_MASK	.\Static_Code\PDD\SIM_PDD.h	111;"	d
SIM_PDD_CLOCK_GATE_CMPA_MASK	.\Static_Code\PDD\SIM_PDD.h	117;"	d
SIM_PDD_CLOCK_GATE_CMPA_MASK	.\Static_Code\PDD\SIM_PDD.h	125;"	d
SIM_PDD_CLOCK_GATE_CMPB_MASK	.\Static_Code\PDD\SIM_PDD.h	112;"	d
SIM_PDD_CLOCK_GATE_CMPB_MASK	.\Static_Code\PDD\SIM_PDD.h	118;"	d
SIM_PDD_CLOCK_GATE_CMPB_MASK	.\Static_Code\PDD\SIM_PDD.h	126;"	d
SIM_PDD_CLOCK_GATE_CMPC_MASK	.\Static_Code\PDD\SIM_PDD.h	119;"	d
SIM_PDD_CLOCK_GATE_CMPC_MASK	.\Static_Code\PDD\SIM_PDD.h	127;"	d
SIM_PDD_CLOCK_GATE_CMPD_MASK	.\Static_Code\PDD\SIM_PDD.h	120;"	d
SIM_PDD_CLOCK_GATE_DACA_MASK	.\Static_Code\PDD\SIM_PDD.h	378;"	d
SIM_PDD_CLOCK_GATE_DACB_MASK	.\Static_Code\PDD\SIM_PDD.h	379;"	d
SIM_PDD_CLOCK_GATE_GPIOA_MASK	.\Static_Code\PDD\SIM_PDD.h	77;"	d
SIM_PDD_CLOCK_GATE_GPIOB_MASK	.\Static_Code\PDD\SIM_PDD.h	78;"	d
SIM_PDD_CLOCK_GATE_GPIOC_MASK	.\Static_Code\PDD\SIM_PDD.h	79;"	d
SIM_PDD_CLOCK_GATE_GPIOD_MASK	.\Static_Code\PDD\SIM_PDD.h	80;"	d
SIM_PDD_CLOCK_GATE_GPIOE_MASK	.\Static_Code\PDD\SIM_PDD.h	81;"	d
SIM_PDD_CLOCK_GATE_GPIOF_MASK	.\Static_Code\PDD\SIM_PDD.h	82;"	d
SIM_PDD_CLOCK_GATE_PIT0_MASK	.\Static_Code\PDD\SIM_PDD.h	132;"	d
SIM_PDD_CLOCK_GATE_PIT1_MASK	.\Static_Code\PDD\SIM_PDD.h	133;"	d
SIM_PDD_CLOCK_GATE_PWMACH0_MASK	.\Static_Code\PDD\SIM_PDD.h	137;"	d
SIM_PDD_CLOCK_GATE_PWMACH1_MASK	.\Static_Code\PDD\SIM_PDD.h	138;"	d
SIM_PDD_CLOCK_GATE_PWMACH2_MASK	.\Static_Code\PDD\SIM_PDD.h	139;"	d
SIM_PDD_CLOCK_GATE_PWMACH3_MASK	.\Static_Code\PDD\SIM_PDD.h	140;"	d
SIM_PDD_CLOCK_GATE_QSCI0_MASK	.\Static_Code\PDD\SIM_PDD.h	87;"	d
SIM_PDD_CLOCK_GATE_QSCI0_MASK	.\Static_Code\PDD\SIM_PDD.h	92;"	d
SIM_PDD_CLOCK_GATE_QSCI1_MASK	.\Static_Code\PDD\SIM_PDD.h	93;"	d
SIM_PDD_CLOCK_GATE_QSPI0_MASK	.\Static_Code\PDD\SIM_PDD.h	105;"	d
SIM_PDD_CLOCK_GATE_QSPI0_MASK	.\Static_Code\PDD\SIM_PDD.h	99;"	d
SIM_PDD_CLOCK_GATE_QSPI1_MASK	.\Static_Code\PDD\SIM_PDD.h	100;"	d
SIM_PDD_CLOCK_GATE_TMRA0_MASK	.\Static_Code\PDD\SIM_PDD.h	70;"	d
SIM_PDD_CLOCK_GATE_TMRA1_MASK	.\Static_Code\PDD\SIM_PDD.h	71;"	d
SIM_PDD_CLOCK_GATE_TMRA2_MASK	.\Static_Code\PDD\SIM_PDD.h	72;"	d
SIM_PDD_CLOCK_GATE_TMRA3_MASK	.\Static_Code\PDD\SIM_PDD.h	73;"	d
SIM_PDD_CLOCK_RATE_2X_BUS_CLK	.\Static_Code\PDD\SIM_PDD.h	411;"	d
SIM_PDD_CLOCK_RATE_BUS_CLK	.\Static_Code\PDD\SIM_PDD.h	410;"	d
SIM_PDD_DIV2_BUS_CLK	.\Static_Code\PDD\SIM_PDD.h	404;"	d
SIM_PDD_DIVIDE_1	.\Static_Code\PDD\SIM_PDD.h	59;"	d
SIM_PDD_DIVIDE_128	.\Static_Code\PDD\SIM_PDD.h	66;"	d
SIM_PDD_DIVIDE_16	.\Static_Code\PDD\SIM_PDD.h	63;"	d
SIM_PDD_DIVIDE_2	.\Static_Code\PDD\SIM_PDD.h	60;"	d
SIM_PDD_DIVIDE_32	.\Static_Code\PDD\SIM_PDD.h	64;"	d
SIM_PDD_DIVIDE_4	.\Static_Code\PDD\SIM_PDD.h	61;"	d
SIM_PDD_DIVIDE_64	.\Static_Code\PDD\SIM_PDD.h	65;"	d
SIM_PDD_DIVIDE_8	.\Static_Code\PDD\SIM_PDD.h	62;"	d
SIM_PDD_DMA_DISABLE	.\Static_Code\PDD\SIM_PDD.h	41;"	d
SIM_PDD_DMA_DISABLE_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	45;"	d
SIM_PDD_DMA_ENABLE_ALL	.\Static_Code\PDD\SIM_PDD.h	44;"	d
SIM_PDD_DMA_ENABLE_ALL_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	48;"	d
SIM_PDD_DMA_ENABLE_RUN	.\Static_Code\PDD\SIM_PDD.h	42;"	d
SIM_PDD_DMA_ENABLE_RUN_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	46;"	d
SIM_PDD_DMA_ENABLE_RUN_WAIT	.\Static_Code\PDD\SIM_PDD.h	43;"	d
SIM_PDD_DMA_ENABLE_RUN_WAIT_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	47;"	d
SIM_PDD_EXTERNAL_RESET_FLAG	.\Static_Code\PDD\SIM_PDD.h	55;"	d
SIM_PDD_EnableAdcScanControlReordering	.\Static_Code\PDD\SIM_PDD.h	6682;"	d
SIM_PDD_EnableClockOutput0	.\Static_Code\PDD\SIM_PDD.h	1125;"	d
SIM_PDD_EnableClockOutput1	.\Static_Code\PDD\SIM_PDD.h	1033;"	d
SIM_PDD_EnableExternalResetPadcellFilter	.\Static_Code\PDD\SIM_PDD.h	442;"	d
SIM_PDD_EnableLowPowerMode	.\Static_Code\PDD\SIM_PDD.h	7495;"	d
SIM_PDD_EnableOnce	.\Static_Code\PDD\SIM_PDD.h	529;"	d
SIM_PDD_EnablePeripheralClockAdc12	.\Static_Code\PDD\SIM_PDD.h	2607;"	d
SIM_PDD_EnablePeripheralClockCmpA	.\Static_Code\PDD\SIM_PDD.h	2523;"	d
SIM_PDD_EnablePeripheralClockCmpB	.\Static_Code\PDD\SIM_PDD.h	2565;"	d
SIM_PDD_EnablePeripheralClockCmpC	.\Static_Code\PDD\SIM_PDD.h	9440;"	d
SIM_PDD_EnablePeripheralClockCmpD	.\Static_Code\PDD\SIM_PDD.h	10123;"	d
SIM_PDD_EnablePeripheralClockCmpMask	.\Static_Code\PDD\SIM_PDD.h	2363;"	d
SIM_PDD_EnablePeripheralClockCrc	.\Static_Code\PDD\SIM_PDD.h	2649;"	d
SIM_PDD_EnablePeripheralClockDacA	.\Static_Code\PDD\SIM_PDD.h	9314;"	d
SIM_PDD_EnablePeripheralClockDacB	.\Static_Code\PDD\SIM_PDD.h	9356;"	d
SIM_PDD_EnablePeripheralClockDacMask	.\Static_Code\PDD\SIM_PDD.h	9242;"	d
SIM_PDD_EnablePeripheralClockGpioA	.\Static_Code\PDD\SIM_PDD.h	1739;"	d
SIM_PDD_EnablePeripheralClockGpioB	.\Static_Code\PDD\SIM_PDD.h	1781;"	d
SIM_PDD_EnablePeripheralClockGpioC	.\Static_Code\PDD\SIM_PDD.h	1823;"	d
SIM_PDD_EnablePeripheralClockGpioD	.\Static_Code\PDD\SIM_PDD.h	1865;"	d
SIM_PDD_EnablePeripheralClockGpioE	.\Static_Code\PDD\SIM_PDD.h	1907;"	d
SIM_PDD_EnablePeripheralClockGpioF	.\Static_Code\PDD\SIM_PDD.h	1949;"	d
SIM_PDD_EnablePeripheralClockGpioMask	.\Static_Code\PDD\SIM_PDD.h	1655;"	d
SIM_PDD_EnablePeripheralClockIic0	.\Static_Code\PDD\SIM_PDD.h	2311;"	d
SIM_PDD_EnablePeripheralClockMscan	.\Static_Code\PDD\SIM_PDD.h	9960;"	d
SIM_PDD_EnablePeripheralClockPit0	.\Static_Code\PDD\SIM_PDD.h	2773;"	d
SIM_PDD_EnablePeripheralClockPit1	.\Static_Code\PDD\SIM_PDD.h	2815;"	d
SIM_PDD_EnablePeripheralClockPitMask	.\Static_Code\PDD\SIM_PDD.h	2701;"	d
SIM_PDD_EnablePeripheralClockPwmA0	.\Static_Code\PDD\SIM_PDD.h	2947;"	d
SIM_PDD_EnablePeripheralClockPwmA1	.\Static_Code\PDD\SIM_PDD.h	2989;"	d
SIM_PDD_EnablePeripheralClockPwmA2	.\Static_Code\PDD\SIM_PDD.h	3031;"	d
SIM_PDD_EnablePeripheralClockPwmA3	.\Static_Code\PDD\SIM_PDD.h	3073;"	d
SIM_PDD_EnablePeripheralClockPwmMask	.\Static_Code\PDD\SIM_PDD.h	2867;"	d
SIM_PDD_EnablePeripheralClockQsci0	.\Static_Code\PDD\SIM_PDD.h	2109;"	d
SIM_PDD_EnablePeripheralClockQsci1	.\Static_Code\PDD\SIM_PDD.h	9398;"	d
SIM_PDD_EnablePeripheralClockQsciMask	.\Static_Code\PDD\SIM_PDD.h	2001;"	d
SIM_PDD_EnablePeripheralClockQspi0	.\Static_Code\PDD\SIM_PDD.h	2269;"	d
SIM_PDD_EnablePeripheralClockQspi1	.\Static_Code\PDD\SIM_PDD.h	10081;"	d
SIM_PDD_EnablePeripheralClockQspiMask	.\Static_Code\PDD\SIM_PDD.h	2161;"	d
SIM_PDD_EnablePeripheralClockTmrA0	.\Static_Code\PDD\SIM_PDD.h	1477;"	d
SIM_PDD_EnablePeripheralClockTmrA1	.\Static_Code\PDD\SIM_PDD.h	1519;"	d
SIM_PDD_EnablePeripheralClockTmrA2	.\Static_Code\PDD\SIM_PDD.h	1561;"	d
SIM_PDD_EnablePeripheralClockTmrA3	.\Static_Code\PDD\SIM_PDD.h	1603;"	d
SIM_PDD_EnablePeripheralClockTmrMask	.\Static_Code\PDD\SIM_PDD.h	1397;"	d
SIM_PDD_EnablePeripheralStopClockAdc12	.\Static_Code\PDD\SIM_PDD.h	4346;"	d
SIM_PDD_EnablePeripheralStopClockCmpA	.\Static_Code\PDD\SIM_PDD.h	4261;"	d
SIM_PDD_EnablePeripheralStopClockCmpB	.\Static_Code\PDD\SIM_PDD.h	4303;"	d
SIM_PDD_EnablePeripheralStopClockCmpC	.\Static_Code\PDD\SIM_PDD.h	9692;"	d
SIM_PDD_EnablePeripheralStopClockCmpD	.\Static_Code\PDD\SIM_PDD.h	10207;"	d
SIM_PDD_EnablePeripheralStopClockCmpMask	.\Static_Code\PDD\SIM_PDD.h	4095;"	d
SIM_PDD_EnablePeripheralStopClockCrc	.\Static_Code\PDD\SIM_PDD.h	4388;"	d
SIM_PDD_EnablePeripheralStopClockDacA	.\Static_Code\PDD\SIM_PDD.h	9566;"	d
SIM_PDD_EnablePeripheralStopClockDacB	.\Static_Code\PDD\SIM_PDD.h	9608;"	d
SIM_PDD_EnablePeripheralStopClockDacMask	.\Static_Code\PDD\SIM_PDD.h	9492;"	d
SIM_PDD_EnablePeripheralStopClockGpioA	.\Static_Code\PDD\SIM_PDD.h	3463;"	d
SIM_PDD_EnablePeripheralStopClockGpioB	.\Static_Code\PDD\SIM_PDD.h	3505;"	d
SIM_PDD_EnablePeripheralStopClockGpioC	.\Static_Code\PDD\SIM_PDD.h	3547;"	d
SIM_PDD_EnablePeripheralStopClockGpioD	.\Static_Code\PDD\SIM_PDD.h	3589;"	d
SIM_PDD_EnablePeripheralStopClockGpioE	.\Static_Code\PDD\SIM_PDD.h	3631;"	d
SIM_PDD_EnablePeripheralStopClockGpioF	.\Static_Code\PDD\SIM_PDD.h	3673;"	d
SIM_PDD_EnablePeripheralStopClockGpioMask	.\Static_Code\PDD\SIM_PDD.h	3377;"	d
SIM_PDD_EnablePeripheralStopClockIic0	.\Static_Code\PDD\SIM_PDD.h	4043;"	d
SIM_PDD_EnablePeripheralStopClockMscan	.\Static_Code\PDD\SIM_PDD.h	10002;"	d
SIM_PDD_EnablePeripheralStopClockPit0	.\Static_Code\PDD\SIM_PDD.h	4514;"	d
SIM_PDD_EnablePeripheralStopClockPit1	.\Static_Code\PDD\SIM_PDD.h	4556;"	d
SIM_PDD_EnablePeripheralStopClockPitMask	.\Static_Code\PDD\SIM_PDD.h	4440;"	d
SIM_PDD_EnablePeripheralStopClockPwmA0	.\Static_Code\PDD\SIM_PDD.h	4691;"	d
SIM_PDD_EnablePeripheralStopClockPwmA1	.\Static_Code\PDD\SIM_PDD.h	4734;"	d
SIM_PDD_EnablePeripheralStopClockPwmA2	.\Static_Code\PDD\SIM_PDD.h	4777;"	d
SIM_PDD_EnablePeripheralStopClockPwmA3	.\Static_Code\PDD\SIM_PDD.h	4820;"	d
SIM_PDD_EnablePeripheralStopClockPwmMask	.\Static_Code\PDD\SIM_PDD.h	4608;"	d
SIM_PDD_EnablePeripheralStopClockQsci0	.\Static_Code\PDD\SIM_PDD.h	3837;"	d
SIM_PDD_EnablePeripheralStopClockQsci1	.\Static_Code\PDD\SIM_PDD.h	9650;"	d
SIM_PDD_EnablePeripheralStopClockQsciMask	.\Static_Code\PDD\SIM_PDD.h	3725;"	d
SIM_PDD_EnablePeripheralStopClockQspi0	.\Static_Code\PDD\SIM_PDD.h	4001;"	d
SIM_PDD_EnablePeripheralStopClockQspi1	.\Static_Code\PDD\SIM_PDD.h	10165;"	d
SIM_PDD_EnablePeripheralStopClockQspiMask	.\Static_Code\PDD\SIM_PDD.h	3889;"	d
SIM_PDD_EnablePeripheralStopClockTmrA0	.\Static_Code\PDD\SIM_PDD.h	3199;"	d
SIM_PDD_EnablePeripheralStopClockTmrA1	.\Static_Code\PDD\SIM_PDD.h	3241;"	d
SIM_PDD_EnablePeripheralStopClockTmrA2	.\Static_Code\PDD\SIM_PDD.h	3283;"	d
SIM_PDD_EnablePeripheralStopClockTmrA3	.\Static_Code\PDD\SIM_PDD.h	3325;"	d
SIM_PDD_EnablePeripheralStopClockTmrMask	.\Static_Code\PDD\SIM_PDD.h	3125;"	d
SIM_PDD_EnableVeryLowPowerMode	.\Static_Code\PDD\SIM_PDD.h	7539;"	d
SIM_PDD_FAST_MODE	.\Static_Code\PDD\SIM_PDD.h	421;"	d
SIM_PDD_GPIOA0_ANA0_CMPA3	.\Static_Code\PDD\SIM_PDD.h	143;"	d
SIM_PDD_GPIOA0_CMPC_O	.\Static_Code\PDD\SIM_PDD.h	144;"	d
SIM_PDD_GPIOA0_CMPD_O	.\Static_Code\PDD\SIM_PDD.h	289;"	d
SIM_PDD_GPIOA0_PWMA_2X	.\Static_Code\PDD\SIM_PDD.h	290;"	d
SIM_PDD_GPIOA0_XB_OUT10	.\Static_Code\PDD\SIM_PDD.h	288;"	d
SIM_PDD_GPIOB1_ANB1_CMPB_IN0	.\Static_Code\PDD\SIM_PDD.h	147;"	d
SIM_PDD_GPIOB1_DACB	.\Static_Code\PDD\SIM_PDD.h	148;"	d
SIM_PDD_GPIOC0_CLKIN	.\Static_Code\PDD\SIM_PDD.h	152;"	d
SIM_PDD_GPIOC0_EXTAL	.\Static_Code\PDD\SIM_PDD.h	151;"	d
SIM_PDD_GPIOC10_MISO0	.\Static_Code\PDD\SIM_PDD.h	202;"	d
SIM_PDD_GPIOC10_MOSI0	.\Static_Code\PDD\SIM_PDD.h	200;"	d
SIM_PDD_GPIOC10_XB_IN5	.\Static_Code\PDD\SIM_PDD.h	201;"	d
SIM_PDD_GPIOC10_XB_OUT9	.\Static_Code\PDD\SIM_PDD.h	203;"	d
SIM_PDD_GPIOC11_CANTX	.\Static_Code\PDD\SIM_PDD.h	206;"	d
SIM_PDD_GPIOC11_SCL0	.\Static_Code\PDD\SIM_PDD.h	207;"	d
SIM_PDD_GPIOC11_TXD1	.\Static_Code\PDD\SIM_PDD.h	208;"	d
SIM_PDD_GPIOC12_CANRX	.\Static_Code\PDD\SIM_PDD.h	211;"	d
SIM_PDD_GPIOC12_RXD1	.\Static_Code\PDD\SIM_PDD.h	213;"	d
SIM_PDD_GPIOC12_SDA0	.\Static_Code\PDD\SIM_PDD.h	212;"	d
SIM_PDD_GPIOC13_EWM_OUT_B	.\Static_Code\PDD\SIM_PDD.h	218;"	d
SIM_PDD_GPIOC13_TA3	.\Static_Code\PDD\SIM_PDD.h	216;"	d
SIM_PDD_GPIOC13_XB_IN6	.\Static_Code\PDD\SIM_PDD.h	217;"	d
SIM_PDD_GPIOC14_PWM_FAULT4	.\Static_Code\PDD\SIM_PDD.h	223;"	d
SIM_PDD_GPIOC14_SDA0	.\Static_Code\PDD\SIM_PDD.h	221;"	d
SIM_PDD_GPIOC14_XB_OUT4	.\Static_Code\PDD\SIM_PDD.h	222;"	d
SIM_PDD_GPIOC15_PWM_FAULT5	.\Static_Code\PDD\SIM_PDD.h	228;"	d
SIM_PDD_GPIOC15_SCL0	.\Static_Code\PDD\SIM_PDD.h	226;"	d
SIM_PDD_GPIOC15_XB_OUT5	.\Static_Code\PDD\SIM_PDD.h	227;"	d
SIM_PDD_GPIOC2_CLKOUT0	.\Static_Code\PDD\SIM_PDD.h	158;"	d
SIM_PDD_GPIOC2_TXD0	.\Static_Code\PDD\SIM_PDD.h	155;"	d
SIM_PDD_GPIOC2_XBOUT_11	.\Static_Code\PDD\SIM_PDD.h	156;"	d
SIM_PDD_GPIOC2_XB_IN2	.\Static_Code\PDD\SIM_PDD.h	157;"	d
SIM_PDD_GPIOC3_CLKIN1	.\Static_Code\PDD\SIM_PDD.h	164;"	d
SIM_PDD_GPIOC3_CMPA_O	.\Static_Code\PDD\SIM_PDD.h	162;"	d
SIM_PDD_GPIOC3_RXD0	.\Static_Code\PDD\SIM_PDD.h	163;"	d
SIM_PDD_GPIOC3_TA0	.\Static_Code\PDD\SIM_PDD.h	161;"	d
SIM_PDD_GPIOC4_CMPB_O	.\Static_Code\PDD\SIM_PDD.h	168;"	d
SIM_PDD_GPIOC4_EWM_OUT_B	.\Static_Code\PDD\SIM_PDD.h	170;"	d
SIM_PDD_GPIOC4_TA1	.\Static_Code\PDD\SIM_PDD.h	167;"	d
SIM_PDD_GPIOC4_XB_IN6	.\Static_Code\PDD\SIM_PDD.h	169;"	d
SIM_PDD_GPIOC5_DACA	.\Static_Code\PDD\SIM_PDD.h	173;"	d
SIM_PDD_GPIOC5_XB_IN7	.\Static_Code\PDD\SIM_PDD.h	174;"	d
SIM_PDD_GPIOC6_CMPREF	.\Static_Code\PDD\SIM_PDD.h	179;"	d
SIM_PDD_GPIOC6_SS0_B	.\Static_Code\PDD\SIM_PDD.h	180;"	d
SIM_PDD_GPIOC6_TA2	.\Static_Code\PDD\SIM_PDD.h	177;"	d
SIM_PDD_GPIOC6_XB_IN3	.\Static_Code\PDD\SIM_PDD.h	178;"	d
SIM_PDD_GPIOC7_SS0_B	.\Static_Code\PDD\SIM_PDD.h	183;"	d
SIM_PDD_GPIOC7_TXD0	.\Static_Code\PDD\SIM_PDD.h	184;"	d
SIM_PDD_GPIOC7_XBIN_8	.\Static_Code\PDD\SIM_PDD.h	185;"	d
SIM_PDD_GPIOC8_MISO0	.\Static_Code\PDD\SIM_PDD.h	188;"	d
SIM_PDD_GPIOC8_RXD0	.\Static_Code\PDD\SIM_PDD.h	189;"	d
SIM_PDD_GPIOC8_XB_IN9	.\Static_Code\PDD\SIM_PDD.h	190;"	d
SIM_PDD_GPIOC8_XB_OUT6	.\Static_Code\PDD\SIM_PDD.h	191;"	d
SIM_PDD_GPIOC9_SCLK0	.\Static_Code\PDD\SIM_PDD.h	194;"	d
SIM_PDD_GPIOC9_TXD0	.\Static_Code\PDD\SIM_PDD.h	196;"	d
SIM_PDD_GPIOC9_XB_IN4	.\Static_Code\PDD\SIM_PDD.h	195;"	d
SIM_PDD_GPIOC9_XB_OUT8	.\Static_Code\PDD\SIM_PDD.h	197;"	d
SIM_PDD_GPIOE4_PWMA_2B	.\Static_Code\PDD\SIM_PDD.h	231;"	d
SIM_PDD_GPIOE4_XB_IN2	.\Static_Code\PDD\SIM_PDD.h	232;"	d
SIM_PDD_GPIOE5_PWMA_2A	.\Static_Code\PDD\SIM_PDD.h	235;"	d
SIM_PDD_GPIOE5_XB_IN3	.\Static_Code\PDD\SIM_PDD.h	236;"	d
SIM_PDD_GPIOE6_PWMA_3B	.\Static_Code\PDD\SIM_PDD.h	239;"	d
SIM_PDD_GPIOE6_XB_IN4	.\Static_Code\PDD\SIM_PDD.h	240;"	d
SIM_PDD_GPIOE7_PWMA_3A	.\Static_Code\PDD\SIM_PDD.h	243;"	d
SIM_PDD_GPIOE7_XB_IN5	.\Static_Code\PDD\SIM_PDD.h	244;"	d
SIM_PDD_GPIOF0_SCLK1	.\Static_Code\PDD\SIM_PDD.h	248;"	d
SIM_PDD_GPIOF0_XB_IN6	.\Static_Code\PDD\SIM_PDD.h	247;"	d
SIM_PDD_GPIOF1_CLKOUT1	.\Static_Code\PDD\SIM_PDD.h	251;"	d
SIM_PDD_GPIOF1_CMPD_O	.\Static_Code\PDD\SIM_PDD.h	253;"	d
SIM_PDD_GPIOF1_XB_IN7	.\Static_Code\PDD\SIM_PDD.h	252;"	d
SIM_PDD_GPIOF2_MISO1	.\Static_Code\PDD\SIM_PDD.h	258;"	d
SIM_PDD_GPIOF2_SCL0	.\Static_Code\PDD\SIM_PDD.h	256;"	d
SIM_PDD_GPIOF2_XB_OUT6	.\Static_Code\PDD\SIM_PDD.h	257;"	d
SIM_PDD_GPIOF3_MOSI1	.\Static_Code\PDD\SIM_PDD.h	263;"	d
SIM_PDD_GPIOF3_SDA0	.\Static_Code\PDD\SIM_PDD.h	261;"	d
SIM_PDD_GPIOF3_XB_OUT7	.\Static_Code\PDD\SIM_PDD.h	262;"	d
SIM_PDD_GPIOF4_PWMA_0X	.\Static_Code\PDD\SIM_PDD.h	268;"	d
SIM_PDD_GPIOF4_PWMA_FAULT6	.\Static_Code\PDD\SIM_PDD.h	269;"	d
SIM_PDD_GPIOF4_TXD1	.\Static_Code\PDD\SIM_PDD.h	266;"	d
SIM_PDD_GPIOF4_XB_OUT8	.\Static_Code\PDD\SIM_PDD.h	267;"	d
SIM_PDD_GPIOF5_PWMA_1x	.\Static_Code\PDD\SIM_PDD.h	274;"	d
SIM_PDD_GPIOF5_PWMA_FAULT7	.\Static_Code\PDD\SIM_PDD.h	275;"	d
SIM_PDD_GPIOF5_RXD1	.\Static_Code\PDD\SIM_PDD.h	272;"	d
SIM_PDD_GPIOF5_XB_OUT9	.\Static_Code\PDD\SIM_PDD.h	273;"	d
SIM_PDD_GPIOF6_PWMA_3X	.\Static_Code\PDD\SIM_PDD.h	278;"	d
SIM_PDD_GPIOF6_XB_IN2	.\Static_Code\PDD\SIM_PDD.h	279;"	d
SIM_PDD_GPIOF7_CMPC_O	.\Static_Code\PDD\SIM_PDD.h	282;"	d
SIM_PDD_GPIOF7_SS1_B	.\Static_Code\PDD\SIM_PDD.h	283;"	d
SIM_PDD_GPIOF7_XB_IN3	.\Static_Code\PDD\SIM_PDD.h	284;"	d
SIM_PDD_GPIOF8_RXD0	.\Static_Code\PDD\SIM_PDD.h	287;"	d
SIM_PDD_Get12VRegulatorStanbyControl	.\Static_Code\PDD\SIM_PDD.h	842;"	d
SIM_PDD_Get27VRegulatorPowerdownControl	.\Static_Code\PDD\SIM_PDD.h	884;"	d
SIM_PDD_Get27VRegulatorStandbyControl	.\Static_Code\PDD\SIM_PDD.h	926;"	d
SIM_PDD_GetAdc12Reset	.\Static_Code\PDD\SIM_PDD.h	7218;"	d
SIM_PDD_GetAdcScanControlReorderingEnabled	.\Static_Code\PDD\SIM_PDD.h	6705;"	d
SIM_PDD_GetClockOutput0Enabled	.\Static_Code\PDD\SIM_PDD.h	1147;"	d
SIM_PDD_GetClockOutput1Enabled	.\Static_Code\PDD\SIM_PDD.h	1055;"	d
SIM_PDD_GetClockOutputDivider	.\Static_Code\PDD\SIM_PDD.h	1011;"	d
SIM_PDD_GetClockOutputSource0	.\Static_Code\PDD\SIM_PDD.h	1193;"	d
SIM_PDD_GetClockOutputSource1	.\Static_Code\PDD\SIM_PDD.h	1101;"	d
SIM_PDD_GetClockRateIicFilter	.\Static_Code\PDD\SIM_PDD.h	1363;"	d
SIM_PDD_GetClockRatePwm	.\Static_Code\PDD\SIM_PDD.h	1320;"	d
SIM_PDD_GetClockRateSci0	.\Static_Code\PDD\SIM_PDD.h	1234;"	d
SIM_PDD_GetClockRateSci1	.\Static_Code\PDD\SIM_PDD.h	9208;"	d
SIM_PDD_GetClockRateTmr	.\Static_Code\PDD\SIM_PDD.h	1277;"	d
SIM_PDD_GetCmpReset	.\Static_Code\PDD\SIM_PDD.h	7181;"	d
SIM_PDD_GetCrcReset	.\Static_Code\PDD\SIM_PDD.h	7255;"	d
SIM_PDD_GetDacAReset	.\Static_Code\PDD\SIM_PDD.h	9796;"	d
SIM_PDD_GetDacBReset	.\Static_Code\PDD\SIM_PDD.h	9833;"	d
SIM_PDD_GetDacResetMask	.\Static_Code\PDD\SIM_PDD.h	9756;"	d
SIM_PDD_GetDmaEnable	.\Static_Code\PDD\SIM_PDD.h	508;"	d
SIM_PDD_GetEwmReset	.\Static_Code\PDD\SIM_PDD.h	7144;"	d
SIM_PDD_GetExternalResetFlag	.\Static_Code\PDD\SIM_PDD.h	746;"	d
SIM_PDD_GetExternalResetPadcellFilterEnabled	.\Static_Code\PDD\SIM_PDD.h	464;"	d
SIM_PDD_GetFastRoscFrequencyTrim	.\Static_Code\PDD\SIM_PDD.h	7602;"	d
SIM_PDD_GetFastRoscTemperatureTrim	.\Static_Code\PDD\SIM_PDD.h	7579;"	d
SIM_PDD_GetGpioInternalPeripheralFunctionSciRxdMask	.\Static_Code\PDD\SIM_PDD.h	6595;"	d
SIM_PDD_GetGpioInternalPeripheralFunctionSciRxdMask	.\Static_Code\PDD\SIM_PDD.h	6612;"	d
SIM_PDD_GetGpioInternalPeripheralSelectProtection	.\Static_Code\PDD\SIM_PDD.h	5151;"	d
SIM_PDD_GetGpioReset	.\Static_Code\PDD\SIM_PDD.h	6864;"	d
SIM_PDD_GetIic0Reset	.\Static_Code\PDD\SIM_PDD.h	7107;"	d
SIM_PDD_GetInternalPeripheralFunctionGpioTmrMask	.\Static_Code\PDD\SIM_PDD.h	6504;"	d
SIM_PDD_GetInternalPeripheralFunctionXbarTmrMask	.\Static_Code\PDD\SIM_PDD.h	6532;"	d
SIM_PDD_GetIoShortAddressLocation	.\Static_Code\PDD\SIM_PDD.h	4965;"	d
SIM_PDD_GetIoShortAddressLocationHigh	.\Static_Code\PDD\SIM_PDD.h	4882;"	d
SIM_PDD_GetIoShortAddressLocationLow	.\Static_Code\PDD\SIM_PDD.h	4920;"	d
SIM_PDD_GetJtagIdHigh	.\Static_Code\PDD\SIM_PDD.h	782;"	d
SIM_PDD_GetJtagIdLow	.\Static_Code\PDD\SIM_PDD.h	800;"	d
SIM_PDD_GetLargeRegulatorStandbyControl	.\Static_Code\PDD\SIM_PDD.h	968;"	d
SIM_PDD_GetLowPowerModeEnabled	.\Static_Code\PDD\SIM_PDD.h	7517;"	d
SIM_PDD_GetLowPowerModeStatus	.\Static_Code\PDD\SIM_PDD.h	7473;"	d
SIM_PDD_GetMasterPit	.\Static_Code\PDD\SIM_PDD.h	6790;"	d
SIM_PDD_GetMscanReset	.\Static_Code\PDD\SIM_PDD.h	10059;"	d
SIM_PDD_GetOccsClockInput	.\Static_Code\PDD\SIM_PDD.h	6748;"	d
SIM_PDD_GetOnceEnabled	.\Static_Code\PDD\SIM_PDD.h	551;"	d
SIM_PDD_GetPeripheralClockAdc12Enabled	.\Static_Code\PDD\SIM_PDD.h	2627;"	d
SIM_PDD_GetPeripheralClockCmpAEnabled	.\Static_Code\PDD\SIM_PDD.h	2543;"	d
SIM_PDD_GetPeripheralClockCmpBEnabled	.\Static_Code\PDD\SIM_PDD.h	2585;"	d
SIM_PDD_GetPeripheralClockCmpCEnabled	.\Static_Code\PDD\SIM_PDD.h	9460;"	d
SIM_PDD_GetPeripheralClockCmpDEnabled	.\Static_Code\PDD\SIM_PDD.h	10143;"	d
SIM_PDD_GetPeripheralClockCmpDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2455;"	d
SIM_PDD_GetPeripheralClockCmpDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2474;"	d
SIM_PDD_GetPeripheralClockCmpDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2497;"	d
SIM_PDD_GetPeripheralClockCmpEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2388;"	d
SIM_PDD_GetPeripheralClockCmpEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2407;"	d
SIM_PDD_GetPeripheralClockCmpEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2430;"	d
SIM_PDD_GetPeripheralClockCrcEnabled	.\Static_Code\PDD\SIM_PDD.h	2669;"	d
SIM_PDD_GetPeripheralClockDacAEnabled	.\Static_Code\PDD\SIM_PDD.h	9334;"	d
SIM_PDD_GetPeripheralClockDacBEnabled	.\Static_Code\PDD\SIM_PDD.h	9376;"	d
SIM_PDD_GetPeripheralClockDacDisabledMask	.\Static_Code\PDD\SIM_PDD.h	9289;"	d
SIM_PDD_GetPeripheralClockDacEnabledMask	.\Static_Code\PDD\SIM_PDD.h	9266;"	d
SIM_PDD_GetPeripheralClockEnableProtection	.\Static_Code\PDD\SIM_PDD.h	5104;"	d
SIM_PDD_GetPeripheralClockGpioAEnabled	.\Static_Code\PDD\SIM_PDD.h	1759;"	d
SIM_PDD_GetPeripheralClockGpioBEnabled	.\Static_Code\PDD\SIM_PDD.h	1801;"	d
SIM_PDD_GetPeripheralClockGpioCEnabled	.\Static_Code\PDD\SIM_PDD.h	1843;"	d
SIM_PDD_GetPeripheralClockGpioDEnabled	.\Static_Code\PDD\SIM_PDD.h	1885;"	d
SIM_PDD_GetPeripheralClockGpioDisabledMask	.\Static_Code\PDD\SIM_PDD.h	1708;"	d
SIM_PDD_GetPeripheralClockGpioEEnabled	.\Static_Code\PDD\SIM_PDD.h	1927;"	d
SIM_PDD_GetPeripheralClockGpioEnabledMask	.\Static_Code\PDD\SIM_PDD.h	1679;"	d
SIM_PDD_GetPeripheralClockGpioFEnabled	.\Static_Code\PDD\SIM_PDD.h	1969;"	d
SIM_PDD_GetPeripheralClockIic0Enabled	.\Static_Code\PDD\SIM_PDD.h	2331;"	d
SIM_PDD_GetPeripheralClockMscanEnabled	.\Static_Code\PDD\SIM_PDD.h	9980;"	d
SIM_PDD_GetPeripheralClockPit0Enabled	.\Static_Code\PDD\SIM_PDD.h	2793;"	d
SIM_PDD_GetPeripheralClockPit1Enabled	.\Static_Code\PDD\SIM_PDD.h	2835;"	d
SIM_PDD_GetPeripheralClockPitDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2748;"	d
SIM_PDD_GetPeripheralClockPitEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2725;"	d
SIM_PDD_GetPeripheralClockPwmA0Enabled	.\Static_Code\PDD\SIM_PDD.h	2967;"	d
SIM_PDD_GetPeripheralClockPwmA1Enabled	.\Static_Code\PDD\SIM_PDD.h	3009;"	d
SIM_PDD_GetPeripheralClockPwmA2Enabled	.\Static_Code\PDD\SIM_PDD.h	3051;"	d
SIM_PDD_GetPeripheralClockPwmA3Enabled	.\Static_Code\PDD\SIM_PDD.h	3093;"	d
SIM_PDD_GetPeripheralClockPwmDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2918;"	d
SIM_PDD_GetPeripheralClockPwmEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2891;"	d
SIM_PDD_GetPeripheralClockQsci0Enabled	.\Static_Code\PDD\SIM_PDD.h	2129;"	d
SIM_PDD_GetPeripheralClockQsci1Enabled	.\Static_Code\PDD\SIM_PDD.h	9418;"	d
SIM_PDD_GetPeripheralClockQsciDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2067;"	d
SIM_PDD_GetPeripheralClockQsciDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2083;"	d
SIM_PDD_GetPeripheralClockQsciEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2026;"	d
SIM_PDD_GetPeripheralClockQsciEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2042;"	d
SIM_PDD_GetPeripheralClockQspi0Enabled	.\Static_Code\PDD\SIM_PDD.h	2289;"	d
SIM_PDD_GetPeripheralClockQspi1Enabled	.\Static_Code\PDD\SIM_PDD.h	10101;"	d
SIM_PDD_GetPeripheralClockQspiDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2227;"	d
SIM_PDD_GetPeripheralClockQspiDisabledMask	.\Static_Code\PDD\SIM_PDD.h	2246;"	d
SIM_PDD_GetPeripheralClockQspiEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2186;"	d
SIM_PDD_GetPeripheralClockQspiEnabledMask	.\Static_Code\PDD\SIM_PDD.h	2205;"	d
SIM_PDD_GetPeripheralClockTmrA0Enabled	.\Static_Code\PDD\SIM_PDD.h	1497;"	d
SIM_PDD_GetPeripheralClockTmrA1Enabled	.\Static_Code\PDD\SIM_PDD.h	1539;"	d
SIM_PDD_GetPeripheralClockTmrA2Enabled	.\Static_Code\PDD\SIM_PDD.h	1581;"	d
SIM_PDD_GetPeripheralClockTmrA3Enabled	.\Static_Code\PDD\SIM_PDD.h	1623;"	d
SIM_PDD_GetPeripheralClockTmrDisabledMask	.\Static_Code\PDD\SIM_PDD.h	1448;"	d
SIM_PDD_GetPeripheralClockTmrEnabledMask	.\Static_Code\PDD\SIM_PDD.h	1421;"	d
SIM_PDD_GetPeripheralFunctionGpioA0	.\Static_Code\PDD\SIM_PDD.h	5195;"	d
SIM_PDD_GetPeripheralFunctionGpioB1	.\Static_Code\PDD\SIM_PDD.h	5239;"	d
SIM_PDD_GetPeripheralFunctionGpioC0	.\Static_Code\PDD\SIM_PDD.h	5282;"	d
SIM_PDD_GetPeripheralFunctionGpioC10	.\Static_Code\PDD\SIM_PDD.h	5670;"	d
SIM_PDD_GetPeripheralFunctionGpioC11	.\Static_Code\PDD\SIM_PDD.h	5714;"	d
SIM_PDD_GetPeripheralFunctionGpioC12	.\Static_Code\PDD\SIM_PDD.h	5758;"	d
SIM_PDD_GetPeripheralFunctionGpioC13	.\Static_Code\PDD\SIM_PDD.h	5802;"	d
SIM_PDD_GetPeripheralFunctionGpioC14	.\Static_Code\PDD\SIM_PDD.h	5846;"	d
SIM_PDD_GetPeripheralFunctionGpioC15	.\Static_Code\PDD\SIM_PDD.h	5890;"	d
SIM_PDD_GetPeripheralFunctionGpioC2	.\Static_Code\PDD\SIM_PDD.h	5325;"	d
SIM_PDD_GetPeripheralFunctionGpioC3	.\Static_Code\PDD\SIM_PDD.h	5368;"	d
SIM_PDD_GetPeripheralFunctionGpioC4	.\Static_Code\PDD\SIM_PDD.h	5411;"	d
SIM_PDD_GetPeripheralFunctionGpioC5	.\Static_Code\PDD\SIM_PDD.h	5454;"	d
SIM_PDD_GetPeripheralFunctionGpioC6	.\Static_Code\PDD\SIM_PDD.h	5497;"	d
SIM_PDD_GetPeripheralFunctionGpioC7	.\Static_Code\PDD\SIM_PDD.h	5540;"	d
SIM_PDD_GetPeripheralFunctionGpioC8	.\Static_Code\PDD\SIM_PDD.h	5583;"	d
SIM_PDD_GetPeripheralFunctionGpioC9	.\Static_Code\PDD\SIM_PDD.h	5626;"	d
SIM_PDD_GetPeripheralFunctionGpioE4	.\Static_Code\PDD\SIM_PDD.h	5933;"	d
SIM_PDD_GetPeripheralFunctionGpioE5	.\Static_Code\PDD\SIM_PDD.h	5976;"	d
SIM_PDD_GetPeripheralFunctionGpioE6	.\Static_Code\PDD\SIM_PDD.h	6019;"	d
SIM_PDD_GetPeripheralFunctionGpioE7	.\Static_Code\PDD\SIM_PDD.h	6062;"	d
SIM_PDD_GetPeripheralFunctionGpioF0	.\Static_Code\PDD\SIM_PDD.h	6105;"	d
SIM_PDD_GetPeripheralFunctionGpioF1	.\Static_Code\PDD\SIM_PDD.h	6148;"	d
SIM_PDD_GetPeripheralFunctionGpioF2	.\Static_Code\PDD\SIM_PDD.h	6191;"	d
SIM_PDD_GetPeripheralFunctionGpioF3	.\Static_Code\PDD\SIM_PDD.h	6234;"	d
SIM_PDD_GetPeripheralFunctionGpioF4	.\Static_Code\PDD\SIM_PDD.h	6277;"	d
SIM_PDD_GetPeripheralFunctionGpioF5	.\Static_Code\PDD\SIM_PDD.h	6320;"	d
SIM_PDD_GetPeripheralFunctionGpioF6	.\Static_Code\PDD\SIM_PDD.h	6363;"	d
SIM_PDD_GetPeripheralFunctionGpioF7	.\Static_Code\PDD\SIM_PDD.h	6406;"	d
SIM_PDD_GetPeripheralFunctionGpioF8	.\Static_Code\PDD\SIM_PDD.h	6449;"	d
SIM_PDD_GetPeripheralStopClockAdc12Enabled	.\Static_Code\PDD\SIM_PDD.h	4366;"	d
SIM_PDD_GetPeripheralStopClockCmpAEnabled	.\Static_Code\PDD\SIM_PDD.h	4281;"	d
SIM_PDD_GetPeripheralStopClockCmpBEnabled	.\Static_Code\PDD\SIM_PDD.h	4323;"	d
SIM_PDD_GetPeripheralStopClockCmpCEnabled	.\Static_Code\PDD\SIM_PDD.h	9712;"	d
SIM_PDD_GetPeripheralStopClockCmpDEnabled	.\Static_Code\PDD\SIM_PDD.h	10227;"	d
SIM_PDD_GetPeripheralStopClockCmpDisabledMask	.\Static_Code\PDD\SIM_PDD.h	4191;"	d
SIM_PDD_GetPeripheralStopClockCmpDisabledMask	.\Static_Code\PDD\SIM_PDD.h	4211;"	d
SIM_PDD_GetPeripheralStopClockCmpDisabledMask	.\Static_Code\PDD\SIM_PDD.h	4235;"	d
SIM_PDD_GetPeripheralStopClockCmpEnabledMask	.\Static_Code\PDD\SIM_PDD.h	4121;"	d
SIM_PDD_GetPeripheralStopClockCmpEnabledMask	.\Static_Code\PDD\SIM_PDD.h	4141;"	d
SIM_PDD_GetPeripheralStopClockCmpEnabledMask	.\Static_Code\PDD\SIM_PDD.h	4165;"	d
SIM_PDD_GetPeripheralStopClockCrcEnabled	.\Static_Code\PDD\SIM_PDD.h	4408;"	d
SIM_PDD_GetPeripheralStopClockDacAEnabled	.\Static_Code\PDD\SIM_PDD.h	9586;"	d
SIM_PDD_GetPeripheralStopClockDacBEnabled	.\Static_Code\PDD\SIM_PDD.h	9628;"	d
SIM_PDD_GetPeripheralStopClockDacDisabledMask	.\Static_Code\PDD\SIM_PDD.h	9541;"	d
SIM_PDD_GetPeripheralStopClockDacEnabledMask	.\Static_Code\PDD\SIM_PDD.h	9517;"	d
SIM_PDD_GetPeripheralStopClockGpioAEnabled	.\Static_Code\PDD\SIM_PDD.h	3483;"	d
SIM_PDD_GetPeripheralStopClockGpioBEnabled	.\Static_Code\PDD\SIM_PDD.h	3525;"	d
SIM_PDD_GetPeripheralStopClockGpioCEnabled	.\Static_Code\PDD\SIM_PDD.h	3567;"	d
SIM_PDD_GetPeripheralStopClockGpioDEnabled	.\Static_Code\PDD\SIM_PDD.h	3609;"	d
SIM_PDD_GetPeripheralStopClockGpioDisabledMask	.\Static_Code\PDD\SIM_PDD.h	3432;"	d
SIM_PDD_GetPeripheralStopClockGpioEEnabled	.\Static_Code\PDD\SIM_PDD.h	3651;"	d
SIM_PDD_GetPeripheralStopClockGpioEnabledMask	.\Static_Code\PDD\SIM_PDD.h	3402;"	d
SIM_PDD_GetPeripheralStopClockGpioFEnabled	.\Static_Code\PDD\SIM_PDD.h	3693;"	d
SIM_PDD_GetPeripheralStopClockIic0Enabled	.\Static_Code\PDD\SIM_PDD.h	4063;"	d
SIM_PDD_GetPeripheralStopClockMscanEnabled	.\Static_Code\PDD\SIM_PDD.h	10022;"	d
SIM_PDD_GetPeripheralStopClockPit0Enabled	.\Static_Code\PDD\SIM_PDD.h	4534;"	d
SIM_PDD_GetPeripheralStopClockPit1Enabled	.\Static_Code\PDD\SIM_PDD.h	4576;"	d
SIM_PDD_GetPeripheralStopClockPitDisabledMask	.\Static_Code\PDD\SIM_PDD.h	4489;"	d
SIM_PDD_GetPeripheralStopClockPitEnabledMask	.\Static_Code\PDD\SIM_PDD.h	4465;"	d
SIM_PDD_GetPeripheralStopClockPwmA0Enabled	.\Static_Code\PDD\SIM_PDD.h	4711;"	d
SIM_PDD_GetPeripheralStopClockPwmA1Enabled	.\Static_Code\PDD\SIM_PDD.h	4754;"	d
SIM_PDD_GetPeripheralStopClockPwmA2Enabled	.\Static_Code\PDD\SIM_PDD.h	4797;"	d
SIM_PDD_GetPeripheralStopClockPwmA3Enabled	.\Static_Code\PDD\SIM_PDD.h	4840;"	d
SIM_PDD_GetPeripheralStopClockPwmDisabledMask	.\Static_Code\PDD\SIM_PDD.h	4661;"	d
SIM_PDD_GetPeripheralStopClockPwmEnabledMask	.\Static_Code\PDD\SIM_PDD.h	4633;"	d
SIM_PDD_GetPeripheralStopClockQsci0Enabled	.\Static_Code\PDD\SIM_PDD.h	3857;"	d
SIM_PDD_GetPeripheralStopClockQsci1Enabled	.\Static_Code\PDD\SIM_PDD.h	9670;"	d
SIM_PDD_GetPeripheralStopClockQsciDisabledMask	.\Static_Code\PDD\SIM_PDD.h	3794;"	d
SIM_PDD_GetPeripheralStopClockQsciDisabledMask	.\Static_Code\PDD\SIM_PDD.h	3811;"	d
SIM_PDD_GetPeripheralStopClockQsciEnabledMask	.\Static_Code\PDD\SIM_PDD.h	3751;"	d
SIM_PDD_GetPeripheralStopClockQsciEnabledMask	.\Static_Code\PDD\SIM_PDD.h	3768;"	d
SIM_PDD_GetPeripheralStopClockQspi0Enabled	.\Static_Code\PDD\SIM_PDD.h	4021;"	d
SIM_PDD_GetPeripheralStopClockQspi1Enabled	.\Static_Code\PDD\SIM_PDD.h	10185;"	d
SIM_PDD_GetPeripheralStopClockQspiDisabledMask	.\Static_Code\PDD\SIM_PDD.h	3958;"	d
SIM_PDD_GetPeripheralStopClockQspiDisabledMask	.\Static_Code\PDD\SIM_PDD.h	3978;"	d
SIM_PDD_GetPeripheralStopClockQspiEnabledMask	.\Static_Code\PDD\SIM_PDD.h	3915;"	d
SIM_PDD_GetPeripheralStopClockQspiEnabledMask	.\Static_Code\PDD\SIM_PDD.h	3935;"	d
SIM_PDD_GetPeripheralStopClockTmrA0Enabled	.\Static_Code\PDD\SIM_PDD.h	3219;"	d
SIM_PDD_GetPeripheralStopClockTmrA1Enabled	.\Static_Code\PDD\SIM_PDD.h	3261;"	d
SIM_PDD_GetPeripheralStopClockTmrA2Enabled	.\Static_Code\PDD\SIM_PDD.h	3303;"	d
SIM_PDD_GetPeripheralStopClockTmrA3Enabled	.\Static_Code\PDD\SIM_PDD.h	3345;"	d
SIM_PDD_GetPeripheralStopClockTmrDisabledMask	.\Static_Code\PDD\SIM_PDD.h	3174;"	d
SIM_PDD_GetPeripheralStopClockTmrEnabledMask	.\Static_Code\PDD\SIM_PDD.h	3150;"	d
SIM_PDD_GetPit0Reset	.\Static_Code\PDD\SIM_PDD.h	7339;"	d
SIM_PDD_GetPit1Reset	.\Static_Code\PDD\SIM_PDD.h	7376;"	d
SIM_PDD_GetPitResetMask	.\Static_Code\PDD\SIM_PDD.h	7299;"	d
SIM_PDD_GetPortDProtection	.\Static_Code\PDD\SIM_PDD.h	5057;"	d
SIM_PDD_GetPowerControllerBandgapTrim	.\Static_Code\PDD\SIM_PDD.h	7623;"	d
SIM_PDD_GetPowerModeControlProtection	.\Static_Code\PDD\SIM_PDD.h	5012;"	d
SIM_PDD_GetPowerModeStatusMask	.\Static_Code\PDD\SIM_PDD.h	7432;"	d
SIM_PDD_GetPowerOnResetFlag	.\Static_Code\PDD\SIM_PDD.h	764;"	d
SIM_PDD_GetPwmAReset	.\Static_Code\PDD\SIM_PDD.h	7413;"	d
SIM_PDD_GetQsci0Reset	.\Static_Code\PDD\SIM_PDD.h	6967;"	d
SIM_PDD_GetQsci1Reset	.\Static_Code\PDD\SIM_PDD.h	9870;"	d
SIM_PDD_GetQsciResetMask	.\Static_Code\PDD\SIM_PDD.h	6910;"	d
SIM_PDD_GetQsciResetMask	.\Static_Code\PDD\SIM_PDD.h	6926;"	d
SIM_PDD_GetQspi0Reset	.\Static_Code\PDD\SIM_PDD.h	7070;"	d
SIM_PDD_GetQspi1Reset	.\Static_Code\PDD\SIM_PDD.h	10264;"	d
SIM_PDD_GetQspiResetMask	.\Static_Code\PDD\SIM_PDD.h	7013;"	d
SIM_PDD_GetQspiResetMask	.\Static_Code\PDD\SIM_PDD.h	7032;"	d
SIM_PDD_GetResetStatusFlags	.\Static_Code\PDD\SIM_PDD.h	656;"	d
SIM_PDD_GetSlowRoscFrequencyTrim	.\Static_Code\PDD\SIM_PDD.h	7646;"	d
SIM_PDD_GetSoftwareResetFlag	.\Static_Code\PDD\SIM_PDD.h	674;"	d
SIM_PDD_GetSpeedMode	.\Static_Code\PDD\SIM_PDD.h	9934;"	d
SIM_PDD_GetSpeedModeStatus	.\Static_Code\PDD\SIM_PDD.h	9889;"	d
SIM_PDD_GetStopInstructionEnable	.\Static_Code\PDD\SIM_PDD.h	593;"	d
SIM_PDD_GetTmrAReset	.\Static_Code\PDD\SIM_PDD.h	6827;"	d
SIM_PDD_GetVeryLowPowerModeEnabled	.\Static_Code\PDD\SIM_PDD.h	7561;"	d
SIM_PDD_GetVeryLowPowerModeStatus	.\Static_Code\PDD\SIM_PDD.h	7454;"	d
SIM_PDD_GetWaitInstructionEnable	.\Static_Code\PDD\SIM_PDD.h	637;"	d
SIM_PDD_GetWatchdogCpuTimeoutResetFlag	.\Static_Code\PDD\SIM_PDD.h	710;"	d
SIM_PDD_GetWatchdogLossOfReferenceFlag	.\Static_Code\PDD\SIM_PDD.h	728;"	d
SIM_PDD_GetWatchdogWindowTimeoutResetFlag	.\Static_Code\PDD\SIM_PDD.h	692;"	d
SIM_PDD_GetXbarInternalPeripheralFunctionSciRxdMask	.\Static_Code\PDD\SIM_PDD.h	6638;"	d
SIM_PDD_GetXbarInternalPeripheralFunctionSciRxdMask	.\Static_Code\PDD\SIM_PDD.h	6655;"	d
SIM_PDD_H_	.\Static_Code\PDD\SIM_PDD.h	9;"	d
SIM_PDD_INSTRUCTION_DISABLE	.\Static_Code\PDD\SIM_PDD.h	391;"	d
SIM_PDD_INSTRUCTION_DISABLE_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	393;"	d
SIM_PDD_INSTRUCTION_ENABLE	.\Static_Code\PDD\SIM_PDD.h	390;"	d
SIM_PDD_INSTRUCTION_ENABLE_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	392;"	d
SIM_PDD_LOW_POWER_MODE	.\Static_Code\PDD\SIM_PDD.h	373;"	d
SIM_PDD_MASTER_PIT0	.\Static_Code\PDD\SIM_PDD.h	316;"	d
SIM_PDD_MASTER_PIT1	.\Static_Code\PDD\SIM_PDD.h	317;"	d
SIM_PDD_MSTR_2X_CLK	.\Static_Code\PDD\SIM_PDD.h	403;"	d
SIM_PDD_MSTR_OSC	.\Static_Code\PDD\SIM_PDD.h	405;"	d
SIM_PDD_NORMAL_MODE	.\Static_Code\PDD\SIM_PDD.h	420;"	d
SIM_PDD_OCCS_CLKIN0	.\Static_Code\PDD\SIM_PDD.h	312;"	d
SIM_PDD_OCCS_CLKIN1	.\Static_Code\PDD\SIM_PDD.h	313;"	d
SIM_PDD_PERIPHERAL_FUNCTION_SCI0_RXD	.\Static_Code\PDD\SIM_PDD.h	302;"	d
SIM_PDD_PERIPHERAL_FUNCTION_SCI0_RXD	.\Static_Code\PDD\SIM_PDD.h	307;"	d
SIM_PDD_PERIPHERAL_FUNCTION_SCI1_RXD	.\Static_Code\PDD\SIM_PDD.h	308;"	d
SIM_PDD_PERIPHERAL_FUNCTION_TMRA0	.\Static_Code\PDD\SIM_PDD.h	294;"	d
SIM_PDD_PERIPHERAL_FUNCTION_TMRA1	.\Static_Code\PDD\SIM_PDD.h	295;"	d
SIM_PDD_PERIPHERAL_FUNCTION_TMRA2	.\Static_Code\PDD\SIM_PDD.h	296;"	d
SIM_PDD_PERIPHERAL_FUNCTION_TMRA3	.\Static_Code\PDD\SIM_PDD.h	297;"	d
SIM_PDD_POWER_DISABLE	.\Static_Code\PDD\SIM_PDD.h	397;"	d
SIM_PDD_POWER_DISABLE_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	399;"	d
SIM_PDD_POWER_ENABLE	.\Static_Code\PDD\SIM_PDD.h	396;"	d
SIM_PDD_POWER_ENABLE_PROTECTED	.\Static_Code\PDD\SIM_PDD.h	398;"	d
SIM_PDD_POWER_ON_RESET_FLAG	.\Static_Code\PDD\SIM_PDD.h	56;"	d
SIM_PDD_PROTECTION_DISABLE	.\Static_Code\PDD\SIM_PDD.h	414;"	d
SIM_PDD_PROTECTION_DISABLE_LOCKED	.\Static_Code\PDD\SIM_PDD.h	416;"	d
SIM_PDD_PROTECTION_ENABLE	.\Static_Code\PDD\SIM_PDD.h	415;"	d
SIM_PDD_PROTECTION_ENABLE_LOCKED	.\Static_Code\PDD\SIM_PDD.h	417;"	d
SIM_PDD_RESET_ADC12	.\Static_Code\PDD\SIM_PDD.h	359;"	d
SIM_PDD_RESET_CMP	.\Static_Code\PDD\SIM_PDD.h	356;"	d
SIM_PDD_RESET_CRC	.\Static_Code\PDD\SIM_PDD.h	362;"	d
SIM_PDD_RESET_DACA	.\Static_Code\PDD\SIM_PDD.h	383;"	d
SIM_PDD_RESET_DACB	.\Static_Code\PDD\SIM_PDD.h	384;"	d
SIM_PDD_RESET_EWM	.\Static_Code\PDD\SIM_PDD.h	353;"	d
SIM_PDD_RESET_GPIO	.\Static_Code\PDD\SIM_PDD.h	323;"	d
SIM_PDD_RESET_IIC0	.\Static_Code\PDD\SIM_PDD.h	350;"	d
SIM_PDD_RESET_MSCAN	.\Static_Code\PDD\SIM_PDD.h	387;"	d
SIM_PDD_RESET_PIT0	.\Static_Code\PDD\SIM_PDD.h	366;"	d
SIM_PDD_RESET_PIT1	.\Static_Code\PDD\SIM_PDD.h	367;"	d
SIM_PDD_RESET_PWMA	.\Static_Code\PDD\SIM_PDD.h	370;"	d
SIM_PDD_RESET_QSCI0	.\Static_Code\PDD\SIM_PDD.h	328;"	d
SIM_PDD_RESET_QSCI0	.\Static_Code\PDD\SIM_PDD.h	333;"	d
SIM_PDD_RESET_QSCI1	.\Static_Code\PDD\SIM_PDD.h	334;"	d
SIM_PDD_RESET_QSPI0	.\Static_Code\PDD\SIM_PDD.h	340;"	d
SIM_PDD_RESET_QSPI0	.\Static_Code\PDD\SIM_PDD.h	346;"	d
SIM_PDD_RESET_QSPI1	.\Static_Code\PDD\SIM_PDD.h	341;"	d
SIM_PDD_RESET_TMRA	.\Static_Code\PDD\SIM_PDD.h	320;"	d
SIM_PDD_ROSC_200K	.\Static_Code\PDD\SIM_PDD.h	407;"	d
SIM_PDD_ROSC_8M	.\Static_Code\PDD\SIM_PDD.h	406;"	d
SIM_PDD_ReadClockOutputSelectReg	.\Static_Code\PDD\SIM_PDD.h	8121;"	d
SIM_PDD_ReadControlReg	.\Static_Code\PDD\SIM_PDD.h	7991;"	d
SIM_PDD_ReadInternalPeripheralSelectReg	.\Static_Code\PDD\SIM_PDD.h	8885;"	d
SIM_PDD_ReadIoShortAddressLocationHighReg	.\Static_Code\PDD\SIM_PDD.h	8505;"	d
SIM_PDD_ReadIoShortAddressLocationLowReg	.\Static_Code\PDD\SIM_PDD.h	8543;"	d
SIM_PDD_ReadJtagIdHighReg	.\Static_Code\PDD\SIM_PDD.h	8027;"	d
SIM_PDD_ReadJtagIdLowReg	.\Static_Code\PDD\SIM_PDD.h	8045;"	d
SIM_PDD_ReadMiscellaneous0Reg	.\Static_Code\PDD\SIM_PDD.h	8923;"	d
SIM_PDD_ReadNonVolatileOption2HighReg	.\Static_Code\PDD\SIM_PDD.h	9131;"	d
SIM_PDD_ReadNonVolatileOption2LowReg	.\Static_Code\PDD\SIM_PDD.h	9149;"	d
SIM_PDD_ReadPeripheralClockEnable0Reg	.\Static_Code\PDD\SIM_PDD.h	8197;"	d
SIM_PDD_ReadPeripheralClockEnable1Reg	.\Static_Code\PDD\SIM_PDD.h	8235;"	d
SIM_PDD_ReadPeripheralClockEnable2Reg	.\Static_Code\PDD\SIM_PDD.h	8273;"	d
SIM_PDD_ReadPeripheralClockEnable3Reg	.\Static_Code\PDD\SIM_PDD.h	8311;"	d
SIM_PDD_ReadPeripheralClockRateReg	.\Static_Code\PDD\SIM_PDD.h	8159;"	d
SIM_PDD_ReadPeripheralSelectGpioALowReg	.\Static_Code\PDD\SIM_PDD.h	8619;"	d
SIM_PDD_ReadPeripheralSelectGpioBLowReg	.\Static_Code\PDD\SIM_PDD.h	8657;"	d
SIM_PDD_ReadPeripheralSelectGpioCHighReg	.\Static_Code\PDD\SIM_PDD.h	8733;"	d
SIM_PDD_ReadPeripheralSelectGpioCLowReg	.\Static_Code\PDD\SIM_PDD.h	8695;"	d
SIM_PDD_ReadPeripheralSelectGpioELowReg	.\Static_Code\PDD\SIM_PDD.h	8771;"	d
SIM_PDD_ReadPeripheralSelectGpioFHighReg	.\Static_Code\PDD\SIM_PDD.h	8847;"	d
SIM_PDD_ReadPeripheralSelectGpioFLowReg	.\Static_Code\PDD\SIM_PDD.h	8809;"	d
SIM_PDD_ReadPeripheralSoftwareReset0Reg	.\Static_Code\PDD\SIM_PDD.h	8961;"	d
SIM_PDD_ReadPeripheralSoftwareReset1Reg	.\Static_Code\PDD\SIM_PDD.h	8999;"	d
SIM_PDD_ReadPeripheralSoftwareReset2Reg	.\Static_Code\PDD\SIM_PDD.h	9037;"	d
SIM_PDD_ReadPeripheralSoftwareReset3Reg	.\Static_Code\PDD\SIM_PDD.h	9075;"	d
SIM_PDD_ReadPeripheralStopClockEnable0Reg	.\Static_Code\PDD\SIM_PDD.h	8350;"	d
SIM_PDD_ReadPeripheralStopClockEnable1Reg	.\Static_Code\PDD\SIM_PDD.h	8389;"	d
SIM_PDD_ReadPeripheralStopClockEnable2Reg	.\Static_Code\PDD\SIM_PDD.h	8428;"	d
SIM_PDD_ReadPeripheralStopClockEnable3Reg	.\Static_Code\PDD\SIM_PDD.h	8467;"	d
SIM_PDD_ReadPowerControlReg	.\Static_Code\PDD\SIM_PDD.h	8083;"	d
SIM_PDD_ReadPowerModeReg	.\Static_Code\PDD\SIM_PDD.h	9113;"	d
SIM_PDD_ReadProtectionReg	.\Static_Code\PDD\SIM_PDD.h	8581;"	d
SIM_PDD_ReadResetStatusReg	.\Static_Code\PDD\SIM_PDD.h	8009;"	d
SIM_PDD_ReadSoftwareControl0Reg	.\Static_Code\PDD\SIM_PDD.h	7687;"	d
SIM_PDD_ReadSoftwareControl1Reg	.\Static_Code\PDD\SIM_PDD.h	7725;"	d
SIM_PDD_ReadSoftwareControl2Reg	.\Static_Code\PDD\SIM_PDD.h	7763;"	d
SIM_PDD_ReadSoftwareControl3Reg	.\Static_Code\PDD\SIM_PDD.h	7801;"	d
SIM_PDD_ReadSoftwareControl4Reg	.\Static_Code\PDD\SIM_PDD.h	7839;"	d
SIM_PDD_ReadSoftwareControl5Reg	.\Static_Code\PDD\SIM_PDD.h	7877;"	d
SIM_PDD_ReadSoftwareControl6Reg	.\Static_Code\PDD\SIM_PDD.h	7915;"	d
SIM_PDD_ReadSoftwareControl7Reg	.\Static_Code\PDD\SIM_PDD.h	7953;"	d
SIM_PDD_ResetAdc12	.\Static_Code\PDD\SIM_PDD.h	7199;"	d
SIM_PDD_ResetCmp	.\Static_Code\PDD\SIM_PDD.h	7162;"	d
SIM_PDD_ResetCrc	.\Static_Code\PDD\SIM_PDD.h	7236;"	d
SIM_PDD_ResetDacA	.\Static_Code\PDD\SIM_PDD.h	9777;"	d
SIM_PDD_ResetDacB	.\Static_Code\PDD\SIM_PDD.h	9814;"	d
SIM_PDD_ResetDacMask	.\Static_Code\PDD\SIM_PDD.h	9736;"	d
SIM_PDD_ResetEwm	.\Static_Code\PDD\SIM_PDD.h	7125;"	d
SIM_PDD_ResetGpio	.\Static_Code\PDD\SIM_PDD.h	6845;"	d
SIM_PDD_ResetIic0	.\Static_Code\PDD\SIM_PDD.h	7088;"	d
SIM_PDD_ResetMscan	.\Static_Code\PDD\SIM_PDD.h	10040;"	d
SIM_PDD_ResetPit0	.\Static_Code\PDD\SIM_PDD.h	7320;"	d
SIM_PDD_ResetPit1	.\Static_Code\PDD\SIM_PDD.h	7357;"	d
SIM_PDD_ResetPitMask	.\Static_Code\PDD\SIM_PDD.h	7279;"	d
SIM_PDD_ResetPwmA	.\Static_Code\PDD\SIM_PDD.h	7394;"	d
SIM_PDD_ResetQsci0	.\Static_Code\PDD\SIM_PDD.h	6948;"	d
SIM_PDD_ResetQsci1	.\Static_Code\PDD\SIM_PDD.h	9851;"	d
SIM_PDD_ResetQsciMask	.\Static_Code\PDD\SIM_PDD.h	6889;"	d
SIM_PDD_ResetQspi0	.\Static_Code\PDD\SIM_PDD.h	7051;"	d
SIM_PDD_ResetQspi1	.\Static_Code\PDD\SIM_PDD.h	10245;"	d
SIM_PDD_ResetQspiMask	.\Static_Code\PDD\SIM_PDD.h	6992;"	d
SIM_PDD_ResetTmrA	.\Static_Code\PDD\SIM_PDD.h	6808;"	d
SIM_PDD_SW_RESET_FLAG	.\Static_Code\PDD\SIM_PDD.h	51;"	d
SIM_PDD_SYS_CLK	.\Static_Code\PDD\SIM_PDD.h	402;"	d
SIM_PDD_Set12VRegulatorStanbyControl	.\Static_Code\PDD\SIM_PDD.h	820;"	d
SIM_PDD_Set27VRegulatorPowerdownControl	.\Static_Code\PDD\SIM_PDD.h	862;"	d
SIM_PDD_Set27VRegulatorStandbyControl	.\Static_Code\PDD\SIM_PDD.h	904;"	d
SIM_PDD_SetClockOutputDivider	.\Static_Code\PDD\SIM_PDD.h	988;"	d
SIM_PDD_SetClockOutputSource0	.\Static_Code\PDD\SIM_PDD.h	1171;"	d
SIM_PDD_SetClockOutputSource1	.\Static_Code\PDD\SIM_PDD.h	1079;"	d
SIM_PDD_SetClockRateIicFilter	.\Static_Code\PDD\SIM_PDD.h	1342;"	d
SIM_PDD_SetClockRatePwm	.\Static_Code\PDD\SIM_PDD.h	1299;"	d
SIM_PDD_SetClockRateSci0	.\Static_Code\PDD\SIM_PDD.h	1213;"	d
SIM_PDD_SetClockRateSci1	.\Static_Code\PDD\SIM_PDD.h	9187;"	d
SIM_PDD_SetClockRateTmr	.\Static_Code\PDD\SIM_PDD.h	1256;"	d
SIM_PDD_SetDmaEnable	.\Static_Code\PDD\SIM_PDD.h	484;"	d
SIM_PDD_SetGpioInternalPeripheralSelectProtection	.\Static_Code\PDD\SIM_PDD.h	5128;"	d
SIM_PDD_SetInternalPeripheralFunctionSciMask	.\Static_Code\PDD\SIM_PDD.h	6569;"	d
SIM_PDD_SetInternalPeripheralFunctionTmrMask	.\Static_Code\PDD\SIM_PDD.h	6479;"	d
SIM_PDD_SetIoShortAddressLocation	.\Static_Code\PDD\SIM_PDD.h	4941;"	d
SIM_PDD_SetIoShortAddressLocationHigh	.\Static_Code\PDD\SIM_PDD.h	4860;"	d
SIM_PDD_SetIoShortAddressLocationLow	.\Static_Code\PDD\SIM_PDD.h	4902;"	d
SIM_PDD_SetLargeRegulatorStandbyControl	.\Static_Code\PDD\SIM_PDD.h	946;"	d
SIM_PDD_SetMasterPit	.\Static_Code\PDD\SIM_PDD.h	6768;"	d
SIM_PDD_SetOccsClockInput	.\Static_Code\PDD\SIM_PDD.h	6725;"	d
SIM_PDD_SetPeripheralClockEnableProtection	.\Static_Code\PDD\SIM_PDD.h	5082;"	d
SIM_PDD_SetPeripheralFunctionGpioA0	.\Static_Code\PDD\SIM_PDD.h	5172;"	d
SIM_PDD_SetPeripheralFunctionGpioB1	.\Static_Code\PDD\SIM_PDD.h	5216;"	d
SIM_PDD_SetPeripheralFunctionGpioC0	.\Static_Code\PDD\SIM_PDD.h	5259;"	d
SIM_PDD_SetPeripheralFunctionGpioC10	.\Static_Code\PDD\SIM_PDD.h	5647;"	d
SIM_PDD_SetPeripheralFunctionGpioC11	.\Static_Code\PDD\SIM_PDD.h	5691;"	d
SIM_PDD_SetPeripheralFunctionGpioC12	.\Static_Code\PDD\SIM_PDD.h	5735;"	d
SIM_PDD_SetPeripheralFunctionGpioC13	.\Static_Code\PDD\SIM_PDD.h	5779;"	d
SIM_PDD_SetPeripheralFunctionGpioC14	.\Static_Code\PDD\SIM_PDD.h	5823;"	d
SIM_PDD_SetPeripheralFunctionGpioC15	.\Static_Code\PDD\SIM_PDD.h	5867;"	d
SIM_PDD_SetPeripheralFunctionGpioC2	.\Static_Code\PDD\SIM_PDD.h	5302;"	d
SIM_PDD_SetPeripheralFunctionGpioC3	.\Static_Code\PDD\SIM_PDD.h	5345;"	d
SIM_PDD_SetPeripheralFunctionGpioC4	.\Static_Code\PDD\SIM_PDD.h	5388;"	d
SIM_PDD_SetPeripheralFunctionGpioC5	.\Static_Code\PDD\SIM_PDD.h	5431;"	d
SIM_PDD_SetPeripheralFunctionGpioC6	.\Static_Code\PDD\SIM_PDD.h	5474;"	d
SIM_PDD_SetPeripheralFunctionGpioC7	.\Static_Code\PDD\SIM_PDD.h	5517;"	d
SIM_PDD_SetPeripheralFunctionGpioC8	.\Static_Code\PDD\SIM_PDD.h	5560;"	d
SIM_PDD_SetPeripheralFunctionGpioC9	.\Static_Code\PDD\SIM_PDD.h	5603;"	d
SIM_PDD_SetPeripheralFunctionGpioE4	.\Static_Code\PDD\SIM_PDD.h	5910;"	d
SIM_PDD_SetPeripheralFunctionGpioE5	.\Static_Code\PDD\SIM_PDD.h	5953;"	d
SIM_PDD_SetPeripheralFunctionGpioE6	.\Static_Code\PDD\SIM_PDD.h	5996;"	d
SIM_PDD_SetPeripheralFunctionGpioE7	.\Static_Code\PDD\SIM_PDD.h	6039;"	d
SIM_PDD_SetPeripheralFunctionGpioF0	.\Static_Code\PDD\SIM_PDD.h	6082;"	d
SIM_PDD_SetPeripheralFunctionGpioF1	.\Static_Code\PDD\SIM_PDD.h	6125;"	d
SIM_PDD_SetPeripheralFunctionGpioF2	.\Static_Code\PDD\SIM_PDD.h	6168;"	d
SIM_PDD_SetPeripheralFunctionGpioF3	.\Static_Code\PDD\SIM_PDD.h	6211;"	d
SIM_PDD_SetPeripheralFunctionGpioF4	.\Static_Code\PDD\SIM_PDD.h	6254;"	d
SIM_PDD_SetPeripheralFunctionGpioF5	.\Static_Code\PDD\SIM_PDD.h	6297;"	d
SIM_PDD_SetPeripheralFunctionGpioF6	.\Static_Code\PDD\SIM_PDD.h	6340;"	d
SIM_PDD_SetPeripheralFunctionGpioF7	.\Static_Code\PDD\SIM_PDD.h	6383;"	d
SIM_PDD_SetPeripheralFunctionGpioF8	.\Static_Code\PDD\SIM_PDD.h	6426;"	d
SIM_PDD_SetPortDProtection	.\Static_Code\PDD\SIM_PDD.h	5035;"	d
SIM_PDD_SetPowerModeControlProtection	.\Static_Code\PDD\SIM_PDD.h	4990;"	d
SIM_PDD_SetSpeedMode	.\Static_Code\PDD\SIM_PDD.h	9913;"	d
SIM_PDD_SetStopInstructionEnable	.\Static_Code\PDD\SIM_PDD.h	571;"	d
SIM_PDD_SetWaitInstructionEnable	.\Static_Code\PDD\SIM_PDD.h	615;"	d
SIM_PDD_SoftwareReset	.\Static_Code\PDD\SIM_PDD.h	9167;"	d
SIM_PDD_VERY_LOW_POWER_MODE	.\Static_Code\PDD\SIM_PDD.h	374;"	d
SIM_PDD_WATCHDOG_CPU_RESET_FLAG	.\Static_Code\PDD\SIM_PDD.h	53;"	d
SIM_PDD_WATCHDOG_LOSS_OF_REFERENCE_RESET_FLAG	.\Static_Code\PDD\SIM_PDD.h	54;"	d
SIM_PDD_WATCHDOG_WINDOW_RESET_FLAG	.\Static_Code\PDD\SIM_PDD.h	52;"	d
SIM_PDD_WriteClockOutputSelectReg	.\Static_Code\PDD\SIM_PDD.h	8103;"	d
SIM_PDD_WriteControlReg	.\Static_Code\PDD\SIM_PDD.h	7973;"	d
SIM_PDD_WriteInternalPeripheralSelectReg	.\Static_Code\PDD\SIM_PDD.h	8867;"	d
SIM_PDD_WriteIoShortAddressLocationHighReg	.\Static_Code\PDD\SIM_PDD.h	8487;"	d
SIM_PDD_WriteIoShortAddressLocationLowReg	.\Static_Code\PDD\SIM_PDD.h	8525;"	d
SIM_PDD_WriteMiscellaneous0Reg	.\Static_Code\PDD\SIM_PDD.h	8905;"	d
SIM_PDD_WritePeripheralClockEnable0Reg	.\Static_Code\PDD\SIM_PDD.h	8179;"	d
SIM_PDD_WritePeripheralClockEnable1Reg	.\Static_Code\PDD\SIM_PDD.h	8217;"	d
SIM_PDD_WritePeripheralClockEnable2Reg	.\Static_Code\PDD\SIM_PDD.h	8255;"	d
SIM_PDD_WritePeripheralClockEnable3Reg	.\Static_Code\PDD\SIM_PDD.h	8293;"	d
SIM_PDD_WritePeripheralClockRateReg	.\Static_Code\PDD\SIM_PDD.h	8141;"	d
SIM_PDD_WritePeripheralSelectGpioALowReg	.\Static_Code\PDD\SIM_PDD.h	8601;"	d
SIM_PDD_WritePeripheralSelectGpioBLowReg	.\Static_Code\PDD\SIM_PDD.h	8639;"	d
SIM_PDD_WritePeripheralSelectGpioCHighReg	.\Static_Code\PDD\SIM_PDD.h	8715;"	d
SIM_PDD_WritePeripheralSelectGpioCLowReg	.\Static_Code\PDD\SIM_PDD.h	8677;"	d
SIM_PDD_WritePeripheralSelectGpioELowReg	.\Static_Code\PDD\SIM_PDD.h	8753;"	d
SIM_PDD_WritePeripheralSelectGpioFHighReg	.\Static_Code\PDD\SIM_PDD.h	8829;"	d
SIM_PDD_WritePeripheralSelectGpioFLowReg	.\Static_Code\PDD\SIM_PDD.h	8791;"	d
SIM_PDD_WritePeripheralSoftwareReset0Reg	.\Static_Code\PDD\SIM_PDD.h	8943;"	d
SIM_PDD_WritePeripheralSoftwareReset1Reg	.\Static_Code\PDD\SIM_PDD.h	8981;"	d
SIM_PDD_WritePeripheralSoftwareReset2Reg	.\Static_Code\PDD\SIM_PDD.h	9019;"	d
SIM_PDD_WritePeripheralSoftwareReset3Reg	.\Static_Code\PDD\SIM_PDD.h	9057;"	d
SIM_PDD_WritePeripheralStopClockEnable0Reg	.\Static_Code\PDD\SIM_PDD.h	8331;"	d
SIM_PDD_WritePeripheralStopClockEnable1Reg	.\Static_Code\PDD\SIM_PDD.h	8370;"	d
SIM_PDD_WritePeripheralStopClockEnable2Reg	.\Static_Code\PDD\SIM_PDD.h	8409;"	d
SIM_PDD_WritePeripheralStopClockEnable3Reg	.\Static_Code\PDD\SIM_PDD.h	8448;"	d
SIM_PDD_WritePowerControlReg	.\Static_Code\PDD\SIM_PDD.h	8065;"	d
SIM_PDD_WritePowerModeReg	.\Static_Code\PDD\SIM_PDD.h	9095;"	d
SIM_PDD_WriteProtectionReg	.\Static_Code\PDD\SIM_PDD.h	8563;"	d
SIM_PDD_WriteSoftwareControl0Reg	.\Static_Code\PDD\SIM_PDD.h	7669;"	d
SIM_PDD_WriteSoftwareControl1Reg	.\Static_Code\PDD\SIM_PDD.h	7707;"	d
SIM_PDD_WriteSoftwareControl2Reg	.\Static_Code\PDD\SIM_PDD.h	7745;"	d
SIM_PDD_WriteSoftwareControl3Reg	.\Static_Code\PDD\SIM_PDD.h	7783;"	d
SIM_PDD_WriteSoftwareControl4Reg	.\Static_Code\PDD\SIM_PDD.h	7821;"	d
SIM_PDD_WriteSoftwareControl5Reg	.\Static_Code\PDD\SIM_PDD.h	7859;"	d
SIM_PDD_WriteSoftwareControl6Reg	.\Static_Code\PDD\SIM_PDD.h	7897;"	d
SIM_PDD_WriteSoftwareControl7Reg	.\Static_Code\PDD\SIM_PDD.h	7935;"	d
SIM_PROT	.\Static_Code\IO_Map\MC56F82748.h	6299;"	d
SIM_PROT_GDP	.\Static_Code\IO_Map\MC56F82748.h	6048;"	d
SIM_PROT_GDP_MASK	.\Static_Code\IO_Map\MC56F82748.h	6046;"	d
SIM_PROT_GDP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6047;"	d
SIM_PROT_GIPSP	.\Static_Code\IO_Map\MC56F82748.h	6042;"	d
SIM_PROT_GIPSP_MASK	.\Static_Code\IO_Map\MC56F82748.h	6040;"	d
SIM_PROT_GIPSP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6041;"	d
SIM_PROT_PCEP	.\Static_Code\IO_Map\MC56F82748.h	6045;"	d
SIM_PROT_PCEP_MASK	.\Static_Code\IO_Map\MC56F82748.h	6043;"	d
SIM_PROT_PCEP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6044;"	d
SIM_PROT_PMODE	.\Static_Code\IO_Map\MC56F82748.h	6051;"	d
SIM_PROT_PMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6049;"	d
SIM_PROT_PMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6050;"	d
SIM_PROT_REG	.\Static_Code\IO_Map\MC56F82748.h	5796;"	d
SIM_PSWR0	.\Static_Code\IO_Map\MC56F82748.h	6309;"	d
SIM_PSWR0_GPIO_MASK	.\Static_Code\IO_Map\MC56F82748.h	6166;"	d
SIM_PSWR0_GPIO_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6167;"	d
SIM_PSWR0_REG	.\Static_Code\IO_Map\MC56F82748.h	5806;"	d
SIM_PSWR0_TA_MASK	.\Static_Code\IO_Map\MC56F82748.h	6168;"	d
SIM_PSWR0_TA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6169;"	d
SIM_PSWR1	.\Static_Code\IO_Map\MC56F82748.h	6310;"	d
SIM_PSWR1_DACA_MASK	.\Static_Code\IO_Map\MC56F82748.h	6183;"	d
SIM_PSWR1_DACA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6184;"	d
SIM_PSWR1_DACB_MASK	.\Static_Code\IO_Map\MC56F82748.h	6185;"	d
SIM_PSWR1_DACB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6186;"	d
SIM_PSWR1_IIC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6173;"	d
SIM_PSWR1_IIC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6174;"	d
SIM_PSWR1_MSCAN_MASK	.\Static_Code\IO_Map\MC56F82748.h	6171;"	d
SIM_PSWR1_MSCAN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6172;"	d
SIM_PSWR1_QSPI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6177;"	d
SIM_PSWR1_QSPI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6178;"	d
SIM_PSWR1_QSPI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6175;"	d
SIM_PSWR1_QSPI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6176;"	d
SIM_PSWR1_REG	.\Static_Code\IO_Map\MC56F82748.h	5807;"	d
SIM_PSWR1_SCI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6181;"	d
SIM_PSWR1_SCI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6182;"	d
SIM_PSWR1_SCI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6179;"	d
SIM_PSWR1_SCI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6180;"	d
SIM_PSWR2	.\Static_Code\IO_Map\MC56F82748.h	6311;"	d
SIM_PSWR2_CMP_MASK	.\Static_Code\IO_Map\MC56F82748.h	6196;"	d
SIM_PSWR2_CMP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6197;"	d
SIM_PSWR2_CRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	6192;"	d
SIM_PSWR2_CRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6193;"	d
SIM_PSWR2_CYCADC_MASK	.\Static_Code\IO_Map\MC56F82748.h	6194;"	d
SIM_PSWR2_CYCADC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6195;"	d
SIM_PSWR2_EWM_MASK	.\Static_Code\IO_Map\MC56F82748.h	6198;"	d
SIM_PSWR2_EWM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6199;"	d
SIM_PSWR2_PIT0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6190;"	d
SIM_PSWR2_PIT0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6191;"	d
SIM_PSWR2_PIT1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6188;"	d
SIM_PSWR2_PIT1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6189;"	d
SIM_PSWR2_REG	.\Static_Code\IO_Map\MC56F82748.h	5808;"	d
SIM_PSWR3	.\Static_Code\IO_Map\MC56F82748.h	6312;"	d
SIM_PSWR3_PWMA_MASK	.\Static_Code\IO_Map\MC56F82748.h	6201;"	d
SIM_PSWR3_PWMA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6202;"	d
SIM_PSWR3_REG	.\Static_Code\IO_Map\MC56F82748.h	5809;"	d
SIM_PWR	.\Static_Code\IO_Map\MC56F82748.h	6286;"	d
SIM_PWRMODE	.\Static_Code\IO_Map\MC56F82748.h	6313;"	d
SIM_PWRMODE_LPMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6206;"	d
SIM_PWRMODE_LPMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6207;"	d
SIM_PWRMODE_LPMS_MASK	.\Static_Code\IO_Map\MC56F82748.h	6210;"	d
SIM_PWRMODE_LPMS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6211;"	d
SIM_PWRMODE_REG	.\Static_Code\IO_Map\MC56F82748.h	5810;"	d
SIM_PWRMODE_VLPMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6204;"	d
SIM_PWRMODE_VLPMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6205;"	d
SIM_PWRMODE_VLPMS_MASK	.\Static_Code\IO_Map\MC56F82748.h	6208;"	d
SIM_PWRMODE_VLPMS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6209;"	d
SIM_PWR_LRSTDBY	.\Static_Code\IO_Map\MC56F82748.h	5868;"	d
SIM_PWR_LRSTDBY_MASK	.\Static_Code\IO_Map\MC56F82748.h	5866;"	d
SIM_PWR_LRSTDBY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5867;"	d
SIM_PWR_REG	.\Static_Code\IO_Map\MC56F82748.h	5783;"	d
SIM_PWR_SR12STDBY	.\Static_Code\IO_Map\MC56F82748.h	5877;"	d
SIM_PWR_SR12STDBY_MASK	.\Static_Code\IO_Map\MC56F82748.h	5875;"	d
SIM_PWR_SR12STDBY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5876;"	d
SIM_PWR_SR27PDN	.\Static_Code\IO_Map\MC56F82748.h	5874;"	d
SIM_PWR_SR27PDN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5872;"	d
SIM_PWR_SR27PDN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5873;"	d
SIM_PWR_SR27STDBY	.\Static_Code\IO_Map\MC56F82748.h	5871;"	d
SIM_PWR_SR27STDBY_MASK	.\Static_Code\IO_Map\MC56F82748.h	5869;"	d
SIM_PWR_SR27STDBY_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5870;"	d
SIM_RSTAT	.\Static_Code\IO_Map\MC56F82748.h	6283;"	d
SIM_RSTAT_COP_CPU_MASK	.\Static_Code\IO_Map\MC56F82748.h	5859;"	d
SIM_RSTAT_COP_CPU_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5860;"	d
SIM_RSTAT_COP_LOR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5857;"	d
SIM_RSTAT_COP_LOR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5858;"	d
SIM_RSTAT_COP_WNDOW_MASK	.\Static_Code\IO_Map\MC56F82748.h	5861;"	d
SIM_RSTAT_COP_WNDOW_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5862;"	d
SIM_RSTAT_EXTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5855;"	d
SIM_RSTAT_EXTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5856;"	d
SIM_RSTAT_POR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5853;"	d
SIM_RSTAT_POR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5854;"	d
SIM_RSTAT_REG	.\Static_Code\IO_Map\MC56F82748.h	5780;"	d
SIM_RSTAT_SWR_MASK	.\Static_Code\IO_Map\MC56F82748.h	5863;"	d
SIM_RSTAT_SWR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5864;"	d
SIM_SCR0	.\Static_Code\IO_Map\MC56F82748.h	6316;"	d
SIM_SCR0_REG	.\Static_Code\IO_Map\MC56F82748.h	5813;"	d
SIM_SCR0_SCR0	.\Static_Code\IO_Map\MC56F82748.h	6229;"	d
SIM_SCR0_SCR0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6227;"	d
SIM_SCR0_SCR0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6228;"	d
SIM_SCR1	.\Static_Code\IO_Map\MC56F82748.h	6317;"	d
SIM_SCR1_REG	.\Static_Code\IO_Map\MC56F82748.h	5814;"	d
SIM_SCR1_SCR1	.\Static_Code\IO_Map\MC56F82748.h	6233;"	d
SIM_SCR1_SCR1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6231;"	d
SIM_SCR1_SCR1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6232;"	d
SIM_SCR2	.\Static_Code\IO_Map\MC56F82748.h	6318;"	d
SIM_SCR2_REG	.\Static_Code\IO_Map\MC56F82748.h	5815;"	d
SIM_SCR2_SCR2	.\Static_Code\IO_Map\MC56F82748.h	6237;"	d
SIM_SCR2_SCR2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6235;"	d
SIM_SCR2_SCR2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6236;"	d
SIM_SCR3	.\Static_Code\IO_Map\MC56F82748.h	6319;"	d
SIM_SCR3_REG	.\Static_Code\IO_Map\MC56F82748.h	5816;"	d
SIM_SCR3_SCR3	.\Static_Code\IO_Map\MC56F82748.h	6241;"	d
SIM_SCR3_SCR3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6239;"	d
SIM_SCR3_SCR3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6240;"	d
SIM_SCR4	.\Static_Code\IO_Map\MC56F82748.h	6320;"	d
SIM_SCR4_REG	.\Static_Code\IO_Map\MC56F82748.h	5817;"	d
SIM_SCR4_SCR4	.\Static_Code\IO_Map\MC56F82748.h	6245;"	d
SIM_SCR4_SCR4_MASK	.\Static_Code\IO_Map\MC56F82748.h	6243;"	d
SIM_SCR4_SCR4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6244;"	d
SIM_SCR5	.\Static_Code\IO_Map\MC56F82748.h	6321;"	d
SIM_SCR5_REG	.\Static_Code\IO_Map\MC56F82748.h	5818;"	d
SIM_SCR5_SCR5	.\Static_Code\IO_Map\MC56F82748.h	6249;"	d
SIM_SCR5_SCR5_MASK	.\Static_Code\IO_Map\MC56F82748.h	6247;"	d
SIM_SCR5_SCR5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6248;"	d
SIM_SCR6	.\Static_Code\IO_Map\MC56F82748.h	6322;"	d
SIM_SCR6_REG	.\Static_Code\IO_Map\MC56F82748.h	5819;"	d
SIM_SCR6_SCR6	.\Static_Code\IO_Map\MC56F82748.h	6253;"	d
SIM_SCR6_SCR6_MASK	.\Static_Code\IO_Map\MC56F82748.h	6251;"	d
SIM_SCR6_SCR6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6252;"	d
SIM_SCR7	.\Static_Code\IO_Map\MC56F82748.h	6323;"	d
SIM_SCR7_REG	.\Static_Code\IO_Map\MC56F82748.h	5820;"	d
SIM_SCR7_SCR7	.\Static_Code\IO_Map\MC56F82748.h	6257;"	d
SIM_SCR7_SCR7_MASK	.\Static_Code\IO_Map\MC56F82748.h	6255;"	d
SIM_SCR7_SCR7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6256;"	d
SIM_SD0	.\Static_Code\IO_Map\MC56F82748.h	6293;"	d
SIM_SD0_GPIOA_MASK	.\Static_Code\IO_Map\MC56F82748.h	5978;"	d
SIM_SD0_GPIOA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5979;"	d
SIM_SD0_GPIOB_MASK	.\Static_Code\IO_Map\MC56F82748.h	5976;"	d
SIM_SD0_GPIOB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5977;"	d
SIM_SD0_GPIOC_MASK	.\Static_Code\IO_Map\MC56F82748.h	5974;"	d
SIM_SD0_GPIOC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5975;"	d
SIM_SD0_GPIOD_MASK	.\Static_Code\IO_Map\MC56F82748.h	5972;"	d
SIM_SD0_GPIOD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5973;"	d
SIM_SD0_GPIOE_MASK	.\Static_Code\IO_Map\MC56F82748.h	5970;"	d
SIM_SD0_GPIOE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5971;"	d
SIM_SD0_GPIOF_MASK	.\Static_Code\IO_Map\MC56F82748.h	5968;"	d
SIM_SD0_GPIOF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5969;"	d
SIM_SD0_REG	.\Static_Code\IO_Map\MC56F82748.h	5790;"	d
SIM_SD0_TA0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5986;"	d
SIM_SD0_TA0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5987;"	d
SIM_SD0_TA1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5984;"	d
SIM_SD0_TA1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5985;"	d
SIM_SD0_TA2_MASK	.\Static_Code\IO_Map\MC56F82748.h	5982;"	d
SIM_SD0_TA2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5983;"	d
SIM_SD0_TA3_MASK	.\Static_Code\IO_Map\MC56F82748.h	5980;"	d
SIM_SD0_TA3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5981;"	d
SIM_SD1	.\Static_Code\IO_Map\MC56F82748.h	6294;"	d
SIM_SD1_DACA_MASK	.\Static_Code\IO_Map\MC56F82748.h	6001;"	d
SIM_SD1_DACA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6002;"	d
SIM_SD1_DACB_MASK	.\Static_Code\IO_Map\MC56F82748.h	6003;"	d
SIM_SD1_DACB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6004;"	d
SIM_SD1_IIC0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5991;"	d
SIM_SD1_IIC0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5992;"	d
SIM_SD1_MSCAN_MASK	.\Static_Code\IO_Map\MC56F82748.h	5989;"	d
SIM_SD1_MSCAN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5990;"	d
SIM_SD1_QSPI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5995;"	d
SIM_SD1_QSPI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5996;"	d
SIM_SD1_QSPI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5993;"	d
SIM_SD1_QSPI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5994;"	d
SIM_SD1_REG	.\Static_Code\IO_Map\MC56F82748.h	5791;"	d
SIM_SD1_SCI0_MASK	.\Static_Code\IO_Map\MC56F82748.h	5999;"	d
SIM_SD1_SCI0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6000;"	d
SIM_SD1_SCI1_MASK	.\Static_Code\IO_Map\MC56F82748.h	5997;"	d
SIM_SD1_SCI1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	5998;"	d
SIM_SD2	.\Static_Code\IO_Map\MC56F82748.h	6295;"	d
SIM_SD2_CMPA_MASK	.\Static_Code\IO_Map\MC56F82748.h	6020;"	d
SIM_SD2_CMPA_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6021;"	d
SIM_SD2_CMPB_MASK	.\Static_Code\IO_Map\MC56F82748.h	6018;"	d
SIM_SD2_CMPB_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6019;"	d
SIM_SD2_CMPC_MASK	.\Static_Code\IO_Map\MC56F82748.h	6016;"	d
SIM_SD2_CMPC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6017;"	d
SIM_SD2_CMPD_MASK	.\Static_Code\IO_Map\MC56F82748.h	6014;"	d
SIM_SD2_CMPD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6015;"	d
SIM_SD2_CRC_MASK	.\Static_Code\IO_Map\MC56F82748.h	6010;"	d
SIM_SD2_CRC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6011;"	d
SIM_SD2_CYCADC_MASK	.\Static_Code\IO_Map\MC56F82748.h	6012;"	d
SIM_SD2_CYCADC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6013;"	d
SIM_SD2_PIT0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6008;"	d
SIM_SD2_PIT0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6009;"	d
SIM_SD2_PIT1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6006;"	d
SIM_SD2_PIT1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6007;"	d
SIM_SD2_REG	.\Static_Code\IO_Map\MC56F82748.h	5792;"	d
SIM_SD3	.\Static_Code\IO_Map\MC56F82748.h	6296;"	d
SIM_SD3_PWMACH0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6029;"	d
SIM_SD3_PWMACH0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6030;"	d
SIM_SD3_PWMACH1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6027;"	d
SIM_SD3_PWMACH1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6028;"	d
SIM_SD3_PWMACH2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6025;"	d
SIM_SD3_PWMACH2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6026;"	d
SIM_SD3_PWMACH3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6023;"	d
SIM_SD3_PWMACH3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6024;"	d
SIM_SD3_REG	.\Static_Code\IO_Map\MC56F82748.h	5793;"	d
SLOW_SPEED	.\Static_Code\System\PE_Const.h	12;"	d
SLTH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SLTH;                                   \/**< I2C SCL Low Timeout Register High, offset: 0xA *\/$/;"	m	struct:I2C_MemMap
SLTL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SLTL;                                   \/**< I2C SCL Low Timeout Register Low, offset: 0xB *\/$/;"	m	struct:I2C_MemMap
SM	.\Static_Code\IO_Map\MC56F82748.h	/^  } SM[4];$/;"	m	struct:PWM_MemMap	typeref:struct:PWM_MemMap::__anon59
SMB	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SMB;                                    \/**< I2C SMBus Control and Status register, offset: 0x8 *\/$/;"	m	struct:I2C_MemMap
SPCTL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPCTL2;                                 \/**< SPI Control Register 2, offset: 0x6 *\/$/;"	m	struct:QSPI_MemMap
SPDRR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPDRR;                                  \/**< SPI Data Receive Register, offset: 0x2 *\/$/;"	m	struct:QSPI_MemMap
SPDSR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPDSR;                                  \/**< SPI Data Size and Control Register, offset: 0x1 *\/$/;"	m	struct:QSPI_MemMap
SPDTR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPDTR;                                  \/**< SPI Data Transmit Register, offset: 0x3 *\/$/;"	m	struct:QSPI_MemMap
SPFIFO	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPFIFO;                                 \/**< SPI FIFO Control Register, offset: 0x4 *\/$/;"	m	struct:QSPI_MemMap
SPSCR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPSCR;                                  \/**< SPI Status and Control Register, offset: 0x0 *\/$/;"	m	struct:QSPI_MemMap
SPWAIT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SPWAIT;                                 \/**< SPI Word Delay Register, offset: 0x5 *\/$/;"	m	struct:QSPI_MemMap
SRE	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SRE;                                    \/**< Slew Rate Control Register, offset: 0xD *\/$/;"	m	struct:GPIO_MemMap
SRPIPC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t SRPIPC;                                 \/**< Memory Protection Illegal PC, offset: 0x34 *\/$/;"	m	struct:MCM_MemMap
SRPMPC	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t SRPMPC;                                 \/**< Resource Protection Misaligned PC, offset: 0x38 *\/$/;"	m	struct:MCM_MemMap
SRPOSP	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t SRPOSP;                                 \/**< Resource Protection Other Stack Pointer, offset: 0x30 *\/$/;"	m	struct:MCM_MemMap
SR_lock	.\Static_Code\System\CPU_Init.c	/^volatile uint16_t SR_lock = 0U;            \/* Lock *\/$/;"	v
SR_reg	.\Static_Code\System\CPU_Init.c	/^volatile uint16_t SR_reg;                  \/* Current value of the SR register *\/$/;"	v
STARTUP_CLOCK_EXTERNAL	.\Generated_Code\CPU_Config.h	160;"	d
STARTUP_CLOCK_EXTERNAL_SELECT	.\Generated_Code\CPU_Config.h	163;"	d
STARTUP_CLOCK_INTERNAL	.\Generated_Code\CPU_Config.h	139;"	d
STARTUP_CLOCK_INTERNAL_FAST	.\Generated_Code\CPU_Config.h	149;"	d
STARTUP_CLOCK_INTERNAL_FAST_FREQ_TRIM	.\Generated_Code\CPU_Config.h	151;"	d
STARTUP_CLOCK_INTERNAL_FAST_FREQ_TRIM_VALUE	.\Generated_Code\CPU_Config.h	153;"	d
STARTUP_CLOCK_INTERNAL_FAST_TEMP_TRIM	.\Generated_Code\CPU_Config.h	155;"	d
STARTUP_CLOCK_INTERNAL_FAST_TEMP_TRIM_VALUE	.\Generated_Code\CPU_Config.h	157;"	d
STARTUP_CLOCK_INTERNAL_SLOW	.\Generated_Code\CPU_Config.h	142;"	d
STARTUP_CLOCK_INTERNAL_SLOW_FREQ_TRIM	.\Generated_Code\CPU_Config.h	144;"	d
STARTUP_CLOCK_INTERNAL_SLOW_FREQ_TRIM_VALUE	.\Generated_Code\CPU_Config.h	146;"	d
STARTUP_CLOCK_PROTECTION_FREQUENCY	.\Generated_Code\CPU_Config.h	208;"	d
STARTUP_CLOCK_PROTECTION_OSCILLATOR	.\Generated_Code\CPU_Config.h	210;"	d
STARTUP_CLOCK_PROTECTION_PLL	.\Generated_Code\CPU_Config.h	212;"	d
STARTUP_CLOCK_RATE_I2C	.\Generated_Code\CPU_Config.h	202;"	d
STARTUP_CLOCK_RATE_PWM	.\Generated_Code\CPU_Config.h	200;"	d
STARTUP_CLOCK_RATE_QSCI0	.\Generated_Code\CPU_Config.h	194;"	d
STARTUP_CLOCK_RATE_QSCI1	.\Generated_Code\CPU_Config.h	196;"	d
STARTUP_CLOCK_RATE_TMR	.\Generated_Code\CPU_Config.h	198;"	d
STARTUP_CLOCK_SOURCE_SELECT	.\Generated_Code\CPU_Config.h	166;"	d
STARTUP_COP_CTRL_VALUE	.\Generated_Code\CPU_Config.h	266;"	d
STARTUP_FAST_INT_0	.\Generated_Code\CPU_Config.h	130;"	d
STARTUP_FAST_INT_1	.\Generated_Code\CPU_Config.h	132;"	d
STARTUP_FAST_MODE	.\Generated_Code\CPU_Config.h	217;"	d
STARTUP_INTC_IPR1_VALUE	.\Generated_Code\CPU_Config.h	262;"	d
STARTUP_OCCS_CLKCHKR_VALUE	.\Generated_Code\CPU_Config.h	247;"	d
STARTUP_OCCS_CLKCHKT_VALUE	.\Generated_Code\CPU_Config.h	248;"	d
STARTUP_OCCS_CTRL_VALUE	.\Generated_Code\CPU_Config.h	242;"	d
STARTUP_OCCS_DIVBY_VALUE	.\Generated_Code\CPU_Config.h	243;"	d
STARTUP_OCCS_OSCTL1_VALUE	.\Generated_Code\CPU_Config.h	245;"	d
STARTUP_OCCS_OSCTL2_VALUE	.\Generated_Code\CPU_Config.h	246;"	d
STARTUP_OCCS_PROT_VALUE	.\Generated_Code\CPU_Config.h	249;"	d
STARTUP_OCCS_STAT_VALUE	.\Generated_Code\CPU_Config.h	244;"	d
STARTUP_PLL	.\Generated_Code\CPU_Config.h	170;"	d
STARTUP_PLL_INT	.\Generated_Code\CPU_Config.h	178;"	d
STARTUP_PLL_INT_LOCK_0	.\Generated_Code\CPU_Config.h	181;"	d
STARTUP_PLL_INT_LOCK_1	.\Generated_Code\CPU_Config.h	183;"	d
STARTUP_PLL_INT_PRIORITY	.\Generated_Code\CPU_Config.h	188;"	d
STARTUP_PLL_INT_REFERENCE	.\Generated_Code\CPU_Config.h	185;"	d
STARTUP_SIM_PCR_VALUE	.\Generated_Code\CPU_Config.h	258;"	d
STARTUP_WDOG	.\Generated_Code\CPU_Config.h	222;"	d
STAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t STAT;                                   \/**< ADC Status Register, offset: 0x9 *\/$/;"	m	struct:ADC_MemMap
STAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t STAT;                                   \/**< OCCS Status Register, offset: 0x2 *\/$/;"	m	struct:OCCS_MemMap
STAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t STAT;                                   \/**< QSCI Status Register, offset: 0x3 *\/$/;"	m	struct:QSCI_MemMap
STATUS	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t STATUS;                                 \/**< Status Register, offset: 0x5 *\/$/;"	m	struct:DAC_MemMap
STEPVAL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t STEPVAL;                                \/**< Step Size Register, offset: 0x2 *\/$/;"	m	union:DAC_MemMap::__anon53
STEPVAL_FMT1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t STEPVAL_FMT1;                           \/**< Step Size Register, offset: 0x2 *\/$/;"	m	union:DAC_MemMap::__anon53
STS	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t STS;                                    \/**< Status Register, array offset: 0x12, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
STS	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t STS;                                    \/**< Status Register, offset: 0x1 *\/$/;"	m	struct:PMC_MemMap
SUBDIRS	.\FLASH_SDM\sources.mk	/^SUBDIRS := \\$/;"	m
SWCOUT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t SWCOUT;                                 \/**< Software Controlled Output Register, offset: 0xC2 *\/$/;"	m	struct:PWM_MemMap
S_DEPS	.\FLASH_SDM\sources.mk	/^S_DEPS := $/;"	m
S_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^S_DEPS_OS_FORMAT := $/;"	m
S_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^S_DEPS_QUOTED := $/;"	m
S_SRCS	.\FLASH_SDM\sources.mk	/^S_SRCS := $/;"	m
S_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^S_SRCS_OS_FORMAT := $/;"	m
S_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^S_SRCS_QUOTED := $/;"	m
S_UPPER_DEPS	.\FLASH_SDM\sources.mk	/^S_UPPER_DEPS := $/;"	m
S_UPPER_DEPS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^S_UPPER_DEPS_OS_FORMAT := $/;"	m
S_UPPER_DEPS_QUOTED	.\FLASH_SDM\sources.mk	/^S_UPPER_DEPS_QUOTED := $/;"	m
S_UPPER_SRCS	.\FLASH_SDM\sources.mk	/^S_UPPER_SRCS := $/;"	m
S_UPPER_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^S_UPPER_SRCS_OS_FORMAT := $/;"	m
S_UPPER_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^S_UPPER_SRCS_QUOTED := $/;"	m
Sec	.\Generated_Code\PE_LDD.h	/^  uint16_t Sec;                        \/* Seconds (0 - 59) *\/$/;"	m	struct:__anon9
Sec100	.\Generated_Code\PE_LDD.h	/^  uint16_t Sec100;                     \/* Hundredths of seconds (0 - 99) *\/$/;"	m	struct:__anon9
SeedHigh	.\Generated_Code\PE_LDD.h	/^  uint16_t SeedHigh;                   \/* Seed high value *\/$/;"	m	struct:__anon13
SeedLow	.\Generated_Code\PE_LDD.h	/^  uint16_t SeedLow;                    \/* Seed low value *\/$/;"	m	struct:__anon13
SentChars	.\Generated_Code\PE_LDD.h	/^  uint32_t SentChars;                  \/* Number of transmitted characters *\/$/;"	m	struct:__anon19
SlaveGeneralCallAddr	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveGeneralCallAddr;       \/* Number of a general call address. *\/$/;"	m	struct:__anon25
SlaveReceivedChars	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveReceivedChars;         \/* Number of slave received characters. *\/$/;"	m	struct:__anon25
SlaveRxOverrun	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveRxOverrun;             \/* Number of slave overrun. *\/$/;"	m	struct:__anon25
SlaveSentChars	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveSentChars;             \/* Number of slave transmitted characters. *\/$/;"	m	struct:__anon25
SlaveSmBusAlertResponse	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveSmBusAlertResponse;    \/* Number of slave SMBus alert response received. *\/$/;"	m	struct:__anon25
SlaveSmBusCallAddr	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveSmBusCallAddr;         \/* Number of a SMBus call address. *\/$/;"	m	struct:__anon25
SlaveTxUnderrun	.\Generated_Code\PE_LDD.h	/^  uint32_t SlaveTxUnderrun;            \/* Number of slave underrun. *\/$/;"	m	struct:__anon25
TAAK	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TAAK;                                   \/**< MSCAN Transmitter Message Abort Acknowledge Register, offset: 0x9 *\/$/;"	m	struct:CAN_MemMap
TAGVD	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t TAGVD[4][4];                            \/**< Cache Tag Storage, array offset: 0x80, array step: index*0x8, index2*0x2 *\/$/;"	m	struct:FMC_MemMap
TARQ	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TARQ;                                   \/**< MSCAN Transmitter Message Abort Request Register, offset: 0x8 *\/$/;"	m	struct:CAN_MemMap
TBSEL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TBSEL;                                  \/**< MSCAN Transmit Buffer Selection Register, offset: 0xA *\/$/;"	m	struct:CAN_MemMap
TCTRL	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t TCTRL;                                  \/**< Output Trigger Control Register, array offset: 0x15, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
TCpuBusFreqHz	.\Generated_Code\CPU_Config.h	/^typedef uint32_t TCpuBusFreqHz;$/;"	t
TCpuClockConfiguration	.\Generated_Code\Cpu.h	/^} TCpuClockConfiguration;$/;"	t	typeref:struct:__anon2
TCpuClockDivider	.\Generated_Code\CPU_Config.h	/^typedef uint16_t TCpuClockDivider;$/;"	t
TCpuClockRate	.\Generated_Code\CPU_Config.h	/^typedef uint16_t TCpuClockRate;$/;"	t
TCpuClockSource	.\Generated_Code\CPU_Config.h	/^} TCpuClockSource;$/;"	t	typeref:enum:__anon3
TCpuNumberOfPllChecks	.\Generated_Code\CPU_Config.h	/^typedef uint32_t TCpuNumberOfPllChecks;$/;"	t
TCpuPllEnabled	.\Generated_Code\CPU_Config.h	/^typedef uint16_t TCpuPllEnabled;$/;"	t
TFLG	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TFLG;                                   \/**< MSCAN Transmitter Flag Register, offset: 0x6 *\/$/;"	m	struct:CAN_MemMap
TIER	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TIER;                                   \/**< MSCAN Transmitter Interrupt Enable Register, offset: 0x7 *\/$/;"	m	struct:CAN_MemMap
TIMAGE	.\Static_Code\System\PE_Types.h	/^} TIMAGE;$/;"	t	typeref:struct:__anon64
TMR_0_CAPT	.\Static_Code\IO_Map\MC56F82748.h	6562;"	d
TMR_0_CMPLD1	.\Static_Code\IO_Map\MC56F82748.h	6568;"	d
TMR_0_CMPLD2	.\Static_Code\IO_Map\MC56F82748.h	6569;"	d
TMR_0_CNTR	.\Static_Code\IO_Map\MC56F82748.h	6565;"	d
TMR_0_COMP1	.\Static_Code\IO_Map\MC56F82748.h	6560;"	d
TMR_0_COMP2	.\Static_Code\IO_Map\MC56F82748.h	6561;"	d
TMR_0_CSCTRL	.\Static_Code\IO_Map\MC56F82748.h	6570;"	d
TMR_0_CTRL	.\Static_Code\IO_Map\MC56F82748.h	6566;"	d
TMR_0_DMA	.\Static_Code\IO_Map\MC56F82748.h	6572;"	d
TMR_0_ENBL	.\Static_Code\IO_Map\MC56F82748.h	6573;"	d
TMR_0_FILT	.\Static_Code\IO_Map\MC56F82748.h	6571;"	d
TMR_0_HOLD	.\Static_Code\IO_Map\MC56F82748.h	6564;"	d
TMR_0_LOAD	.\Static_Code\IO_Map\MC56F82748.h	6563;"	d
TMR_0_SCTRL	.\Static_Code\IO_Map\MC56F82748.h	6567;"	d
TMR_1_CAPT	.\Static_Code\IO_Map\MC56F82748.h	6576;"	d
TMR_1_CMPLD1	.\Static_Code\IO_Map\MC56F82748.h	6582;"	d
TMR_1_CMPLD2	.\Static_Code\IO_Map\MC56F82748.h	6583;"	d
TMR_1_CNTR	.\Static_Code\IO_Map\MC56F82748.h	6579;"	d
TMR_1_COMP1	.\Static_Code\IO_Map\MC56F82748.h	6574;"	d
TMR_1_COMP2	.\Static_Code\IO_Map\MC56F82748.h	6575;"	d
TMR_1_CSCTRL	.\Static_Code\IO_Map\MC56F82748.h	6584;"	d
TMR_1_CTRL	.\Static_Code\IO_Map\MC56F82748.h	6580;"	d
TMR_1_DMA	.\Static_Code\IO_Map\MC56F82748.h	6586;"	d
TMR_1_FILT	.\Static_Code\IO_Map\MC56F82748.h	6585;"	d
TMR_1_HOLD	.\Static_Code\IO_Map\MC56F82748.h	6578;"	d
TMR_1_LOAD	.\Static_Code\IO_Map\MC56F82748.h	6577;"	d
TMR_1_SCTRL	.\Static_Code\IO_Map\MC56F82748.h	6581;"	d
TMR_2_CAPT	.\Static_Code\IO_Map\MC56F82748.h	6589;"	d
TMR_2_CMPLD1	.\Static_Code\IO_Map\MC56F82748.h	6595;"	d
TMR_2_CMPLD2	.\Static_Code\IO_Map\MC56F82748.h	6596;"	d
TMR_2_CNTR	.\Static_Code\IO_Map\MC56F82748.h	6592;"	d
TMR_2_COMP1	.\Static_Code\IO_Map\MC56F82748.h	6587;"	d
TMR_2_COMP2	.\Static_Code\IO_Map\MC56F82748.h	6588;"	d
TMR_2_CSCTRL	.\Static_Code\IO_Map\MC56F82748.h	6597;"	d
TMR_2_CTRL	.\Static_Code\IO_Map\MC56F82748.h	6593;"	d
TMR_2_DMA	.\Static_Code\IO_Map\MC56F82748.h	6599;"	d
TMR_2_FILT	.\Static_Code\IO_Map\MC56F82748.h	6598;"	d
TMR_2_HOLD	.\Static_Code\IO_Map\MC56F82748.h	6591;"	d
TMR_2_LOAD	.\Static_Code\IO_Map\MC56F82748.h	6590;"	d
TMR_2_SCTRL	.\Static_Code\IO_Map\MC56F82748.h	6594;"	d
TMR_3_CAPT	.\Static_Code\IO_Map\MC56F82748.h	6602;"	d
TMR_3_CMPLD1	.\Static_Code\IO_Map\MC56F82748.h	6608;"	d
TMR_3_CMPLD2	.\Static_Code\IO_Map\MC56F82748.h	6609;"	d
TMR_3_CNTR	.\Static_Code\IO_Map\MC56F82748.h	6605;"	d
TMR_3_COMP1	.\Static_Code\IO_Map\MC56F82748.h	6600;"	d
TMR_3_COMP2	.\Static_Code\IO_Map\MC56F82748.h	6601;"	d
TMR_3_CSCTRL	.\Static_Code\IO_Map\MC56F82748.h	6610;"	d
TMR_3_CTRL	.\Static_Code\IO_Map\MC56F82748.h	6606;"	d
TMR_3_DMA	.\Static_Code\IO_Map\MC56F82748.h	6612;"	d
TMR_3_FILT	.\Static_Code\IO_Map\MC56F82748.h	6611;"	d
TMR_3_HOLD	.\Static_Code\IO_Map\MC56F82748.h	6604;"	d
TMR_3_LOAD	.\Static_Code\IO_Map\MC56F82748.h	6603;"	d
TMR_3_SCTRL	.\Static_Code\IO_Map\MC56F82748.h	6607;"	d
TMR_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	6544;"	d
TMR_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	6546;"	d
TMR_CAPT	.\Static_Code\IO_Map\MC56F82748.h	6617;"	d
TMR_CAPT_CAPTURE	.\Static_Code\IO_Map\MC56F82748.h	6416;"	d
TMR_CAPT_CAPTURE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6414;"	d
TMR_CAPT_CAPTURE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6415;"	d
TMR_CAPT_REG	.\Static_Code\IO_Map\MC56F82748.h	6378;"	d
TMR_CMPLD1	.\Static_Code\IO_Map\MC56F82748.h	6623;"	d
TMR_CMPLD1_COMPARATOR_LOAD_1	.\Static_Code\IO_Map\MC56F82748.h	6485;"	d
TMR_CMPLD1_COMPARATOR_LOAD_1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6483;"	d
TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6484;"	d
TMR_CMPLD1_REG	.\Static_Code\IO_Map\MC56F82748.h	6384;"	d
TMR_CMPLD2	.\Static_Code\IO_Map\MC56F82748.h	6624;"	d
TMR_CMPLD2_COMPARATOR_LOAD_2	.\Static_Code\IO_Map\MC56F82748.h	6489;"	d
TMR_CMPLD2_COMPARATOR_LOAD_2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6487;"	d
TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6488;"	d
TMR_CMPLD2_REG	.\Static_Code\IO_Map\MC56F82748.h	6385;"	d
TMR_CNTR	.\Static_Code\IO_Map\MC56F82748.h	6620;"	d
TMR_CNTR_COUNTER	.\Static_Code\IO_Map\MC56F82748.h	6428;"	d
TMR_CNTR_COUNTER_MASK	.\Static_Code\IO_Map\MC56F82748.h	6426;"	d
TMR_CNTR_COUNTER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6427;"	d
TMR_CNTR_REG	.\Static_Code\IO_Map\MC56F82748.h	6381;"	d
TMR_COMP1	.\Static_Code\IO_Map\MC56F82748.h	6615;"	d
TMR_COMP1_COMPARISON_1	.\Static_Code\IO_Map\MC56F82748.h	6408;"	d
TMR_COMP1_COMPARISON_1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6406;"	d
TMR_COMP1_COMPARISON_1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6407;"	d
TMR_COMP1_REG	.\Static_Code\IO_Map\MC56F82748.h	6376;"	d
TMR_COMP2	.\Static_Code\IO_Map\MC56F82748.h	6616;"	d
TMR_COMP2_COMPARISON_2	.\Static_Code\IO_Map\MC56F82748.h	6412;"	d
TMR_COMP2_COMPARISON_2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6410;"	d
TMR_COMP2_COMPARISON_2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6411;"	d
TMR_COMP2_REG	.\Static_Code\IO_Map\MC56F82748.h	6377;"	d
TMR_CSCTRL	.\Static_Code\IO_Map\MC56F82748.h	6625;"	d
TMR_CSCTRL_ALT_LOAD_MASK	.\Static_Code\IO_Map\MC56F82748.h	6511;"	d
TMR_CSCTRL_ALT_LOAD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6512;"	d
TMR_CSCTRL_CL1	.\Static_Code\IO_Map\MC56F82748.h	6493;"	d
TMR_CSCTRL_CL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6491;"	d
TMR_CSCTRL_CL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6492;"	d
TMR_CSCTRL_CL2	.\Static_Code\IO_Map\MC56F82748.h	6496;"	d
TMR_CSCTRL_CL2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6494;"	d
TMR_CSCTRL_CL2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6495;"	d
TMR_CSCTRL_DBG_EN	.\Static_Code\IO_Map\MC56F82748.h	6517;"	d
TMR_CSCTRL_DBG_EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	6515;"	d
TMR_CSCTRL_DBG_EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6516;"	d
TMR_CSCTRL_FAULT_MASK	.\Static_Code\IO_Map\MC56F82748.h	6513;"	d
TMR_CSCTRL_FAULT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6514;"	d
TMR_CSCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	6386;"	d
TMR_CSCTRL_ROC_MASK	.\Static_Code\IO_Map\MC56F82748.h	6509;"	d
TMR_CSCTRL_ROC_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6510;"	d
TMR_CSCTRL_TCF1EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	6501;"	d
TMR_CSCTRL_TCF1EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6502;"	d
TMR_CSCTRL_TCF1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6497;"	d
TMR_CSCTRL_TCF1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6498;"	d
TMR_CSCTRL_TCF2EN_MASK	.\Static_Code\IO_Map\MC56F82748.h	6503;"	d
TMR_CSCTRL_TCF2EN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6504;"	d
TMR_CSCTRL_TCF2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6499;"	d
TMR_CSCTRL_TCF2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6500;"	d
TMR_CSCTRL_TCI_MASK	.\Static_Code\IO_Map\MC56F82748.h	6507;"	d
TMR_CSCTRL_TCI_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6508;"	d
TMR_CSCTRL_UP_MASK	.\Static_Code\IO_Map\MC56F82748.h	6505;"	d
TMR_CSCTRL_UP_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6506;"	d
TMR_CTRL	.\Static_Code\IO_Map\MC56F82748.h	6621;"	d
TMR_CTRL_CM	.\Static_Code\IO_Map\MC56F82748.h	6449;"	d
TMR_CTRL_CM_MASK	.\Static_Code\IO_Map\MC56F82748.h	6447;"	d
TMR_CTRL_CM_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6448;"	d
TMR_CTRL_COINIT_MASK	.\Static_Code\IO_Map\MC56F82748.h	6433;"	d
TMR_CTRL_COINIT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6434;"	d
TMR_CTRL_DIR_MASK	.\Static_Code\IO_Map\MC56F82748.h	6435;"	d
TMR_CTRL_DIR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6436;"	d
TMR_CTRL_LENGTH_MASK	.\Static_Code\IO_Map\MC56F82748.h	6437;"	d
TMR_CTRL_LENGTH_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6438;"	d
TMR_CTRL_ONCE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6439;"	d
TMR_CTRL_ONCE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6440;"	d
TMR_CTRL_OUTMODE	.\Static_Code\IO_Map\MC56F82748.h	6432;"	d
TMR_CTRL_OUTMODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6430;"	d
TMR_CTRL_OUTMODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6431;"	d
TMR_CTRL_PCS	.\Static_Code\IO_Map\MC56F82748.h	6446;"	d
TMR_CTRL_PCS_MASK	.\Static_Code\IO_Map\MC56F82748.h	6444;"	d
TMR_CTRL_PCS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6445;"	d
TMR_CTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	6382;"	d
TMR_CTRL_SCS	.\Static_Code\IO_Map\MC56F82748.h	6443;"	d
TMR_CTRL_SCS_MASK	.\Static_Code\IO_Map\MC56F82748.h	6441;"	d
TMR_CTRL_SCS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6442;"	d
TMR_DMA	.\Static_Code\IO_Map\MC56F82748.h	6627;"	d
TMR_DMA_CMPLD1DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6528;"	d
TMR_DMA_CMPLD1DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6529;"	d
TMR_DMA_CMPLD2DE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6530;"	d
TMR_DMA_CMPLD2DE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6531;"	d
TMR_DMA_IEFDE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6526;"	d
TMR_DMA_IEFDE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6527;"	d
TMR_DMA_REG	.\Static_Code\IO_Map\MC56F82748.h	6388;"	d
TMR_ENBL	.\Static_Code\IO_Map\MC56F82748.h	6628;"	d
TMR_ENBL_ENBL	.\Static_Code\IO_Map\MC56F82748.h	6535;"	d
TMR_ENBL_ENBL_MASK	.\Static_Code\IO_Map\MC56F82748.h	6533;"	d
TMR_ENBL_ENBL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6534;"	d
TMR_ENBL_REG	.\Static_Code\IO_Map\MC56F82748.h	6389;"	d
TMR_FILT	.\Static_Code\IO_Map\MC56F82748.h	6626;"	d
TMR_FILT_FILT_CNT	.\Static_Code\IO_Map\MC56F82748.h	6524;"	d
TMR_FILT_FILT_CNT_MASK	.\Static_Code\IO_Map\MC56F82748.h	6522;"	d
TMR_FILT_FILT_CNT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6523;"	d
TMR_FILT_FILT_PER	.\Static_Code\IO_Map\MC56F82748.h	6521;"	d
TMR_FILT_FILT_PER_MASK	.\Static_Code\IO_Map\MC56F82748.h	6519;"	d
TMR_FILT_FILT_PER_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6520;"	d
TMR_FILT_REG	.\Static_Code\IO_Map\MC56F82748.h	6387;"	d
TMR_HOLD	.\Static_Code\IO_Map\MC56F82748.h	6619;"	d
TMR_HOLD_HOLD	.\Static_Code\IO_Map\MC56F82748.h	6424;"	d
TMR_HOLD_HOLD_MASK	.\Static_Code\IO_Map\MC56F82748.h	6422;"	d
TMR_HOLD_HOLD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6423;"	d
TMR_HOLD_REG	.\Static_Code\IO_Map\MC56F82748.h	6380;"	d
TMR_Init	.\Static_Code\Peripherals\TMR_Init.c	/^void TMR_Init(void) {$/;"	f
TMR_LOAD	.\Static_Code\IO_Map\MC56F82748.h	6618;"	d
TMR_LOAD_LOAD	.\Static_Code\IO_Map\MC56F82748.h	6420;"	d
TMR_LOAD_LOAD_MASK	.\Static_Code\IO_Map\MC56F82748.h	6418;"	d
TMR_LOAD_LOAD_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6419;"	d
TMR_LOAD_REG	.\Static_Code\IO_Map\MC56F82748.h	6379;"	d
TMR_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct TMR_MemMap {$/;"	s
TMR_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *TMR_MemMapPtr;$/;"	t
TMR_PDD_CAPTURE_BOTH	.\Static_Code\PDD\TMR_PDD.h	112;"	d
TMR_PDD_CAPTURE_DISABLED	.\Static_Code\PDD\TMR_PDD.h	109;"	d
TMR_PDD_CAPTURE_FALLING	.\Static_Code\PDD\TMR_PDD.h	111;"	d
TMR_PDD_CAPTURE_RISING	.\Static_Code\PDD\TMR_PDD.h	110;"	d
TMR_PDD_CLC_COMP1	.\Static_Code\PDD\TMR_PDD.h	126;"	d
TMR_PDD_CLC_COMP2	.\Static_Code\PDD\TMR_PDD.h	127;"	d
TMR_PDD_CLC_NEVER	.\Static_Code\PDD\TMR_PDD.h	125;"	d
TMR_PDD_CM_BOTH_EDGES	.\Static_Code\PDD\TMR_PDD.h	55;"	d
TMR_PDD_CM_CASCADED	.\Static_Code\PDD\TMR_PDD.h	60;"	d
TMR_PDD_CM_GATED	.\Static_Code\PDD\TMR_PDD.h	56;"	d
TMR_PDD_CM_QUADRATURE	.\Static_Code\PDD\TMR_PDD.h	57;"	d
TMR_PDD_CM_RISING_EDGES	.\Static_Code\PDD\TMR_PDD.h	54;"	d
TMR_PDD_CM_SIGNED	.\Static_Code\PDD\TMR_PDD.h	58;"	d
TMR_PDD_CM_STOP	.\Static_Code\PDD\TMR_PDD.h	53;"	d
TMR_PDD_CM_TRIGGERED	.\Static_Code\PDD\TMR_PDD.h	59;"	d
TMR_PDD_ClearCmp1InterruptFlag	.\Static_Code\PDD\TMR_PDD.h	1322;"	d
TMR_PDD_ClearCmp2InterruptFlag	.\Static_Code\PDD\TMR_PDD.h	1274;"	d
TMR_PDD_ClearCmpInterruptFlag	.\Static_Code\PDD\TMR_PDD.h	421;"	d
TMR_PDD_ClearEdgeInterruptFlag	.\Static_Code\PDD\TMR_PDD.h	609;"	d
TMR_PDD_ClearOvfInterruptFlag	.\Static_Code\PDD\TMR_PDD.h	515;"	d
TMR_PDD_DEBUG_FORCE	.\Static_Code\PDD\TMR_PDD.h	117;"	d
TMR_PDD_DEBUG_HALT	.\Static_Code\PDD\TMR_PDD.h	116;"	d
TMR_PDD_DEBUG_HALT_FORCE	.\Static_Code\PDD\TMR_PDD.h	118;"	d
TMR_PDD_DEBUG_NORMAL	.\Static_Code\PDD\TMR_PDD.h	115;"	d
TMR_PDD_DIR_COUNT_DOWN	.\Static_Code\PDD\TMR_PDD.h	92;"	d
TMR_PDD_DIR_COUNT_UP	.\Static_Code\PDD\TMR_PDD.h	91;"	d
TMR_PDD_DisableCmp1Interrupt	.\Static_Code\PDD\TMR_PDD.h	1226;"	d
TMR_PDD_DisableCmp2Interrupt	.\Static_Code\PDD\TMR_PDD.h	1177;"	d
TMR_PDD_DisableCmpInterrupt	.\Static_Code\PDD\TMR_PDD.h	470;"	d
TMR_PDD_DisableEdgeInterrupt	.\Static_Code\PDD\TMR_PDD.h	658;"	d
TMR_PDD_DisableOvfInterrupt	.\Static_Code\PDD\TMR_PDD.h	564;"	d
TMR_PDD_ENBL_0_MASK	.\Static_Code\PDD\TMR_PDD.h	47;"	d
TMR_PDD_ENBL_1_MASK	.\Static_Code\PDD\TMR_PDD.h	48;"	d
TMR_PDD_ENBL_2_MASK	.\Static_Code\PDD\TMR_PDD.h	49;"	d
TMR_PDD_ENBL_3_MASK	.\Static_Code\PDD\TMR_PDD.h	50;"	d
TMR_PDD_EnableAlternativeLoad	.\Static_Code\PDD\TMR_PDD.h	1029;"	d
TMR_PDD_EnableChannel	.\Static_Code\PDD\TMR_PDD.h	1527;"	d
TMR_PDD_EnableCmp1Interrupt	.\Static_Code\PDD\TMR_PDD.h	1201;"	d
TMR_PDD_EnableCmp2Interrupt	.\Static_Code\PDD\TMR_PDD.h	1152;"	d
TMR_PDD_EnableCmpInterrupt	.\Static_Code\PDD\TMR_PDD.h	445;"	d
TMR_PDD_EnableCoChannelInit	.\Static_Code\PDD\TMR_PDD.h	346;"	d
TMR_PDD_EnableCountOnce	.\Static_Code\PDD\TMR_PDD.h	260;"	d
TMR_PDD_EnableDmaPreload1	.\Static_Code\PDD\TMR_PDD.h	1495;"	d
TMR_PDD_EnableDmaPreload2	.\Static_Code\PDD\TMR_PDD.h	1462;"	d
TMR_PDD_EnableEdgeInterrupt	.\Static_Code\PDD\TMR_PDD.h	633;"	d
TMR_PDD_EnableExternalFlagForce	.\Static_Code\PDD\TMR_PDD.h	810;"	d
TMR_PDD_EnableFault	.\Static_Code\PDD\TMR_PDD.h	993;"	d
TMR_PDD_EnableMasterMode	.\Static_Code\PDD\TMR_PDD.h	775;"	d
TMR_PDD_EnableOutput	.\Static_Code\PDD\TMR_PDD.h	931;"	d
TMR_PDD_EnableOvfInterrupt	.\Static_Code\PDD\TMR_PDD.h	539;"	d
TMR_PDD_EnableReloadOnCapture	.\Static_Code\PDD\TMR_PDD.h	1064;"	d
TMR_PDD_FILT_COUNT_10	.\Static_Code\PDD\TMR_PDD.h	137;"	d
TMR_PDD_FILT_COUNT_3	.\Static_Code\PDD\TMR_PDD.h	130;"	d
TMR_PDD_FILT_COUNT_4	.\Static_Code\PDD\TMR_PDD.h	131;"	d
TMR_PDD_FILT_COUNT_5	.\Static_Code\PDD\TMR_PDD.h	132;"	d
TMR_PDD_FILT_COUNT_6	.\Static_Code\PDD\TMR_PDD.h	133;"	d
TMR_PDD_FILT_COUNT_7	.\Static_Code\PDD\TMR_PDD.h	134;"	d
TMR_PDD_FILT_COUNT_8	.\Static_Code\PDD\TMR_PDD.h	135;"	d
TMR_PDD_FILT_COUNT_9	.\Static_Code\PDD\TMR_PDD.h	136;"	d
TMR_PDD_ForceOutputFlag	.\Static_Code\PDD\TMR_PDD.h	869;"	d
TMR_PDD_GROUP_0	.\Static_Code\PDD\TMR_PDD.h	41;"	d
TMR_PDD_GROUP_1	.\Static_Code\PDD\TMR_PDD.h	42;"	d
TMR_PDD_GROUP_2	.\Static_Code\PDD\TMR_PDD.h	43;"	d
TMR_PDD_GROUP_3	.\Static_Code\PDD\TMR_PDD.h	44;"	d
TMR_PDD_GetCmp1InterruptFlag	.\Static_Code\PDD\TMR_PDD.h	1299;"	d
TMR_PDD_GetCmp2InterruptFlag	.\Static_Code\PDD\TMR_PDD.h	1251;"	d
TMR_PDD_GetCmpInterruptFlag	.\Static_Code\PDD\TMR_PDD.h	401;"	d
TMR_PDD_GetCountingDirection	.\Static_Code\PDD\TMR_PDD.h	1129;"	d
TMR_PDD_GetEdgeInterruptFlag	.\Static_Code\PDD\TMR_PDD.h	589;"	d
TMR_PDD_GetEnableDeviceStatus	.\Static_Code\PDD\TMR_PDD.h	183;"	d
TMR_PDD_GetInputState	.\Static_Code\PDD\TMR_PDD.h	718;"	d
TMR_PDD_GetOvfInterruptFlag	.\Static_Code\PDD\TMR_PDD.h	495;"	d
TMR_PDD_H_	.\Static_Code\PDD\TMR_PDD.h	9;"	d
TMR_PDD_LENGTH_REINIT	.\Static_Code\PDD\TMR_PDD.h	88;"	d
TMR_PDD_LENGTH_ROLLOVER	.\Static_Code\PDD\TMR_PDD.h	87;"	d
TMR_PDD_OM_ASSERTED	.\Static_Code\PDD\TMR_PDD.h	95;"	d
TMR_PDD_OM_CLEAR	.\Static_Code\PDD\TMR_PDD.h	96;"	d
TMR_PDD_OM_GATED	.\Static_Code\PDD\TMR_PDD.h	102;"	d
TMR_PDD_OM_SET	.\Static_Code\PDD\TMR_PDD.h	97;"	d
TMR_PDD_OM_SET_INPUT_CLEAR	.\Static_Code\PDD\TMR_PDD.h	100;"	d
TMR_PDD_OM_SET_ROLLOVER_CLEAR	.\Static_Code\PDD\TMR_PDD.h	101;"	d
TMR_PDD_OM_TOGGLE	.\Static_Code\PDD\TMR_PDD.h	98;"	d
TMR_PDD_OM_TOGGLE_ALT	.\Static_Code\PDD\TMR_PDD.h	99;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_1	.\Static_Code\PDD\TMR_PDD.h	71;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_128	.\Static_Code\PDD\TMR_PDD.h	78;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_16	.\Static_Code\PDD\TMR_PDD.h	75;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_2	.\Static_Code\PDD\TMR_PDD.h	72;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_32	.\Static_Code\PDD\TMR_PDD.h	76;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_4	.\Static_Code\PDD\TMR_PDD.h	73;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_64	.\Static_Code\PDD\TMR_PDD.h	77;"	d
TMR_PDD_PCS_BUSCLK_DIVIDE_8	.\Static_Code\PDD\TMR_PDD.h	74;"	d
TMR_PDD_PCS_COUNTER_0_INPUT	.\Static_Code\PDD\TMR_PDD.h	63;"	d
TMR_PDD_PCS_COUNTER_0_OUTPUT	.\Static_Code\PDD\TMR_PDD.h	67;"	d
TMR_PDD_PCS_COUNTER_1_INPUT	.\Static_Code\PDD\TMR_PDD.h	64;"	d
TMR_PDD_PCS_COUNTER_1_OUTPUT	.\Static_Code\PDD\TMR_PDD.h	68;"	d
TMR_PDD_PCS_COUNTER_2_INPUT	.\Static_Code\PDD\TMR_PDD.h	65;"	d
TMR_PDD_PCS_COUNTER_2_OUTPUT	.\Static_Code\PDD\TMR_PDD.h	69;"	d
TMR_PDD_PCS_COUNTER_3_INPUT	.\Static_Code\PDD\TMR_PDD.h	66;"	d
TMR_PDD_PCS_COUNTER_3_OUTPUT	.\Static_Code\PDD\TMR_PDD.h	70;"	d
TMR_PDD_POLARITY_INVERTED	.\Static_Code\PDD\TMR_PDD.h	106;"	d
TMR_PDD_POLARITY_NORMAL	.\Static_Code\PDD\TMR_PDD.h	105;"	d
TMR_PDD_ReadCaptureReg	.\Static_Code\PDD\TMR_PDD.h	1657;"	d
TMR_PDD_ReadChannelEnableReg	.\Static_Code\PDD\TMR_PDD.h	2120;"	d
TMR_PDD_ReadCmpLoad1Reg	.\Static_Code\PDD\TMR_PDD.h	1909;"	d
TMR_PDD_ReadCmpLoad2Reg	.\Static_Code\PDD\TMR_PDD.h	1951;"	d
TMR_PDD_ReadCmpStatusReg	.\Static_Code\PDD\TMR_PDD.h	1993;"	d
TMR_PDD_ReadCompare1Reg	.\Static_Code\PDD\TMR_PDD.h	1573;"	d
TMR_PDD_ReadCompare2Reg	.\Static_Code\PDD\TMR_PDD.h	1615;"	d
TMR_PDD_ReadControlReg	.\Static_Code\PDD\TMR_PDD.h	1825;"	d
TMR_PDD_ReadCounterReg	.\Static_Code\PDD\TMR_PDD.h	1783;"	d
TMR_PDD_ReadDmaEnableReg	.\Static_Code\PDD\TMR_PDD.h	2077;"	d
TMR_PDD_ReadHoldReg	.\Static_Code\PDD\TMR_PDD.h	1741;"	d
TMR_PDD_ReadInputFilterReg	.\Static_Code\PDD\TMR_PDD.h	2035;"	d
TMR_PDD_ReadLoadReg	.\Static_Code\PDD\TMR_PDD.h	1699;"	d
TMR_PDD_ReadStatusReg	.\Static_Code\PDD\TMR_PDD.h	1867;"	d
TMR_PDD_SCS_COUNTER_0_INPUT	.\Static_Code\PDD\TMR_PDD.h	81;"	d
TMR_PDD_SCS_COUNTER_1_INPUT	.\Static_Code\PDD\TMR_PDD.h	82;"	d
TMR_PDD_SCS_COUNTER_2_INPUT	.\Static_Code\PDD\TMR_PDD.h	83;"	d
TMR_PDD_SCS_COUNTER_3_INPUT	.\Static_Code\PDD\TMR_PDD.h	84;"	d
TMR_PDD_SetCaptureMode	.\Static_Code\PDD\TMR_PDD.h	745;"	d
TMR_PDD_SetCompareLoadControl1	.\Static_Code\PDD\TMR_PDD.h	1378;"	d
TMR_PDD_SetCompareLoadControl2	.\Static_Code\PDD\TMR_PDD.h	1349;"	d
TMR_PDD_SetCountDirection	.\Static_Code\PDD\TMR_PDD.h	320;"	d
TMR_PDD_SetCountLength	.\Static_Code\PDD\TMR_PDD.h	288;"	d
TMR_PDD_SetCountMode	.\Static_Code\PDD\TMR_PDD.h	158;"	d
TMR_PDD_SetDebugMode	.\Static_Code\PDD\TMR_PDD.h	965;"	d
TMR_PDD_SetFilterCount	.\Static_Code\PDD\TMR_PDD.h	1405;"	d
TMR_PDD_SetFilterPeriod	.\Static_Code\PDD\TMR_PDD.h	1433;"	d
TMR_PDD_SetForcedFlagValue	.\Static_Code\PDD\TMR_PDD.h	843;"	d
TMR_PDD_SetInputPolarity	.\Static_Code\PDD\TMR_PDD.h	686;"	d
TMR_PDD_SetOutMode	.\Static_Code\PDD\TMR_PDD.h	376;"	d
TMR_PDD_SetOutputPolarity	.\Static_Code\PDD\TMR_PDD.h	897;"	d
TMR_PDD_SetPrimaryCountSource	.\Static_Code\PDD\TMR_PDD.h	206;"	d
TMR_PDD_SetSecondaryCountSource	.\Static_Code\PDD\TMR_PDD.h	233;"	d
TMR_PDD_SetTriggeredCountInit	.\Static_Code\PDD\TMR_PDD.h	1098;"	d
TMR_PDD_TCI_RELOAD_COUNTER	.\Static_Code\PDD\TMR_PDD.h	122;"	d
TMR_PDD_TCI_STOP_COUNTER	.\Static_Code\PDD\TMR_PDD.h	121;"	d
TMR_PDD_WriteCaptureReg	.\Static_Code\PDD\TMR_PDD.h	1637;"	d
TMR_PDD_WriteChannelEnableReg	.\Static_Code\PDD\TMR_PDD.h	2099;"	d
TMR_PDD_WriteCmpLoad1Reg	.\Static_Code\PDD\TMR_PDD.h	1889;"	d
TMR_PDD_WriteCmpLoad2Reg	.\Static_Code\PDD\TMR_PDD.h	1931;"	d
TMR_PDD_WriteCmpStatusReg	.\Static_Code\PDD\TMR_PDD.h	1973;"	d
TMR_PDD_WriteCompare1Reg	.\Static_Code\PDD\TMR_PDD.h	1553;"	d
TMR_PDD_WriteCompare2Reg	.\Static_Code\PDD\TMR_PDD.h	1595;"	d
TMR_PDD_WriteControlReg	.\Static_Code\PDD\TMR_PDD.h	1805;"	d
TMR_PDD_WriteCounterReg	.\Static_Code\PDD\TMR_PDD.h	1763;"	d
TMR_PDD_WriteDmaEnableReg	.\Static_Code\PDD\TMR_PDD.h	2057;"	d
TMR_PDD_WriteHoldReg	.\Static_Code\PDD\TMR_PDD.h	1721;"	d
TMR_PDD_WriteInputFilterReg	.\Static_Code\PDD\TMR_PDD.h	2015;"	d
TMR_PDD_WriteLoadReg	.\Static_Code\PDD\TMR_PDD.h	1679;"	d
TMR_PDD_WriteStatusReg	.\Static_Code\PDD\TMR_PDD.h	1847;"	d
TMR_SCTRL	.\Static_Code\IO_Map\MC56F82748.h	6622;"	d
TMR_SCTRL_CAPTURE_MODE	.\Static_Code\IO_Map\MC56F82748.h	6465;"	d
TMR_SCTRL_CAPTURE_MODE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6463;"	d
TMR_SCTRL_CAPTURE_MODE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6464;"	d
TMR_SCTRL_EEOF_MASK	.\Static_Code\IO_Map\MC56F82748.h	6459;"	d
TMR_SCTRL_EEOF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6460;"	d
TMR_SCTRL_FORCE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6455;"	d
TMR_SCTRL_FORCE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6456;"	d
TMR_SCTRL_IEFIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6470;"	d
TMR_SCTRL_IEFIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6471;"	d
TMR_SCTRL_IEF_MASK	.\Static_Code\IO_Map\MC56F82748.h	6472;"	d
TMR_SCTRL_IEF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6473;"	d
TMR_SCTRL_INPUT_MASK	.\Static_Code\IO_Map\MC56F82748.h	6466;"	d
TMR_SCTRL_INPUT_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6467;"	d
TMR_SCTRL_IPS_MASK	.\Static_Code\IO_Map\MC56F82748.h	6468;"	d
TMR_SCTRL_IPS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6469;"	d
TMR_SCTRL_MSTR_MASK	.\Static_Code\IO_Map\MC56F82748.h	6461;"	d
TMR_SCTRL_MSTR_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6462;"	d
TMR_SCTRL_OEN_MASK	.\Static_Code\IO_Map\MC56F82748.h	6451;"	d
TMR_SCTRL_OEN_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6452;"	d
TMR_SCTRL_OPS_MASK	.\Static_Code\IO_Map\MC56F82748.h	6453;"	d
TMR_SCTRL_OPS_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6454;"	d
TMR_SCTRL_REG	.\Static_Code\IO_Map\MC56F82748.h	6383;"	d
TMR_SCTRL_TCFIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6478;"	d
TMR_SCTRL_TCFIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6479;"	d
TMR_SCTRL_TCF_MASK	.\Static_Code\IO_Map\MC56F82748.h	6480;"	d
TMR_SCTRL_TCF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6481;"	d
TMR_SCTRL_TOFIE_MASK	.\Static_Code\IO_Map\MC56F82748.h	6474;"	d
TMR_SCTRL_TOFIE_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6475;"	d
TMR_SCTRL_TOF_MASK	.\Static_Code\IO_Map\MC56F82748.h	6476;"	d
TMR_SCTRL_TOF_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6477;"	d
TMR_SCTRL_VAL_MASK	.\Static_Code\IO_Map\MC56F82748.h	6457;"	d
TMR_SCTRL_VAL_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6458;"	d
TODISASSEMBLE_SRCS	.\FLASH_SDM\sources.mk	/^TODISASSEMBLE_SRCS := $/;"	m
TODISASSEMBLE_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^TODISASSEMBLE_SRCS_OS_FORMAT := $/;"	m
TODISASSEMBLE_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^TODISASSEMBLE_SRCS_QUOTED := $/;"	m
TOPREPROCESS_SRCS	.\FLASH_SDM\sources.mk	/^TOPREPROCESS_SRCS := $/;"	m
TOPREPROCESS_SRCS_OS_FORMAT	.\FLASH_SDM\sources.mk	/^TOPREPROCESS_SRCS_OS_FORMAT := $/;"	m
TOPREPROCESS_SRCS_QUOTED	.\FLASH_SDM\sources.mk	/^TOPREPROCESS_SRCS_QUOTED := $/;"	m
TOUT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TOUT;                                   \/**< COP Timeout Register, offset: 0x1 *\/$/;"	m	struct:COP_MemMap
TPE_ErrCode	.\Static_Code\System\PE_Types.h	/^typedef uint8_t TPE_ErrCode;$/;"	t
TPE_Float	.\Static_Code\System\PE_Types.h	/^typedef float TPE_Float;$/;"	t
TRANSPOSE	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TRANSPOSE;                              \/**< CRC Transpose Register, offset: 0x2 *\/$/;"	m	struct:CRC_MemMap
TRUE	.\Static_Code\System\PE_Types.h	20;"	d
TShadowRegs	.\Static_Code\System\CPU_Init.h	/^  } TShadowRegs;$/;"	t	typeref:struct:__anon63
TU1_CNT_INP_FREQ_COUNT	.\Generated_Code\TU1.h	119;"	d
TU1_CNT_INP_FREQ_R_0	.\Generated_Code\TU1.h	118;"	d
TU1_CNT_INP_FREQ_U_0	.\Generated_Code\TU1.h	117;"	d
TU1_COUNTER_DIR	.\Generated_Code\TU1.h	123;"	d
TU1_COUNTER_WIDTH	.\Generated_Code\TU1.h	122;"	d
TU1_Init	.\Generated_Code\TU1.c	/^LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr)$/;"	f
TU1_Init_METHOD_ENABLED	.\Generated_Code\TU1.h	128;"	d
TU1_NUMBER_OF_CHANNELS	.\Generated_Code\TU1.h	121;"	d
TU1_PERIOD_TICKS	.\Generated_Code\TU1.h	120;"	d
TU1_PRPH_BASE_ADDRESS	.\Generated_Code\TU1.h	125;"	d
TU1_TDeviceData	.\Generated_Code\TU1.c	/^} TU1_TDeviceData;$/;"	t	typeref:struct:__anon45	file:
TU1_TDeviceDataPtr	.\Generated_Code\TU1.c	/^typedef TU1_TDeviceData *TU1_TDeviceDataPtr; \/* Pointer to the device data structure. *\/$/;"	t	file:
TU1_TValueType	.\Generated_Code\TU1.h	/^  typedef uint32_t TU1_TValueType ;    \/* Type for data parameters of methods *\/$/;"	t
TWREG	.\Static_Code\System\PE_Types.h	/^} TWREG;$/;"	t	typeref:union:__anon65
TXERR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXERR;                                  \/**< MSCAN Transmit Error Counter Register, offset: 0xF *\/$/;"	m	struct:CAN_MemMap
TXFG_DLR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_DLR;                               \/**< MSCAN Transmit Buffer Data Length Register, offset: 0x3C *\/$/;"	m	struct:CAN_MemMap
TXFG_DSR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_DSR[8];                            \/**< Transmit Buffer Data Segment Registers, array offset: 0x34, array step: 0x1 *\/$/;"	m	struct:CAN_MemMap
TXFG_IDR0_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t TXFG_IDR0_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 0 - Extended Identifer Mapping, offset: 0x30 *\/$/;"	m	union:CAN_MemMap::__anon50
TXFG_IDR0_STD	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t TXFG_IDR0_STD;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 0 - Standard Identifer Mapping, offset: 0x30 *\/$/;"	m	union:CAN_MemMap::__anon50
TXFG_IDR1_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t TXFG_IDR1_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 1 - Extended Identifer Mapping, offset: 0x31 *\/$/;"	m	union:CAN_MemMap::__anon51
TXFG_IDR1_STD	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t TXFG_IDR1_STD;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 1 - Standard Identifier Mapping, offset: 0x31 *\/$/;"	m	union:CAN_MemMap::__anon51
TXFG_IDR2_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_IDR2_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 2 - Extended Identifer Mapping, offset: 0x32 *\/$/;"	m	struct:CAN_MemMap
TXFG_IDR3_EXT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_IDR3_EXT;                          \/**< MSCAN Receive and Transmit Buffer Identifier Register 3 - Extended Identifier Mapping, offset: 0x33 *\/$/;"	m	struct:CAN_MemMap
TXFG_TBPR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_TBPR;                              \/**< MSCAN Transmit Buffer Priority Register, offset: 0x3D *\/$/;"	m	struct:CAN_MemMap
TXFG_TSRH	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_TSRH;                              \/**< Transmit Buffer Time Stamp Register - High Byte, offset: 0x3E *\/$/;"	m	struct:CAN_MemMap
TXFG_TSRL	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t TXFG_TSRL;                              \/**< Transmit Buffer Time Stamp Register - Low Byte, offset: 0x3F *\/$/;"	m	struct:CAN_MemMap
TimeStamp	.\Generated_Code\PE_LDD.h	/^  uint16_t TimeStamp;                  \/* Message time stamp *\/$/;"	m	struct:__anon41
TriggerPinMask	.\Generated_Code\PE_LDD.h	/^  uint16_t TriggerPinMask;             \/*!< Trigger pin mask *\/$/;"	m	struct:__anon42
TxChars	.\Generated_Code\PE_LDD.h	/^  uint32_t TxChars;                    \/* Number of transmitted characters *\/$/;"	m	struct:__anon26
TxChars	.\Generated_Code\PE_LDD.h	/^  uint32_t TxChars;                    \/* Number of transmitted characters *\/$/;"	m	struct:__anon27
TxFrames	.\Generated_Code\PE_LDD.h	/^  uint32_t TxFrames;                   \/* Transmitted frame counter *\/$/;"	m	struct:__anon40
TxUnderruns	.\Generated_Code\PE_LDD.h	/^  uint32_t TxUnderruns;                \/* Number of transmitter underruns, which have occured *\/  $/;"	m	struct:__anon27
TxWarnings	.\Generated_Code\PE_LDD.h	/^  uint32_t TxWarnings;                 \/* Transmission warning counter *\/$/;"	m	struct:__anon40
UFLASHBAR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t UFLASHBAR;                              \/**< User Flash Base Address Register, offset: 0x24 *\/$/;"	m	struct:MCM_MemMap
UInt16	.\Static_Code\System\PE_Types.h	/^typedef unsigned int   UInt16;$/;"	t
UInt32	.\Static_Code\System\PE_Types.h	/^typedef unsigned long  UInt32;$/;"	t
UInt8	.\Static_Code\System\PE_Types.h	/^typedef unsigned char  UInt8;$/;"	t
UPRAMBAR	.\Static_Code\IO_Map\MC56F82748.h	/^  uint32_t UPRAMBAR;                               \/**< User Program RAM Base Address Register, offset: 0x28 *\/$/;"	m	struct:MCM_MemMap
USER_OBJS	.\FLASH_SDM\objects.mk	/^USER_OBJS :=$/;"	m
USER_OBJS_QUOTED	.\FLASH_SDM\objects.mk	/^USER_OBJS_QUOTED :=$/;"	m
UWord16	.\Static_Code\System\PE_Types.h	/^typedef unsigned short UWord16;$/;"	t
UWord32	.\Static_Code\System\PE_Types.h	/^typedef unsigned long  UWord32;$/;"	t
UWord8	.\Static_Code\System\PE_Types.h	/^typedef unsigned char  UWord8;$/;"	t
UnusedPins_Init	.\Static_Code\System\CPU_Init.c	/^void UnusedPins_Init(void)$/;"	f
UpConting	.\Generated_Code\PE_LDD.h	/^  unsigned int UpConting : 1;          \/* Enables up counting *\/$/;"	m	struct:__anon30
UserDataPtr	.\Generated_Code\BitIoLdd1.c	/^  LDD_TUserData *UserDataPtr;          \/* Pointer to user data *\/$/;"	m	struct:__anon1	file:
UserDataPtr	.\Generated_Code\TU1.c	/^  LDD_TUserData *UserDataPtr;          \/* RTOS device data structure *\/$/;"	m	struct:__anon45	file:
VAL0	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t VAL0;                                   \/**< Value Register 0, array offset: 0x5, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
VAL1	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t VAL1;                                   \/**< Value Register 1, array offset: 0x7, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
VAL2	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t VAL2;                                   \/**< Value Register 2, array offset: 0x9, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
VAL3	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t VAL3;                                   \/**< Value Register 3, array offset: 0xB, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
VAL4	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t VAL4;                                   \/**< Value Register 4, array offset: 0xD, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
VAL5	.\Static_Code\IO_Map\MC56F82748.h	/^    uint16_t VAL5;                                   \/**< Value Register 5, array offset: 0xF, array step: 0x30 *\/$/;"	m	struct:PWM_MemMap::__anon59
VBA	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t VBA;                                    \/**< Vector Base Address Register, offset: 0xD *\/$/;"	m	struct:INTC_MemMap
Value	.\Static_Code\System\PE_Types.h	/^        UWord16 Value;$/;"	m	union:__anon75
VoltRefPinMask	.\Generated_Code\PE_LDD.h	/^  uint8_t  VoltRefPinMask;             \/*!< Voltage reference pin mask *\/$/;"	m	struct:__anon42
WINDOW	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t WINDOW;                                 \/**< COP Window Timeout Register, offset: 0x4 *\/$/;"	m	struct:COP_MemMap
Wakeups	.\Generated_Code\PE_LDD.h	/^  uint32_t Wakeups;                    \/* Wakeup counter *\/$/;"	m	struct:__anon40
Width32bit	.\Generated_Code\PE_LDD.h	/^  bool Width32bit;                     \/* 32bir CRC? *\/$/;"	m	struct:__anon13
Word16	.\Static_Code\System\PE_Types.h	/^typedef short          Word16;$/;"	t
Word32	.\Static_Code\System\PE_Types.h	/^typedef long           Word32;$/;"	t
Word8	.\Static_Code\System\PE_Types.h	/^typedef signed char    Word8;$/;"	t
XBARA_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	6915;"	d
XBARA_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	6917;"	d
XBARA_CTRL0	.\Static_Code\IO_Map\MC56F82748.h	6952;"	d
XBARA_CTRL0_DEN0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6870;"	d
XBARA_CTRL0_DEN0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6871;"	d
XBARA_CTRL0_DEN1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6879;"	d
XBARA_CTRL0_DEN1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6880;"	d
XBARA_CTRL0_EDGE0	.\Static_Code\IO_Map\MC56F82748.h	6876;"	d
XBARA_CTRL0_EDGE0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6874;"	d
XBARA_CTRL0_EDGE0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6875;"	d
XBARA_CTRL0_EDGE1	.\Static_Code\IO_Map\MC56F82748.h	6885;"	d
XBARA_CTRL0_EDGE1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6883;"	d
XBARA_CTRL0_EDGE1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6884;"	d
XBARA_CTRL0_IEN0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6872;"	d
XBARA_CTRL0_IEN0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6873;"	d
XBARA_CTRL0_IEN1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6881;"	d
XBARA_CTRL0_IEN1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6882;"	d
XBARA_CTRL0_REG	.\Static_Code\IO_Map\MC56F82748.h	6708;"	d
XBARA_CTRL0_STS0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6877;"	d
XBARA_CTRL0_STS0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6878;"	d
XBARA_CTRL0_STS1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6886;"	d
XBARA_CTRL0_STS1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6887;"	d
XBARA_CTRL1	.\Static_Code\IO_Map\MC56F82748.h	6953;"	d
XBARA_CTRL1_DEN2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6889;"	d
XBARA_CTRL1_DEN2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6890;"	d
XBARA_CTRL1_DEN3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6898;"	d
XBARA_CTRL1_DEN3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6899;"	d
XBARA_CTRL1_EDGE2	.\Static_Code\IO_Map\MC56F82748.h	6895;"	d
XBARA_CTRL1_EDGE2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6893;"	d
XBARA_CTRL1_EDGE2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6894;"	d
XBARA_CTRL1_EDGE3	.\Static_Code\IO_Map\MC56F82748.h	6904;"	d
XBARA_CTRL1_EDGE3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6902;"	d
XBARA_CTRL1_EDGE3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6903;"	d
XBARA_CTRL1_IEN2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6891;"	d
XBARA_CTRL1_IEN2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6892;"	d
XBARA_CTRL1_IEN3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6900;"	d
XBARA_CTRL1_IEN3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6901;"	d
XBARA_CTRL1_REG	.\Static_Code\IO_Map\MC56F82748.h	6709;"	d
XBARA_CTRL1_STS2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6896;"	d
XBARA_CTRL1_STS2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6897;"	d
XBARA_CTRL1_STS3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6905;"	d
XBARA_CTRL1_STS3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6906;"	d
XBARA_Init	.\Static_Code\Peripherals\XBARA_Init.c	/^void XBARA_Init(void) {$/;"	f
XBARA_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct XBARA_MemMap {$/;"	s
XBARA_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *XBARA_MemMapPtr;$/;"	t
XBARA_PDD_AND_OR_INVERT_0	.\Static_Code\PDD\XBARA_PDD.h	70;"	d
XBARA_PDD_AND_OR_INVERT_1	.\Static_Code\PDD\XBARA_PDD.h	71;"	d
XBARA_PDD_AND_OR_INVERT_2	.\Static_Code\PDD\XBARA_PDD.h	72;"	d
XBARA_PDD_AND_OR_INVERT_3	.\Static_Code\PDD\XBARA_PDD.h	73;"	d
XBARA_PDD_BOTH_EDGES	.\Static_Code\PDD\XBARA_PDD.h	84;"	d
XBARA_PDD_CMPA_OUT	.\Static_Code\PDD\XBARA_PDD.h	52;"	d
XBARA_PDD_CMPB_OUT	.\Static_Code\PDD\XBARA_PDD.h	53;"	d
XBARA_PDD_CMPC_OUT	.\Static_Code\PDD\XBARA_PDD.h	54;"	d
XBARA_PDD_CMPD_OUT	.\Static_Code\PDD\XBARA_PDD.h	55;"	d
XBARA_PDD_ClearDMA_REQ0InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3563;"	d
XBARA_PDD_ClearDMA_REQ1InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3585;"	d
XBARA_PDD_ClearDMA_REQ2InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3607;"	d
XBARA_PDD_ClearDMA_REQ3InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3629;"	d
XBARA_PDD_EnableDmaForDMA_REQ0	.\Static_Code\PDD\XBARA_PDD.h	3175;"	d
XBARA_PDD_EnableDmaForDMA_REQ1	.\Static_Code\PDD\XBARA_PDD.h	3207;"	d
XBARA_PDD_EnableDmaForDMA_REQ2	.\Static_Code\PDD\XBARA_PDD.h	3239;"	d
XBARA_PDD_EnableDmaForDMA_REQ3	.\Static_Code\PDD\XBARA_PDD.h	3271;"	d
XBARA_PDD_EnableInterruptForDMA_REQ0	.\Static_Code\PDD\XBARA_PDD.h	2971;"	d
XBARA_PDD_EnableInterruptForDMA_REQ1	.\Static_Code\PDD\XBARA_PDD.h	3003;"	d
XBARA_PDD_EnableInterruptForDMA_REQ2	.\Static_Code\PDD\XBARA_PDD.h	3035;"	d
XBARA_PDD_EnableInterruptForDMA_REQ3	.\Static_Code\PDD\XBARA_PDD.h	3067;"	d
XBARA_PDD_FALLING_EDGE	.\Static_Code\PDD\XBARA_PDD.h	83;"	d
XBARA_PDD_GetADCA_TRIG	.\Static_Code\PDD\XBARA_PDD.h	1327;"	d
XBARA_PDD_GetADCB_TRIG	.\Static_Code\PDD\XBARA_PDD.h	1345;"	d
XBARA_PDD_GetCMPA	.\Static_Code\PDD\XBARA_PDD.h	1404;"	d
XBARA_PDD_GetCMPB	.\Static_Code\PDD\XBARA_PDD.h	1423;"	d
XBARA_PDD_GetCMPC	.\Static_Code\PDD\XBARA_PDD.h	1444;"	d
XBARA_PDD_GetCMPD	.\Static_Code\PDD\XBARA_PDD.h	1463;"	d
XBARA_PDD_GetDACA_12B_SYNC	.\Static_Code\PDD\XBARA_PDD.h	1383;"	d
XBARA_PDD_GetDACB_12B_SYNC	.\Static_Code\PDD\XBARA_PDD.h	1365;"	d
XBARA_PDD_GetDMA_REQ0	.\Static_Code\PDD\XBARA_PDD.h	1099;"	d
XBARA_PDD_GetDMA_REQ0Destination	.\Static_Code\PDD\XBARA_PDD.h	2836;"	d
XBARA_PDD_GetDMA_REQ0EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3480;"	d
XBARA_PDD_GetDMA_REQ0InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3651;"	d
XBARA_PDD_GetDMA_REQ1	.\Static_Code\PDD\XBARA_PDD.h	1117;"	d
XBARA_PDD_GetDMA_REQ1Destination	.\Static_Code\PDD\XBARA_PDD.h	2869;"	d
XBARA_PDD_GetDMA_REQ1EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3501;"	d
XBARA_PDD_GetDMA_REQ1InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3669;"	d
XBARA_PDD_GetDMA_REQ2	.\Static_Code\PDD\XBARA_PDD.h	1137;"	d
XBARA_PDD_GetDMA_REQ2Destination	.\Static_Code\PDD\XBARA_PDD.h	2902;"	d
XBARA_PDD_GetDMA_REQ2EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3522;"	d
XBARA_PDD_GetDMA_REQ2InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3687;"	d
XBARA_PDD_GetDMA_REQ3	.\Static_Code\PDD\XBARA_PDD.h	1155;"	d
XBARA_PDD_GetDMA_REQ3Destination	.\Static_Code\PDD\XBARA_PDD.h	2935;"	d
XBARA_PDD_GetDMA_REQ3EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3543;"	d
XBARA_PDD_GetDMA_REQ3InterruptFlag	.\Static_Code\PDD\XBARA_PDD.h	3705;"	d
XBARA_PDD_GetDmaForDMA_REQ0Enabled	.\Static_Code\PDD\XBARA_PDD.h	3300;"	d
XBARA_PDD_GetDmaForDMA_REQ1Enabled	.\Static_Code\PDD\XBARA_PDD.h	3319;"	d
XBARA_PDD_GetDmaForDMA_REQ2Enabled	.\Static_Code\PDD\XBARA_PDD.h	3338;"	d
XBARA_PDD_GetDmaForDMA_REQ3Enabled	.\Static_Code\PDD\XBARA_PDD.h	3357;"	d
XBARA_PDD_GetEWM_IN	.\Static_Code\PDD\XBARA_PDD.h	1863;"	d
XBARA_PDD_GetInterruptForDMA_REQ0Enabled	.\Static_Code\PDD\XBARA_PDD.h	3096;"	d
XBARA_PDD_GetInterruptForDMA_REQ1Enabled	.\Static_Code\PDD\XBARA_PDD.h	3115;"	d
XBARA_PDD_GetInterruptForDMA_REQ2Enabled	.\Static_Code\PDD\XBARA_PDD.h	3134;"	d
XBARA_PDD_GetInterruptForDMA_REQ3Enabled	.\Static_Code\PDD\XBARA_PDD.h	3153;"	d
XBARA_PDD_GetPWM0_EXTA	.\Static_Code\PDD\XBARA_PDD.h	1483;"	d
XBARA_PDD_GetPWM0_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	1559;"	d
XBARA_PDD_GetPWM1_EXTA	.\Static_Code\PDD\XBARA_PDD.h	1501;"	d
XBARA_PDD_GetPWM1_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	1577;"	d
XBARA_PDD_GetPWM2_EXTA	.\Static_Code\PDD\XBARA_PDD.h	1521;"	d
XBARA_PDD_GetPWM2_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	1597;"	d
XBARA_PDD_GetPWM3_EXTA	.\Static_Code\PDD\XBARA_PDD.h	1539;"	d
XBARA_PDD_GetPWM3_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	1615;"	d
XBARA_PDD_GetPWM_EXT_CLK	.\Static_Code\PDD\XBARA_PDD.h	1635;"	d
XBARA_PDD_GetPWM_FAULT0	.\Static_Code\PDD\XBARA_PDD.h	1653;"	d
XBARA_PDD_GetPWM_FAULT1	.\Static_Code\PDD\XBARA_PDD.h	1673;"	d
XBARA_PDD_GetPWM_FAULT2	.\Static_Code\PDD\XBARA_PDD.h	1691;"	d
XBARA_PDD_GetPWM_FAULT3	.\Static_Code\PDD\XBARA_PDD.h	1711;"	d
XBARA_PDD_GetPWM_FORCE	.\Static_Code\PDD\XBARA_PDD.h	1729;"	d
XBARA_PDD_GetSCI0_RXD	.\Static_Code\PDD\XBARA_PDD.h	1825;"	d
XBARA_PDD_GetSCI1_RXD	.\Static_Code\PDD\XBARA_PDD.h	1843;"	d
XBARA_PDD_GetTA0_IN	.\Static_Code\PDD\XBARA_PDD.h	1749;"	d
XBARA_PDD_GetTA1_IN	.\Static_Code\PDD\XBARA_PDD.h	1767;"	d
XBARA_PDD_GetTA2_IN	.\Static_Code\PDD\XBARA_PDD.h	1787;"	d
XBARA_PDD_GetTA3_IN	.\Static_Code\PDD\XBARA_PDD.h	1805;"	d
XBARA_PDD_GetXB_OUT10	.\Static_Code\PDD\XBARA_PDD.h	1289;"	d
XBARA_PDD_GetXB_OUT11	.\Static_Code\PDD\XBARA_PDD.h	1307;"	d
XBARA_PDD_GetXB_OUT4	.\Static_Code\PDD\XBARA_PDD.h	1175;"	d
XBARA_PDD_GetXB_OUT5	.\Static_Code\PDD\XBARA_PDD.h	1193;"	d
XBARA_PDD_GetXB_OUT6	.\Static_Code\PDD\XBARA_PDD.h	1213;"	d
XBARA_PDD_GetXB_OUT7	.\Static_Code\PDD\XBARA_PDD.h	1231;"	d
XBARA_PDD_GetXB_OUT8	.\Static_Code\PDD\XBARA_PDD.h	1251;"	d
XBARA_PDD_GetXB_OUT9	.\Static_Code\PDD\XBARA_PDD.h	1269;"	d
XBARA_PDD_H_	.\Static_Code\PDD\XBARA_PDD.h	9;"	d
XBARA_PDD_NEITHER_EDGE	.\Static_Code\PDD\XBARA_PDD.h	85;"	d
XBARA_PDD_PIT0_SYNC_OUT	.\Static_Code\PDD\XBARA_PDD.h	68;"	d
XBARA_PDD_PIT1_SYNC_OUT	.\Static_Code\PDD\XBARA_PDD.h	69;"	d
XBARA_PDD_PWM0_TRG0	.\Static_Code\PDD\XBARA_PDD.h	60;"	d
XBARA_PDD_PWM0_TRG1	.\Static_Code\PDD\XBARA_PDD.h	61;"	d
XBARA_PDD_PWM1_TRG0	.\Static_Code\PDD\XBARA_PDD.h	62;"	d
XBARA_PDD_PWM1_TRG1	.\Static_Code\PDD\XBARA_PDD.h	63;"	d
XBARA_PDD_PWM2_TRG0	.\Static_Code\PDD\XBARA_PDD.h	64;"	d
XBARA_PDD_PWM2_TRG1	.\Static_Code\PDD\XBARA_PDD.h	65;"	d
XBARA_PDD_PWM3_TRG0	.\Static_Code\PDD\XBARA_PDD.h	66;"	d
XBARA_PDD_PWM3_TRG1	.\Static_Code\PDD\XBARA_PDD.h	67;"	d
XBARA_PDD_REQ_DISABLE	.\Static_Code\PDD\XBARA_PDD.h	78;"	d
XBARA_PDD_REQ_DMA	.\Static_Code\PDD\XBARA_PDD.h	76;"	d
XBARA_PDD_REQ_INTERRUPT	.\Static_Code\PDD\XBARA_PDD.h	77;"	d
XBARA_PDD_RISING_EDGE	.\Static_Code\PDD\XBARA_PDD.h	82;"	d
XBARA_PDD_ReadCrossbarControl0Reg	.\Static_Code\PDD\XBARA_PDD.h	3763;"	d
XBARA_PDD_ReadCrossbarControl1Reg	.\Static_Code\PDD\XBARA_PDD.h	3781;"	d
XBARA_PDD_ReadCrossbarSelect0Reg	.\Static_Code\PDD\XBARA_PDD.h	2301;"	d
XBARA_PDD_ReadCrossbarSelect10Reg	.\Static_Code\PDD\XBARA_PDD.h	2481;"	d
XBARA_PDD_ReadCrossbarSelect11Reg	.\Static_Code\PDD\XBARA_PDD.h	2499;"	d
XBARA_PDD_ReadCrossbarSelect12Reg	.\Static_Code\PDD\XBARA_PDD.h	2517;"	d
XBARA_PDD_ReadCrossbarSelect13Reg	.\Static_Code\PDD\XBARA_PDD.h	2535;"	d
XBARA_PDD_ReadCrossbarSelect14Reg	.\Static_Code\PDD\XBARA_PDD.h	2553;"	d
XBARA_PDD_ReadCrossbarSelect15Reg	.\Static_Code\PDD\XBARA_PDD.h	2571;"	d
XBARA_PDD_ReadCrossbarSelect16Reg	.\Static_Code\PDD\XBARA_PDD.h	2589;"	d
XBARA_PDD_ReadCrossbarSelect17Reg	.\Static_Code\PDD\XBARA_PDD.h	2607;"	d
XBARA_PDD_ReadCrossbarSelect18Reg	.\Static_Code\PDD\XBARA_PDD.h	2625;"	d
XBARA_PDD_ReadCrossbarSelect19Reg	.\Static_Code\PDD\XBARA_PDD.h	2643;"	d
XBARA_PDD_ReadCrossbarSelect1Reg	.\Static_Code\PDD\XBARA_PDD.h	2319;"	d
XBARA_PDD_ReadCrossbarSelect20Reg	.\Static_Code\PDD\XBARA_PDD.h	2661;"	d
XBARA_PDD_ReadCrossbarSelect2Reg	.\Static_Code\PDD\XBARA_PDD.h	2337;"	d
XBARA_PDD_ReadCrossbarSelect3Reg	.\Static_Code\PDD\XBARA_PDD.h	2355;"	d
XBARA_PDD_ReadCrossbarSelect4Reg	.\Static_Code\PDD\XBARA_PDD.h	2373;"	d
XBARA_PDD_ReadCrossbarSelect5Reg	.\Static_Code\PDD\XBARA_PDD.h	2391;"	d
XBARA_PDD_ReadCrossbarSelect6Reg	.\Static_Code\PDD\XBARA_PDD.h	2409;"	d
XBARA_PDD_ReadCrossbarSelect7Reg	.\Static_Code\PDD\XBARA_PDD.h	2427;"	d
XBARA_PDD_ReadCrossbarSelect8Reg	.\Static_Code\PDD\XBARA_PDD.h	2445;"	d
XBARA_PDD_ReadCrossbarSelect9Reg	.\Static_Code\PDD\XBARA_PDD.h	2463;"	d
XBARA_PDD_SetADCA_TRIG	.\Static_Code\PDD\XBARA_PDD.h	397;"	d
XBARA_PDD_SetADCB_TRIG	.\Static_Code\PDD\XBARA_PDD.h	422;"	d
XBARA_PDD_SetCMPA	.\Static_Code\PDD\XBARA_PDD.h	497;"	d
XBARA_PDD_SetCMPB	.\Static_Code\PDD\XBARA_PDD.h	522;"	d
XBARA_PDD_SetCMPC	.\Static_Code\PDD\XBARA_PDD.h	547;"	d
XBARA_PDD_SetCMPD	.\Static_Code\PDD\XBARA_PDD.h	572;"	d
XBARA_PDD_SetDACA_12B_SYNC	.\Static_Code\PDD\XBARA_PDD.h	472;"	d
XBARA_PDD_SetDACB_12B_SYNC	.\Static_Code\PDD\XBARA_PDD.h	447;"	d
XBARA_PDD_SetDMA_REQ0	.\Static_Code\PDD\XBARA_PDD.h	105;"	d
XBARA_PDD_SetDMA_REQ0Destination	.\Static_Code\PDD\XBARA_PDD.h	2681;"	d
XBARA_PDD_SetDMA_REQ0EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3378;"	d
XBARA_PDD_SetDMA_REQ1	.\Static_Code\PDD\XBARA_PDD.h	130;"	d
XBARA_PDD_SetDMA_REQ1Destination	.\Static_Code\PDD\XBARA_PDD.h	2720;"	d
XBARA_PDD_SetDMA_REQ1EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3404;"	d
XBARA_PDD_SetDMA_REQ2	.\Static_Code\PDD\XBARA_PDD.h	155;"	d
XBARA_PDD_SetDMA_REQ2Destination	.\Static_Code\PDD\XBARA_PDD.h	2759;"	d
XBARA_PDD_SetDMA_REQ2EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3430;"	d
XBARA_PDD_SetDMA_REQ3	.\Static_Code\PDD\XBARA_PDD.h	180;"	d
XBARA_PDD_SetDMA_REQ3Destination	.\Static_Code\PDD\XBARA_PDD.h	2798;"	d
XBARA_PDD_SetDMA_REQ3EdgeDetection	.\Static_Code\PDD\XBARA_PDD.h	3456;"	d
XBARA_PDD_SetEWM_IN	.\Static_Code\PDD\XBARA_PDD.h	1077;"	d
XBARA_PDD_SetPWM0_EXTA	.\Static_Code\PDD\XBARA_PDD.h	596;"	d
XBARA_PDD_SetPWM0_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	692;"	d
XBARA_PDD_SetPWM1_EXTA	.\Static_Code\PDD\XBARA_PDD.h	620;"	d
XBARA_PDD_SetPWM1_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	716;"	d
XBARA_PDD_SetPWM2_EXTA	.\Static_Code\PDD\XBARA_PDD.h	644;"	d
XBARA_PDD_SetPWM2_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	740;"	d
XBARA_PDD_SetPWM3_EXTA	.\Static_Code\PDD\XBARA_PDD.h	668;"	d
XBARA_PDD_SetPWM3_EXT_SYNC	.\Static_Code\PDD\XBARA_PDD.h	764;"	d
XBARA_PDD_SetPWM_EXT_CLK	.\Static_Code\PDD\XBARA_PDD.h	788;"	d
XBARA_PDD_SetPWM_FAULT0	.\Static_Code\PDD\XBARA_PDD.h	812;"	d
XBARA_PDD_SetPWM_FAULT1	.\Static_Code\PDD\XBARA_PDD.h	836;"	d
XBARA_PDD_SetPWM_FAULT2	.\Static_Code\PDD\XBARA_PDD.h	860;"	d
XBARA_PDD_SetPWM_FAULT3	.\Static_Code\PDD\XBARA_PDD.h	884;"	d
XBARA_PDD_SetPWM_FORCE	.\Static_Code\PDD\XBARA_PDD.h	908;"	d
XBARA_PDD_SetSCI0_RXD	.\Static_Code\PDD\XBARA_PDD.h	1028;"	d
XBARA_PDD_SetSCI1_RXD	.\Static_Code\PDD\XBARA_PDD.h	1052;"	d
XBARA_PDD_SetTA0_IN	.\Static_Code\PDD\XBARA_PDD.h	932;"	d
XBARA_PDD_SetTA1_IN	.\Static_Code\PDD\XBARA_PDD.h	956;"	d
XBARA_PDD_SetTA2_IN	.\Static_Code\PDD\XBARA_PDD.h	980;"	d
XBARA_PDD_SetTA3_IN	.\Static_Code\PDD\XBARA_PDD.h	1004;"	d
XBARA_PDD_SetXB_OUT10	.\Static_Code\PDD\XBARA_PDD.h	348;"	d
XBARA_PDD_SetXB_OUT11	.\Static_Code\PDD\XBARA_PDD.h	372;"	d
XBARA_PDD_SetXB_OUT4	.\Static_Code\PDD\XBARA_PDD.h	204;"	d
XBARA_PDD_SetXB_OUT5	.\Static_Code\PDD\XBARA_PDD.h	228;"	d
XBARA_PDD_SetXB_OUT6	.\Static_Code\PDD\XBARA_PDD.h	252;"	d
XBARA_PDD_SetXB_OUT7	.\Static_Code\PDD\XBARA_PDD.h	276;"	d
XBARA_PDD_SetXB_OUT8	.\Static_Code\PDD\XBARA_PDD.h	300;"	d
XBARA_PDD_SetXB_OUT9	.\Static_Code\PDD\XBARA_PDD.h	324;"	d
XBARA_PDD_TA0_OUT	.\Static_Code\PDD\XBARA_PDD.h	56;"	d
XBARA_PDD_TA1_OUT	.\Static_Code\PDD\XBARA_PDD.h	57;"	d
XBARA_PDD_TA2_OUT	.\Static_Code\PDD\XBARA_PDD.h	58;"	d
XBARA_PDD_TA3_OUT	.\Static_Code\PDD\XBARA_PDD.h	59;"	d
XBARA_PDD_VDD	.\Static_Code\PDD\XBARA_PDD.h	43;"	d
XBARA_PDD_VSS	.\Static_Code\PDD\XBARA_PDD.h	42;"	d
XBARA_PDD_WriteCrossbarControl0Reg	.\Static_Code\PDD\XBARA_PDD.h	3725;"	d
XBARA_PDD_WriteCrossbarControl1Reg	.\Static_Code\PDD\XBARA_PDD.h	3745;"	d
XBARA_PDD_WriteCrossbarSelect0Reg	.\Static_Code\PDD\XBARA_PDD.h	1883;"	d
XBARA_PDD_WriteCrossbarSelect10Reg	.\Static_Code\PDD\XBARA_PDD.h	2083;"	d
XBARA_PDD_WriteCrossbarSelect11Reg	.\Static_Code\PDD\XBARA_PDD.h	2103;"	d
XBARA_PDD_WriteCrossbarSelect12Reg	.\Static_Code\PDD\XBARA_PDD.h	2123;"	d
XBARA_PDD_WriteCrossbarSelect13Reg	.\Static_Code\PDD\XBARA_PDD.h	2143;"	d
XBARA_PDD_WriteCrossbarSelect14Reg	.\Static_Code\PDD\XBARA_PDD.h	2163;"	d
XBARA_PDD_WriteCrossbarSelect15Reg	.\Static_Code\PDD\XBARA_PDD.h	2183;"	d
XBARA_PDD_WriteCrossbarSelect16Reg	.\Static_Code\PDD\XBARA_PDD.h	2203;"	d
XBARA_PDD_WriteCrossbarSelect17Reg	.\Static_Code\PDD\XBARA_PDD.h	2223;"	d
XBARA_PDD_WriteCrossbarSelect18Reg	.\Static_Code\PDD\XBARA_PDD.h	2243;"	d
XBARA_PDD_WriteCrossbarSelect19Reg	.\Static_Code\PDD\XBARA_PDD.h	2263;"	d
XBARA_PDD_WriteCrossbarSelect1Reg	.\Static_Code\PDD\XBARA_PDD.h	1903;"	d
XBARA_PDD_WriteCrossbarSelect20Reg	.\Static_Code\PDD\XBARA_PDD.h	2283;"	d
XBARA_PDD_WriteCrossbarSelect2Reg	.\Static_Code\PDD\XBARA_PDD.h	1923;"	d
XBARA_PDD_WriteCrossbarSelect3Reg	.\Static_Code\PDD\XBARA_PDD.h	1943;"	d
XBARA_PDD_WriteCrossbarSelect4Reg	.\Static_Code\PDD\XBARA_PDD.h	1963;"	d
XBARA_PDD_WriteCrossbarSelect5Reg	.\Static_Code\PDD\XBARA_PDD.h	1983;"	d
XBARA_PDD_WriteCrossbarSelect6Reg	.\Static_Code\PDD\XBARA_PDD.h	2003;"	d
XBARA_PDD_WriteCrossbarSelect7Reg	.\Static_Code\PDD\XBARA_PDD.h	2023;"	d
XBARA_PDD_WriteCrossbarSelect8Reg	.\Static_Code\PDD\XBARA_PDD.h	2043;"	d
XBARA_PDD_WriteCrossbarSelect9Reg	.\Static_Code\PDD\XBARA_PDD.h	2063;"	d
XBARA_PDD_XB_IN2	.\Static_Code\PDD\XBARA_PDD.h	44;"	d
XBARA_PDD_XB_IN3	.\Static_Code\PDD\XBARA_PDD.h	45;"	d
XBARA_PDD_XB_IN4	.\Static_Code\PDD\XBARA_PDD.h	46;"	d
XBARA_PDD_XB_IN5	.\Static_Code\PDD\XBARA_PDD.h	47;"	d
XBARA_PDD_XB_IN6	.\Static_Code\PDD\XBARA_PDD.h	48;"	d
XBARA_PDD_XB_IN7	.\Static_Code\PDD\XBARA_PDD.h	49;"	d
XBARA_PDD_XB_IN8	.\Static_Code\PDD\XBARA_PDD.h	50;"	d
XBARA_PDD_XB_IN9	.\Static_Code\PDD\XBARA_PDD.h	51;"	d
XBARA_SEL0	.\Static_Code\IO_Map\MC56F82748.h	6931;"	d
XBARA_SEL0_REG	.\Static_Code\IO_Map\MC56F82748.h	6687;"	d
XBARA_SEL0_SEL0	.\Static_Code\IO_Map\MC56F82748.h	6728;"	d
XBARA_SEL0_SEL0_MASK	.\Static_Code\IO_Map\MC56F82748.h	6726;"	d
XBARA_SEL0_SEL0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6727;"	d
XBARA_SEL0_SEL1	.\Static_Code\IO_Map\MC56F82748.h	6731;"	d
XBARA_SEL0_SEL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	6729;"	d
XBARA_SEL0_SEL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6730;"	d
XBARA_SEL1	.\Static_Code\IO_Map\MC56F82748.h	6932;"	d
XBARA_SEL10	.\Static_Code\IO_Map\MC56F82748.h	6941;"	d
XBARA_SEL10_REG	.\Static_Code\IO_Map\MC56F82748.h	6697;"	d
XBARA_SEL10_SEL20	.\Static_Code\IO_Map\MC56F82748.h	6798;"	d
XBARA_SEL10_SEL20_MASK	.\Static_Code\IO_Map\MC56F82748.h	6796;"	d
XBARA_SEL10_SEL20_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6797;"	d
XBARA_SEL10_SEL21	.\Static_Code\IO_Map\MC56F82748.h	6801;"	d
XBARA_SEL10_SEL21_MASK	.\Static_Code\IO_Map\MC56F82748.h	6799;"	d
XBARA_SEL10_SEL21_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6800;"	d
XBARA_SEL11	.\Static_Code\IO_Map\MC56F82748.h	6942;"	d
XBARA_SEL11_REG	.\Static_Code\IO_Map\MC56F82748.h	6698;"	d
XBARA_SEL11_SEL22	.\Static_Code\IO_Map\MC56F82748.h	6805;"	d
XBARA_SEL11_SEL22_MASK	.\Static_Code\IO_Map\MC56F82748.h	6803;"	d
XBARA_SEL11_SEL22_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6804;"	d
XBARA_SEL11_SEL23	.\Static_Code\IO_Map\MC56F82748.h	6808;"	d
XBARA_SEL11_SEL23_MASK	.\Static_Code\IO_Map\MC56F82748.h	6806;"	d
XBARA_SEL11_SEL23_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6807;"	d
XBARA_SEL12	.\Static_Code\IO_Map\MC56F82748.h	6943;"	d
XBARA_SEL12_REG	.\Static_Code\IO_Map\MC56F82748.h	6699;"	d
XBARA_SEL12_SEL24	.\Static_Code\IO_Map\MC56F82748.h	6812;"	d
XBARA_SEL12_SEL24_MASK	.\Static_Code\IO_Map\MC56F82748.h	6810;"	d
XBARA_SEL12_SEL24_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6811;"	d
XBARA_SEL12_SEL25	.\Static_Code\IO_Map\MC56F82748.h	6815;"	d
XBARA_SEL12_SEL25_MASK	.\Static_Code\IO_Map\MC56F82748.h	6813;"	d
XBARA_SEL12_SEL25_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6814;"	d
XBARA_SEL13	.\Static_Code\IO_Map\MC56F82748.h	6944;"	d
XBARA_SEL13_REG	.\Static_Code\IO_Map\MC56F82748.h	6700;"	d
XBARA_SEL13_SEL26	.\Static_Code\IO_Map\MC56F82748.h	6819;"	d
XBARA_SEL13_SEL26_MASK	.\Static_Code\IO_Map\MC56F82748.h	6817;"	d
XBARA_SEL13_SEL26_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6818;"	d
XBARA_SEL13_SEL27	.\Static_Code\IO_Map\MC56F82748.h	6822;"	d
XBARA_SEL13_SEL27_MASK	.\Static_Code\IO_Map\MC56F82748.h	6820;"	d
XBARA_SEL13_SEL27_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6821;"	d
XBARA_SEL14	.\Static_Code\IO_Map\MC56F82748.h	6945;"	d
XBARA_SEL14_REG	.\Static_Code\IO_Map\MC56F82748.h	6701;"	d
XBARA_SEL14_SEL28	.\Static_Code\IO_Map\MC56F82748.h	6826;"	d
XBARA_SEL14_SEL28_MASK	.\Static_Code\IO_Map\MC56F82748.h	6824;"	d
XBARA_SEL14_SEL28_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6825;"	d
XBARA_SEL14_SEL29	.\Static_Code\IO_Map\MC56F82748.h	6829;"	d
XBARA_SEL14_SEL29_MASK	.\Static_Code\IO_Map\MC56F82748.h	6827;"	d
XBARA_SEL14_SEL29_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6828;"	d
XBARA_SEL15	.\Static_Code\IO_Map\MC56F82748.h	6946;"	d
XBARA_SEL15_REG	.\Static_Code\IO_Map\MC56F82748.h	6702;"	d
XBARA_SEL15_SEL30	.\Static_Code\IO_Map\MC56F82748.h	6833;"	d
XBARA_SEL15_SEL30_MASK	.\Static_Code\IO_Map\MC56F82748.h	6831;"	d
XBARA_SEL15_SEL30_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6832;"	d
XBARA_SEL15_SEL31	.\Static_Code\IO_Map\MC56F82748.h	6836;"	d
XBARA_SEL15_SEL31_MASK	.\Static_Code\IO_Map\MC56F82748.h	6834;"	d
XBARA_SEL15_SEL31_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6835;"	d
XBARA_SEL16	.\Static_Code\IO_Map\MC56F82748.h	6947;"	d
XBARA_SEL16_REG	.\Static_Code\IO_Map\MC56F82748.h	6703;"	d
XBARA_SEL16_SEL32	.\Static_Code\IO_Map\MC56F82748.h	6840;"	d
XBARA_SEL16_SEL32_MASK	.\Static_Code\IO_Map\MC56F82748.h	6838;"	d
XBARA_SEL16_SEL32_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6839;"	d
XBARA_SEL16_SEL33	.\Static_Code\IO_Map\MC56F82748.h	6843;"	d
XBARA_SEL16_SEL33_MASK	.\Static_Code\IO_Map\MC56F82748.h	6841;"	d
XBARA_SEL16_SEL33_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6842;"	d
XBARA_SEL17	.\Static_Code\IO_Map\MC56F82748.h	6948;"	d
XBARA_SEL17_REG	.\Static_Code\IO_Map\MC56F82748.h	6704;"	d
XBARA_SEL17_SEL34	.\Static_Code\IO_Map\MC56F82748.h	6847;"	d
XBARA_SEL17_SEL34_MASK	.\Static_Code\IO_Map\MC56F82748.h	6845;"	d
XBARA_SEL17_SEL34_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6846;"	d
XBARA_SEL17_SEL35	.\Static_Code\IO_Map\MC56F82748.h	6850;"	d
XBARA_SEL17_SEL35_MASK	.\Static_Code\IO_Map\MC56F82748.h	6848;"	d
XBARA_SEL17_SEL35_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6849;"	d
XBARA_SEL18	.\Static_Code\IO_Map\MC56F82748.h	6949;"	d
XBARA_SEL18_REG	.\Static_Code\IO_Map\MC56F82748.h	6705;"	d
XBARA_SEL18_SEL36	.\Static_Code\IO_Map\MC56F82748.h	6854;"	d
XBARA_SEL18_SEL36_MASK	.\Static_Code\IO_Map\MC56F82748.h	6852;"	d
XBARA_SEL18_SEL36_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6853;"	d
XBARA_SEL18_SEL37	.\Static_Code\IO_Map\MC56F82748.h	6857;"	d
XBARA_SEL18_SEL37_MASK	.\Static_Code\IO_Map\MC56F82748.h	6855;"	d
XBARA_SEL18_SEL37_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6856;"	d
XBARA_SEL19	.\Static_Code\IO_Map\MC56F82748.h	6950;"	d
XBARA_SEL19_REG	.\Static_Code\IO_Map\MC56F82748.h	6706;"	d
XBARA_SEL19_SEL38	.\Static_Code\IO_Map\MC56F82748.h	6861;"	d
XBARA_SEL19_SEL38_MASK	.\Static_Code\IO_Map\MC56F82748.h	6859;"	d
XBARA_SEL19_SEL38_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6860;"	d
XBARA_SEL19_SEL39	.\Static_Code\IO_Map\MC56F82748.h	6864;"	d
XBARA_SEL19_SEL39_MASK	.\Static_Code\IO_Map\MC56F82748.h	6862;"	d
XBARA_SEL19_SEL39_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6863;"	d
XBARA_SEL1_REG	.\Static_Code\IO_Map\MC56F82748.h	6688;"	d
XBARA_SEL1_SEL2	.\Static_Code\IO_Map\MC56F82748.h	6735;"	d
XBARA_SEL1_SEL2_MASK	.\Static_Code\IO_Map\MC56F82748.h	6733;"	d
XBARA_SEL1_SEL2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6734;"	d
XBARA_SEL1_SEL3	.\Static_Code\IO_Map\MC56F82748.h	6738;"	d
XBARA_SEL1_SEL3_MASK	.\Static_Code\IO_Map\MC56F82748.h	6736;"	d
XBARA_SEL1_SEL3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6737;"	d
XBARA_SEL2	.\Static_Code\IO_Map\MC56F82748.h	6933;"	d
XBARA_SEL20	.\Static_Code\IO_Map\MC56F82748.h	6951;"	d
XBARA_SEL20_REG	.\Static_Code\IO_Map\MC56F82748.h	6707;"	d
XBARA_SEL20_SEL40	.\Static_Code\IO_Map\MC56F82748.h	6868;"	d
XBARA_SEL20_SEL40_MASK	.\Static_Code\IO_Map\MC56F82748.h	6866;"	d
XBARA_SEL20_SEL40_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6867;"	d
XBARA_SEL2_REG	.\Static_Code\IO_Map\MC56F82748.h	6689;"	d
XBARA_SEL2_SEL4	.\Static_Code\IO_Map\MC56F82748.h	6742;"	d
XBARA_SEL2_SEL4_MASK	.\Static_Code\IO_Map\MC56F82748.h	6740;"	d
XBARA_SEL2_SEL4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6741;"	d
XBARA_SEL2_SEL5	.\Static_Code\IO_Map\MC56F82748.h	6745;"	d
XBARA_SEL2_SEL5_MASK	.\Static_Code\IO_Map\MC56F82748.h	6743;"	d
XBARA_SEL2_SEL5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6744;"	d
XBARA_SEL3	.\Static_Code\IO_Map\MC56F82748.h	6934;"	d
XBARA_SEL3_REG	.\Static_Code\IO_Map\MC56F82748.h	6690;"	d
XBARA_SEL3_SEL6	.\Static_Code\IO_Map\MC56F82748.h	6749;"	d
XBARA_SEL3_SEL6_MASK	.\Static_Code\IO_Map\MC56F82748.h	6747;"	d
XBARA_SEL3_SEL6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6748;"	d
XBARA_SEL3_SEL7	.\Static_Code\IO_Map\MC56F82748.h	6752;"	d
XBARA_SEL3_SEL7_MASK	.\Static_Code\IO_Map\MC56F82748.h	6750;"	d
XBARA_SEL3_SEL7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6751;"	d
XBARA_SEL4	.\Static_Code\IO_Map\MC56F82748.h	6935;"	d
XBARA_SEL4_REG	.\Static_Code\IO_Map\MC56F82748.h	6691;"	d
XBARA_SEL4_SEL8	.\Static_Code\IO_Map\MC56F82748.h	6756;"	d
XBARA_SEL4_SEL8_MASK	.\Static_Code\IO_Map\MC56F82748.h	6754;"	d
XBARA_SEL4_SEL8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6755;"	d
XBARA_SEL4_SEL9	.\Static_Code\IO_Map\MC56F82748.h	6759;"	d
XBARA_SEL4_SEL9_MASK	.\Static_Code\IO_Map\MC56F82748.h	6757;"	d
XBARA_SEL4_SEL9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6758;"	d
XBARA_SEL5	.\Static_Code\IO_Map\MC56F82748.h	6936;"	d
XBARA_SEL5_REG	.\Static_Code\IO_Map\MC56F82748.h	6692;"	d
XBARA_SEL5_SEL10	.\Static_Code\IO_Map\MC56F82748.h	6763;"	d
XBARA_SEL5_SEL10_MASK	.\Static_Code\IO_Map\MC56F82748.h	6761;"	d
XBARA_SEL5_SEL10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6762;"	d
XBARA_SEL5_SEL11	.\Static_Code\IO_Map\MC56F82748.h	6766;"	d
XBARA_SEL5_SEL11_MASK	.\Static_Code\IO_Map\MC56F82748.h	6764;"	d
XBARA_SEL5_SEL11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6765;"	d
XBARA_SEL6	.\Static_Code\IO_Map\MC56F82748.h	6937;"	d
XBARA_SEL6_REG	.\Static_Code\IO_Map\MC56F82748.h	6693;"	d
XBARA_SEL6_SEL12	.\Static_Code\IO_Map\MC56F82748.h	6770;"	d
XBARA_SEL6_SEL12_MASK	.\Static_Code\IO_Map\MC56F82748.h	6768;"	d
XBARA_SEL6_SEL12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6769;"	d
XBARA_SEL6_SEL13	.\Static_Code\IO_Map\MC56F82748.h	6773;"	d
XBARA_SEL6_SEL13_MASK	.\Static_Code\IO_Map\MC56F82748.h	6771;"	d
XBARA_SEL6_SEL13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6772;"	d
XBARA_SEL7	.\Static_Code\IO_Map\MC56F82748.h	6938;"	d
XBARA_SEL7_REG	.\Static_Code\IO_Map\MC56F82748.h	6694;"	d
XBARA_SEL7_SEL14	.\Static_Code\IO_Map\MC56F82748.h	6777;"	d
XBARA_SEL7_SEL14_MASK	.\Static_Code\IO_Map\MC56F82748.h	6775;"	d
XBARA_SEL7_SEL14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6776;"	d
XBARA_SEL7_SEL15	.\Static_Code\IO_Map\MC56F82748.h	6780;"	d
XBARA_SEL7_SEL15_MASK	.\Static_Code\IO_Map\MC56F82748.h	6778;"	d
XBARA_SEL7_SEL15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6779;"	d
XBARA_SEL8	.\Static_Code\IO_Map\MC56F82748.h	6939;"	d
XBARA_SEL8_REG	.\Static_Code\IO_Map\MC56F82748.h	6695;"	d
XBARA_SEL8_SEL16	.\Static_Code\IO_Map\MC56F82748.h	6784;"	d
XBARA_SEL8_SEL16_MASK	.\Static_Code\IO_Map\MC56F82748.h	6782;"	d
XBARA_SEL8_SEL16_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6783;"	d
XBARA_SEL8_SEL17	.\Static_Code\IO_Map\MC56F82748.h	6787;"	d
XBARA_SEL8_SEL17_MASK	.\Static_Code\IO_Map\MC56F82748.h	6785;"	d
XBARA_SEL8_SEL17_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6786;"	d
XBARA_SEL9	.\Static_Code\IO_Map\MC56F82748.h	6940;"	d
XBARA_SEL9_REG	.\Static_Code\IO_Map\MC56F82748.h	6696;"	d
XBARA_SEL9_SEL18	.\Static_Code\IO_Map\MC56F82748.h	6791;"	d
XBARA_SEL9_SEL18_MASK	.\Static_Code\IO_Map\MC56F82748.h	6789;"	d
XBARA_SEL9_SEL18_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6790;"	d
XBARA_SEL9_SEL19	.\Static_Code\IO_Map\MC56F82748.h	6794;"	d
XBARA_SEL9_SEL19_MASK	.\Static_Code\IO_Map\MC56F82748.h	6792;"	d
XBARA_SEL9_SEL19_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	6793;"	d
XBARB_BASE_PTR	.\Static_Code\IO_Map\MC56F82748.h	7084;"	d
XBARB_BASE_PTRS	.\Static_Code\IO_Map\MC56F82748.h	7086;"	d
XBARB_Init	.\Static_Code\Peripherals\XBARB_Init.c	/^void XBARB_Init(void) {$/;"	f
XBARB_MemMap	.\Static_Code\IO_Map\MC56F82748.h	/^typedef struct XBARB_MemMap {$/;"	s
XBARB_MemMapPtr	.\Static_Code\IO_Map\MC56F82748.h	/^} volatile *XBARB_MemMapPtr;$/;"	t
XBARB_PDD_CMPA_OUT	.\Static_Code\PDD\XBARB_PDD.h	52;"	d
XBARB_PDD_CMPB_OUT	.\Static_Code\PDD\XBARB_PDD.h	53;"	d
XBARB_PDD_CMPC_OUT	.\Static_Code\PDD\XBARB_PDD.h	54;"	d
XBARB_PDD_CMPD_OUT	.\Static_Code\PDD\XBARB_PDD.h	55;"	d
XBARB_PDD_GetAOI_Input0A	.\Static_Code\PDD\XBARB_PDD.h	468;"	d
XBARB_PDD_GetAOI_Input0B	.\Static_Code\PDD\XBARB_PDD.h	486;"	d
XBARB_PDD_GetAOI_Input0C	.\Static_Code\PDD\XBARB_PDD.h	506;"	d
XBARB_PDD_GetAOI_Input0D	.\Static_Code\PDD\XBARB_PDD.h	524;"	d
XBARB_PDD_GetAOI_Input1A	.\Static_Code\PDD\XBARB_PDD.h	544;"	d
XBARB_PDD_GetAOI_Input1B	.\Static_Code\PDD\XBARB_PDD.h	562;"	d
XBARB_PDD_GetAOI_Input1C	.\Static_Code\PDD\XBARB_PDD.h	582;"	d
XBARB_PDD_GetAOI_Input1D	.\Static_Code\PDD\XBARB_PDD.h	600;"	d
XBARB_PDD_GetAOI_Input2A	.\Static_Code\PDD\XBARB_PDD.h	620;"	d
XBARB_PDD_GetAOI_Input2B	.\Static_Code\PDD\XBARB_PDD.h	638;"	d
XBARB_PDD_GetAOI_Input2C	.\Static_Code\PDD\XBARB_PDD.h	658;"	d
XBARB_PDD_GetAOI_Input2D	.\Static_Code\PDD\XBARB_PDD.h	676;"	d
XBARB_PDD_GetAOI_Input3A	.\Static_Code\PDD\XBARB_PDD.h	696;"	d
XBARB_PDD_GetAOI_Input3B	.\Static_Code\PDD\XBARB_PDD.h	714;"	d
XBARB_PDD_GetAOI_Input3C	.\Static_Code\PDD\XBARB_PDD.h	734;"	d
XBARB_PDD_GetAOI_Input3D	.\Static_Code\PDD\XBARB_PDD.h	752;"	d
XBARB_PDD_H_	.\Static_Code\PDD\XBARB_PDD.h	9;"	d
XBARB_PDD_PWM0_TRG0	.\Static_Code\PDD\XBARB_PDD.h	60;"	d
XBARB_PDD_PWM0_TRG1	.\Static_Code\PDD\XBARB_PDD.h	61;"	d
XBARB_PDD_PWM1_TRG0	.\Static_Code\PDD\XBARB_PDD.h	62;"	d
XBARB_PDD_PWM1_TRG1	.\Static_Code\PDD\XBARB_PDD.h	63;"	d
XBARB_PDD_PWM2_TRG0	.\Static_Code\PDD\XBARB_PDD.h	64;"	d
XBARB_PDD_PWM2_TRG1	.\Static_Code\PDD\XBARB_PDD.h	65;"	d
XBARB_PDD_PWM3_TRG0	.\Static_Code\PDD\XBARB_PDD.h	66;"	d
XBARB_PDD_PWM3_TRG1	.\Static_Code\PDD\XBARB_PDD.h	67;"	d
XBARB_PDD_ReadCrossbarSelect0Reg	.\Static_Code\PDD\XBARB_PDD.h	932;"	d
XBARB_PDD_ReadCrossbarSelect1Reg	.\Static_Code\PDD\XBARB_PDD.h	950;"	d
XBARB_PDD_ReadCrossbarSelect2Reg	.\Static_Code\PDD\XBARB_PDD.h	968;"	d
XBARB_PDD_ReadCrossbarSelect3Reg	.\Static_Code\PDD\XBARB_PDD.h	986;"	d
XBARB_PDD_ReadCrossbarSelect4Reg	.\Static_Code\PDD\XBARB_PDD.h	1004;"	d
XBARB_PDD_ReadCrossbarSelect5Reg	.\Static_Code\PDD\XBARB_PDD.h	1022;"	d
XBARB_PDD_ReadCrossbarSelect6Reg	.\Static_Code\PDD\XBARB_PDD.h	1040;"	d
XBARB_PDD_ReadCrossbarSelect7Reg	.\Static_Code\PDD\XBARB_PDD.h	1058;"	d
XBARB_PDD_SCI0_TXD	.\Static_Code\PDD\XBARB_PDD.h	42;"	d
XBARB_PDD_SCI1_TXD	.\Static_Code\PDD\XBARB_PDD.h	43;"	d
XBARB_PDD_SetAOI_Input0A	.\Static_Code\PDD\XBARB_PDD.h	86;"	d
XBARB_PDD_SetAOI_Input0B	.\Static_Code\PDD\XBARB_PDD.h	110;"	d
XBARB_PDD_SetAOI_Input0C	.\Static_Code\PDD\XBARB_PDD.h	134;"	d
XBARB_PDD_SetAOI_Input0D	.\Static_Code\PDD\XBARB_PDD.h	158;"	d
XBARB_PDD_SetAOI_Input1A	.\Static_Code\PDD\XBARB_PDD.h	182;"	d
XBARB_PDD_SetAOI_Input1B	.\Static_Code\PDD\XBARB_PDD.h	206;"	d
XBARB_PDD_SetAOI_Input1C	.\Static_Code\PDD\XBARB_PDD.h	230;"	d
XBARB_PDD_SetAOI_Input1D	.\Static_Code\PDD\XBARB_PDD.h	254;"	d
XBARB_PDD_SetAOI_Input2A	.\Static_Code\PDD\XBARB_PDD.h	278;"	d
XBARB_PDD_SetAOI_Input2B	.\Static_Code\PDD\XBARB_PDD.h	302;"	d
XBARB_PDD_SetAOI_Input2C	.\Static_Code\PDD\XBARB_PDD.h	326;"	d
XBARB_PDD_SetAOI_Input2D	.\Static_Code\PDD\XBARB_PDD.h	350;"	d
XBARB_PDD_SetAOI_Input3A	.\Static_Code\PDD\XBARB_PDD.h	374;"	d
XBARB_PDD_SetAOI_Input3B	.\Static_Code\PDD\XBARB_PDD.h	398;"	d
XBARB_PDD_SetAOI_Input3C	.\Static_Code\PDD\XBARB_PDD.h	422;"	d
XBARB_PDD_SetAOI_Input3D	.\Static_Code\PDD\XBARB_PDD.h	446;"	d
XBARB_PDD_TA0_OUT	.\Static_Code\PDD\XBARB_PDD.h	56;"	d
XBARB_PDD_TA1_OUT	.\Static_Code\PDD\XBARB_PDD.h	57;"	d
XBARB_PDD_TA2_OUT	.\Static_Code\PDD\XBARB_PDD.h	58;"	d
XBARB_PDD_TA3_OUT	.\Static_Code\PDD\XBARB_PDD.h	59;"	d
XBARB_PDD_WriteCrossbarSelect0Reg	.\Static_Code\PDD\XBARB_PDD.h	774;"	d
XBARB_PDD_WriteCrossbarSelect1Reg	.\Static_Code\PDD\XBARB_PDD.h	794;"	d
XBARB_PDD_WriteCrossbarSelect2Reg	.\Static_Code\PDD\XBARB_PDD.h	814;"	d
XBARB_PDD_WriteCrossbarSelect3Reg	.\Static_Code\PDD\XBARB_PDD.h	834;"	d
XBARB_PDD_WriteCrossbarSelect4Reg	.\Static_Code\PDD\XBARB_PDD.h	854;"	d
XBARB_PDD_WriteCrossbarSelect5Reg	.\Static_Code\PDD\XBARB_PDD.h	874;"	d
XBARB_PDD_WriteCrossbarSelect6Reg	.\Static_Code\PDD\XBARB_PDD.h	894;"	d
XBARB_PDD_WriteCrossbarSelect7Reg	.\Static_Code\PDD\XBARB_PDD.h	914;"	d
XBARB_PDD_XB_IN2	.\Static_Code\PDD\XBARB_PDD.h	44;"	d
XBARB_PDD_XB_IN3	.\Static_Code\PDD\XBARB_PDD.h	45;"	d
XBARB_PDD_XB_IN4	.\Static_Code\PDD\XBARB_PDD.h	46;"	d
XBARB_PDD_XB_IN5	.\Static_Code\PDD\XBARB_PDD.h	47;"	d
XBARB_PDD_XB_IN6	.\Static_Code\PDD\XBARB_PDD.h	48;"	d
XBARB_PDD_XB_IN7	.\Static_Code\PDD\XBARB_PDD.h	49;"	d
XBARB_PDD_XB_IN8	.\Static_Code\PDD\XBARB_PDD.h	50;"	d
XBARB_PDD_XB_IN9	.\Static_Code\PDD\XBARB_PDD.h	51;"	d
XBARB_SEL0	.\Static_Code\IO_Map\MC56F82748.h	7100;"	d
XBARB_SEL0_REG	.\Static_Code\IO_Map\MC56F82748.h	6997;"	d
XBARB_SEL0_SEL0	.\Static_Code\IO_Map\MC56F82748.h	7023;"	d
XBARB_SEL0_SEL0_MASK	.\Static_Code\IO_Map\MC56F82748.h	7021;"	d
XBARB_SEL0_SEL0_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7022;"	d
XBARB_SEL0_SEL1	.\Static_Code\IO_Map\MC56F82748.h	7026;"	d
XBARB_SEL0_SEL1_MASK	.\Static_Code\IO_Map\MC56F82748.h	7024;"	d
XBARB_SEL0_SEL1_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7025;"	d
XBARB_SEL1	.\Static_Code\IO_Map\MC56F82748.h	7101;"	d
XBARB_SEL1_REG	.\Static_Code\IO_Map\MC56F82748.h	6998;"	d
XBARB_SEL1_SEL2	.\Static_Code\IO_Map\MC56F82748.h	7030;"	d
XBARB_SEL1_SEL2_MASK	.\Static_Code\IO_Map\MC56F82748.h	7028;"	d
XBARB_SEL1_SEL2_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7029;"	d
XBARB_SEL1_SEL3	.\Static_Code\IO_Map\MC56F82748.h	7033;"	d
XBARB_SEL1_SEL3_MASK	.\Static_Code\IO_Map\MC56F82748.h	7031;"	d
XBARB_SEL1_SEL3_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7032;"	d
XBARB_SEL2	.\Static_Code\IO_Map\MC56F82748.h	7102;"	d
XBARB_SEL2_REG	.\Static_Code\IO_Map\MC56F82748.h	6999;"	d
XBARB_SEL2_SEL4	.\Static_Code\IO_Map\MC56F82748.h	7037;"	d
XBARB_SEL2_SEL4_MASK	.\Static_Code\IO_Map\MC56F82748.h	7035;"	d
XBARB_SEL2_SEL4_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7036;"	d
XBARB_SEL2_SEL5	.\Static_Code\IO_Map\MC56F82748.h	7040;"	d
XBARB_SEL2_SEL5_MASK	.\Static_Code\IO_Map\MC56F82748.h	7038;"	d
XBARB_SEL2_SEL5_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7039;"	d
XBARB_SEL3	.\Static_Code\IO_Map\MC56F82748.h	7103;"	d
XBARB_SEL3_REG	.\Static_Code\IO_Map\MC56F82748.h	7000;"	d
XBARB_SEL3_SEL6	.\Static_Code\IO_Map\MC56F82748.h	7044;"	d
XBARB_SEL3_SEL6_MASK	.\Static_Code\IO_Map\MC56F82748.h	7042;"	d
XBARB_SEL3_SEL6_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7043;"	d
XBARB_SEL3_SEL7	.\Static_Code\IO_Map\MC56F82748.h	7047;"	d
XBARB_SEL3_SEL7_MASK	.\Static_Code\IO_Map\MC56F82748.h	7045;"	d
XBARB_SEL3_SEL7_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7046;"	d
XBARB_SEL4	.\Static_Code\IO_Map\MC56F82748.h	7104;"	d
XBARB_SEL4_REG	.\Static_Code\IO_Map\MC56F82748.h	7001;"	d
XBARB_SEL4_SEL8	.\Static_Code\IO_Map\MC56F82748.h	7051;"	d
XBARB_SEL4_SEL8_MASK	.\Static_Code\IO_Map\MC56F82748.h	7049;"	d
XBARB_SEL4_SEL8_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7050;"	d
XBARB_SEL4_SEL9	.\Static_Code\IO_Map\MC56F82748.h	7054;"	d
XBARB_SEL4_SEL9_MASK	.\Static_Code\IO_Map\MC56F82748.h	7052;"	d
XBARB_SEL4_SEL9_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7053;"	d
XBARB_SEL5	.\Static_Code\IO_Map\MC56F82748.h	7105;"	d
XBARB_SEL5_REG	.\Static_Code\IO_Map\MC56F82748.h	7002;"	d
XBARB_SEL5_SEL10	.\Static_Code\IO_Map\MC56F82748.h	7058;"	d
XBARB_SEL5_SEL10_MASK	.\Static_Code\IO_Map\MC56F82748.h	7056;"	d
XBARB_SEL5_SEL10_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7057;"	d
XBARB_SEL5_SEL11	.\Static_Code\IO_Map\MC56F82748.h	7061;"	d
XBARB_SEL5_SEL11_MASK	.\Static_Code\IO_Map\MC56F82748.h	7059;"	d
XBARB_SEL5_SEL11_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7060;"	d
XBARB_SEL6	.\Static_Code\IO_Map\MC56F82748.h	7106;"	d
XBARB_SEL6_REG	.\Static_Code\IO_Map\MC56F82748.h	7003;"	d
XBARB_SEL6_SEL12	.\Static_Code\IO_Map\MC56F82748.h	7065;"	d
XBARB_SEL6_SEL12_MASK	.\Static_Code\IO_Map\MC56F82748.h	7063;"	d
XBARB_SEL6_SEL12_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7064;"	d
XBARB_SEL6_SEL13	.\Static_Code\IO_Map\MC56F82748.h	7068;"	d
XBARB_SEL6_SEL13_MASK	.\Static_Code\IO_Map\MC56F82748.h	7066;"	d
XBARB_SEL6_SEL13_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7067;"	d
XBARB_SEL7	.\Static_Code\IO_Map\MC56F82748.h	7107;"	d
XBARB_SEL7_REG	.\Static_Code\IO_Map\MC56F82748.h	7004;"	d
XBARB_SEL7_SEL14	.\Static_Code\IO_Map\MC56F82748.h	7072;"	d
XBARB_SEL7_SEL14_MASK	.\Static_Code\IO_Map\MC56F82748.h	7070;"	d
XBARB_SEL7_SEL14_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7071;"	d
XBARB_SEL7_SEL15	.\Static_Code\IO_Map\MC56F82748.h	7075;"	d
XBARB_SEL7_SEL15_MASK	.\Static_Code\IO_Map\MC56F82748.h	7073;"	d
XBARB_SEL7_SEL15_SHIFT	.\Static_Code\IO_Map\MC56F82748.h	7074;"	d
XP_MODE	.\Project_Settings\Startup_Code\56F83x_init.asm	/^XP_MODE                                                          EQU  $0080$/;"	d
Year	.\Generated_Code\PE_LDD.h	/^  uint16_t Year;                       \/* Years (1998 - 2099) *\/$/;"	m	struct:__anon10
ZXCTRL1	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t ZXCTRL1;                                \/**< ADC Zero Crossing Control 1 Register, offset: 0x2 *\/$/;"	m	struct:ADC_MemMap
ZXCTRL2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t ZXCTRL2;                                \/**< ADC Zero Crossing Control 2 Register, offset: 0x3 *\/$/;"	m	struct:ADC_MemMap
ZXCTRL3	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t ZXCTRL3;                                \/**< ADC Zero Crossing Control 3 Register, offset: 0x58 *\/$/;"	m	struct:ADC_MemMap
ZXSTAT	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t ZXSTAT;                                 \/**< ADC Zero Crossing Status Register, offset: 0xD *\/$/;"	m	struct:ADC_MemMap
ZXSTAT2	.\Static_Code\IO_Map\MC56F82748.h	/^  uint16_t ZXSTAT2;                                \/**< ADC Zero Crossing Status Register 2, offset: 0x5E *\/$/;"	m	struct:ADC_MemMap
ZeroCrossingMode	.\Generated_Code\PE_LDD.h	/^  LDD_ADC_TZeroCrossingMode ZeroCrossingMode; \/*!< Zero crossing mode *\/$/;"	m	struct:__anon44
_EntryPoint	.\Static_Code\System\CPU_Init.c	/^void _EntryPoint(void)$/;"	f
__ASSERT_H	.\Generated_Code\assert.h	60;"	d
__BWUserType_TShadowRegs	.\Static_Code\System\CPU_Init.h	60;"	d
__BWUserType_TU1_TValueType	.\Generated_Code\TU1.h	114;"	d
__BitIoLdd1_H	.\Generated_Code\BitIoLdd1.h	85;"	d
__CPU_Config_H	.\Generated_Code\CPU_Config.h	51;"	d
__CPU_Init_H	.\Static_Code\System\CPU_Init.h	47;"	d
__Cpu_H	.\Generated_Code\Cpu.h	67;"	d
__DI	.\Static_Code\System\PE_Types.h	681;"	d
__EI	.\Static_Code\System\PE_Types.h	679;"	d
__EI0	.\Static_Code\System\PE_Types.h	674;"	d
__EI1	.\Static_Code\System\PE_Types.h	675;"	d
__EI2	.\Static_Code\System\PE_Types.h	676;"	d
__EI3	.\Static_Code\System\PE_Types.h	677;"	d
__Events_H	.\Sources\Events.h	30;"	d
__GPIOE0_H	.\Generated_Code\GPIOE0.h	91;"	d
__IO_Map_H	.\Generated_Code\IO_Map.h	64;"	d
__Init_Config_H	.\Generated_Code\Init_Config.h	66;"	d
__PDD_Includes_H	.\Static_Code\System\PDD_Includes.h	47;"	d
__PE_Const_H	.\Static_Code\System\PE_Const.h	3;"	d
__PE_Error_H	.\Static_Code\System\PE_Error.h	3;"	d
__PE_LDD_H	.\Generated_Code\PE_LDD.h	56;"	d
__PE_Types_H	.\Static_Code\System\PE_Types.h	3;"	d
__Peripherals_Init_H	.\Static_Code\System\Peripherals_Init.h	47;"	d
__TU1_H	.\Generated_Code\TU1.h	96;"	d
__Vectors_Config_H	.\Generated_Code\Vectors_Config.h	47;"	d
_cfm	.\Static_Code\System\CPU_Init.c	/^static const uint8_t _cfm[] = {CPU_FLASH_CONFIG_FIELD};$/;"	v	file:
_vect	.\Static_Code\System\Vectors.c	/^volatile asm void _vect(void) {$/;"	f
_vectboot	.\Static_Code\System\Vectors.c	/^volatile asm void _vectboot(void) {$/;"	f
alpha	.\Static_Code\System\PE_Types.h	/^        Frac16 alpha;$/;"	m	struct:__anon78
assert	.\Generated_Code\assert.h	73;"	d
assert	.\Generated_Code\assert.h	79;"	d
assert	.\Generated_Code\assert.h	81;"	d
b	.\Static_Code\System\PE_Types.h	/^   } b;$/;"	m	union:__anon65	typeref:struct:__anon65::__anon66
beta	.\Static_Code\System\PE_Types.h	/^        Frac16 beta;$/;"	m	struct:__anon78
bool	.\Static_Code\System\PE_Types.h	/^typedef unsigned char bool;$/;"	t
byte	.\Static_Code\System\PE_Types.h	/^typedef unsigned char byte;$/;"	t
changeRegBit	.\Static_Code\System\PE_Types.h	519;"	d
changeRegBits	.\Static_Code\System\PE_Types.h	518;"	d
char_t	.\Static_Code\System\PE_Types.h	/^typedef char                char_t;$/;"	t
clrReg16Bit	.\Static_Code\System\PE_Types.h	573;"	d
clrReg16Bits	.\Static_Code\System\PE_Types.h	583;"	d
clrReg16BitsByOne	.\Static_Code\System\PE_Types.h	594;"	d
clrReg32Bit	.\Static_Code\System\PE_Types.h	620;"	d
clrReg32Bits	.\Static_Code\System\PE_Types.h	630;"	d
clrReg32BitsByOne	.\Static_Code\System\PE_Types.h	640;"	d
clrReg8Bit	.\Static_Code\System\PE_Types.h	527;"	d
clrReg8Bits	.\Static_Code\System\PE_Types.h	537;"	d
clrReg8BitsByOne	.\Static_Code\System\PE_Types.h	547;"	d
clrRegBit	.\Static_Code\System\PE_Types.h	506;"	d
clrRegBits	.\Static_Code\System\PE_Types.h	512;"	d
clrSetReg16Bits	.\Static_Code\System\PE_Types.h	587;"	d
clrSetReg32Bits	.\Static_Code\System\PE_Types.h	633;"	d
clrSetReg8Bits	.\Static_Code\System\PE_Types.h	540;"	d
cosine	.\Static_Code\System\PE_Types.h	/^        Frac16 cosine;$/;"	m	struct:__anon79
cpu_bus_clk_hz	.\Generated_Code\Cpu.h	/^  uint32_t cpu_bus_clk_hz;             \/* Bus clock frequency in clock configuration *\/$/;"	m	struct:__anon2
cpu_core_clk_hz	.\Generated_Code\Cpu.h	/^  uint32_t cpu_core_clk_hz;            \/* Core clock frequency in clock configuration *\/$/;"	m	struct:__anon2
cpu_pll_clk_hz	.\Generated_Code\Cpu.h	/^  uint32_t cpu_pll_clk_hz;             \/* PLL clock frequency in clock configuration *\/$/;"	m	struct:__anon2
cpu_system_clk_hz	.\Generated_Code\Cpu.h	/^  uint32_t cpu_system_clk_hz;          \/* System clock frequency in clock configuration *\/$/;"	m	struct:__anon2
cpu_xtal_clk_hz	.\Generated_Code\Cpu.h	/^  uint32_t cpu_xtal_clk_hz;            \/* System OSC external reference clock frequency in clock configuration *\/$/;"	m	struct:__anon2
d_axis	.\Static_Code\System\PE_Types.h	/^        Frac16 d_axis;$/;"	m	struct:__anon80
decoder_sEncScale	.\Static_Code\System\PE_Types.h	/^}decoder_sEncScale;$/;"	t	typeref:struct:__anon73
decoder_sEncSignals	.\Static_Code\System\PE_Types.h	/^}decoder_sEncSignals;$/;"	t	typeref:struct:__anon74
decoder_sState	.\Static_Code\System\PE_Types.h	/^}decoder_sState;$/;"	t	typeref:struct:__anon69
decoder_uEncSignals	.\Static_Code\System\PE_Types.h	/^} decoder_uEncSignals;$/;"	t	typeref:union:__anon75
decoder_uReg32bit	.\Static_Code\System\PE_Types.h	/^} decoder_uReg32bit;$/;"	t	typeref:union:__anon67
dlong	.\Static_Code\System\PE_Types.h	/^typedef unsigned long dlong[2];$/;"	t
dword	.\Static_Code\System\PE_Types.h	/^typedef unsigned long dword;$/;"	t
end_prom2pram	.\Project_Settings\Startup_Code\56F83x_init.asm	/^end_prom2pram:$/;"	l
end_prom2xram	.\Project_Settings\Startup_Code\56F83x_init.asm	/^end_prom2xram:$/;"	l
end_xrom2xram	.\Project_Settings\Startup_Code\56F83x_init.asm	/^end_xrom2xram:$/;"	l
end_zeroBSS	.\Project_Settings\Startup_Code\56F83x_init.asm	/^end_zeroBSS:$/;"	l
getReg	.\Static_Code\System\PE_Types.h	509;"	d
getReg16	.\Static_Code\System\PE_Types.h	579;"	d
getReg16BitGroupVal	.\Static_Code\System\PE_Types.h	598;"	d
getReg32	.\Static_Code\System\PE_Types.h	626;"	d
getReg32BitGroupVal	.\Static_Code\System\PE_Types.h	644;"	d
getReg8	.\Static_Code\System\PE_Types.h	533;"	d
getReg8BitGroupVal	.\Static_Code\System\PE_Types.h	551;"	d
getRegBit	.\Static_Code\System\PE_Types.h	507;"	d
getRegBitGroup	.\Static_Code\System\PE_Types.h	514;"	d
getRegBits	.\Static_Code\System\PE_Types.h	511;"	d
height	.\Static_Code\System\PE_Types.h	/^  word height;            \/* Image height *\/$/;"	m	struct:__anon64
high	.\Static_Code\System\PE_Types.h	/^     byte high,low;$/;"	m	struct:__anon65::__anon66
i_Sd	.\Static_Code\System\PE_Types.h	/^        Frac16 i_Sd;$/;"	m	struct:__anon81
i_Sq	.\Static_Code\System\PE_Types.h	/^        Frac16 i_Sq;$/;"	m	struct:__anon81
ibool	.\Static_Code\System\PE_Types.h	/^typedef int ibool;$/;"	t
in16	.\Static_Code\System\PE_Types.h	668;"	d
input	.\Static_Code\System\PE_Types.h	672;"	d
invertReg16Bit	.\Static_Code\System\PE_Types.h	574;"	d
invertReg16Bits	.\Static_Code\System\PE_Types.h	585;"	d
invertReg32Bit	.\Static_Code\System\PE_Types.h	621;"	d
invertReg32Bits	.\Static_Code\System\PE_Types.h	632;"	d
invertReg8Bit	.\Static_Code\System\PE_Types.h	528;"	d
invertReg8Bits	.\Static_Code\System\PE_Types.h	539;"	d
loop_at_end_of_app	.\Project_Settings\Startup_Code\56F83x_init.asm	/^loop_at_end_of_app:$/;"	l
low	.\Static_Code\System\PE_Types.h	/^     byte high,low;$/;"	m	struct:__anon65::__anon66
main	.\Sources\main.c	/^void main(void)$/;"	f
mcPhaseA	.\Static_Code\System\PE_Types.h	/^        mcPhaseA,$/;"	e	enum:__anon76
mcPhaseB	.\Static_Code\System\PE_Types.h	/^        mcPhaseB,$/;"	e	enum:__anon76
mcPhaseC	.\Static_Code\System\PE_Types.h	/^        mcPhaseC$/;"	e	enum:__anon76
mc_ePhaseType	.\Static_Code\System\PE_Types.h	/^} mc_ePhaseType;$/;"	t	typeref:enum:__anon76
mc_s3PhaseSystem	.\Static_Code\System\PE_Types.h	/^} mc_s3PhaseSystem;$/;"	t	typeref:struct:__anon77
mc_sAngle	.\Static_Code\System\PE_Types.h	/^} mc_sAngle;$/;"	t	typeref:struct:__anon79
mc_sDQEstabl	.\Static_Code\System\PE_Types.h	/^} mc_sDQEstabl;$/;"	t	typeref:struct:__anon81
mc_sDQsystem	.\Static_Code\System\PE_Types.h	/^} mc_sDQsystem;$/;"	t	typeref:struct:__anon80
mc_sPIDparams	.\Static_Code\System\PE_Types.h	/^}mc_sPIDparams;$/;"	t	typeref:struct:__anon82
mc_sPIparams	.\Static_Code\System\PE_Types.h	/^}mc_sPIparams;$/;"	t	typeref:struct:__anon83
mc_sPhase	.\Static_Code\System\PE_Types.h	/^} mc_sPhase;$/;"	t	typeref:struct:__anon78
mc_tPWMSignalMask	.\Static_Code\System\PE_Types.h	/^typedef UWord16 mc_tPWMSignalMask;    \/*  pwm_tSignalMask contains six control bits$/;"	t
name	.\Static_Code\System\PE_Types.h	/^  char_t *name;           \/* Image name *\/$/;"	m	struct:__anon64
noinc	.\Project_Settings\Startup_Code\56F83x_init.asm	/^noinc:$/;"	l
normDiffPosCoef	.\Static_Code\System\PE_Types.h	/^        Int16   normDiffPosCoef;$/;"	m	struct:__anon73
normPosCoef	.\Static_Code\System\PE_Types.h	/^        Int16   normPosCoef;$/;"	m	struct:__anon73
omega_field	.\Static_Code\System\PE_Types.h	/^        Frac16 omega_field;$/;"	m	struct:__anon81
out16	.\Static_Code\System\PE_Types.h	669;"	d
output	.\Static_Code\System\PE_Types.h	671;"	d
periphBitsClr16	.\Static_Code\System\PE_Types.h	610;"	d
periphBitsClr32	.\Static_Code\System\PE_Types.h	656;"	d
periphBitsClr8	.\Static_Code\System\PE_Types.h	563;"	d
periphBitsSet16	.\Static_Code\System\PE_Types.h	611;"	d
periphBitsSet32	.\Static_Code\System\PE_Types.h	657;"	d
periphBitsSet8	.\Static_Code\System\PE_Types.h	564;"	d
periphBitsTest16	.\Static_Code\System\PE_Types.h	612;"	d
periphBitsTest32	.\Static_Code\System\PE_Types.h	658;"	d
periphBitsTest8	.\Static_Code\System\PE_Types.h	565;"	d
periphMemDummyRead	.\Static_Code\System\PE_Types.h	/^inline void periphMemDummyRead(register volatile UWord16* addr)$/;"	f
periphMemRead16	.\Static_Code\System\PE_Types.h	609;"	d
periphMemRead32	.\Static_Code\System\PE_Types.h	655;"	d
periphMemRead8	.\Static_Code\System\PE_Types.h	562;"	d
periphMemWrite16	.\Static_Code\System\PE_Types.h	608;"	d
periphMemWrite32	.\Static_Code\System\PE_Types.h	654;"	d
periphMemWrite8	.\Static_Code\System\PE_Types.h	561;"	d
pixmap	.\Static_Code\System\PE_Types.h	/^  byte *pixmap;           \/* Image pixel bitmap *\/$/;"	m	struct:__anon64
posdh	.\Static_Code\System\PE_Types.h	/^                Word16 posdh; };$/;"	m	union:__anon69::__anon70
posh	.\Static_Code\System\PE_Types.h	/^                Word32 posh; };$/;"	m	union:__anon69::__anon72
psi_Rd	.\Static_Code\System\PE_Types.h	/^        Frac16 psi_Rd;$/;"	m	struct:__anon81
q_axis	.\Static_Code\System\PE_Types.h	/^        Frac16 q_axis;$/;"	m	struct:__anon80
revh	.\Static_Code\System\PE_Types.h	/^                Word16 revh; };$/;"	m	union:__anon69::__anon71
scaleDiffPosCoef	.\Static_Code\System\PE_Types.h	/^        Int16   scaleDiffPosCoef;$/;"	m	struct:__anon73
scalePosCoef	.\Static_Code\System\PE_Types.h	/^        UInt16  scalePosCoef;$/;"	m	struct:__anon73
seqClrSetReg16BitGroupVal	.\Static_Code\System\PE_Types.h	600;"	d
seqClrSetReg16Bits	.\Static_Code\System\PE_Types.h	588;"	d
seqClrSetReg32BitGroupVal	.\Static_Code\System\PE_Types.h	646;"	d
seqClrSetReg32Bits	.\Static_Code\System\PE_Types.h	634;"	d
seqClrSetReg8BitGroupVal	.\Static_Code\System\PE_Types.h	553;"	d
seqClrSetReg8Bits	.\Static_Code\System\PE_Types.h	541;"	d
seqResetSetReg16BitGroupVal	.\Static_Code\System\PE_Types.h	604;"	d
seqResetSetReg16Bits	.\Static_Code\System\PE_Types.h	592;"	d
seqResetSetReg32BitGroupVal	.\Static_Code\System\PE_Types.h	650;"	d
seqResetSetReg32Bits	.\Static_Code\System\PE_Types.h	638;"	d
seqResetSetReg8BitGroupVal	.\Static_Code\System\PE_Types.h	557;"	d
seqResetSetReg8Bits	.\Static_Code\System\PE_Types.h	545;"	d
seqSetClrReg16BitGroupVal	.\Static_Code\System\PE_Types.h	602;"	d
seqSetClrReg16Bits	.\Static_Code\System\PE_Types.h	590;"	d
seqSetClrReg32BitGroupVal	.\Static_Code\System\PE_Types.h	648;"	d
seqSetClrReg32Bits	.\Static_Code\System\PE_Types.h	636;"	d
seqSetClrReg8BitGroupVal	.\Static_Code\System\PE_Types.h	555;"	d
seqSetClrReg8Bits	.\Static_Code\System\PE_Types.h	543;"	d
setReg	.\Static_Code\System\PE_Types.h	508;"	d
setReg16	.\Static_Code\System\PE_Types.h	578;"	d
setReg16Bit	.\Static_Code\System\PE_Types.h	572;"	d
setReg16BitGroupVal	.\Static_Code\System\PE_Types.h	599;"	d
setReg16Bits	.\Static_Code\System\PE_Types.h	584;"	d
setReg32	.\Static_Code\System\PE_Types.h	625;"	d
setReg32Bit	.\Static_Code\System\PE_Types.h	619;"	d
setReg32BitGroupVal	.\Static_Code\System\PE_Types.h	645;"	d
setReg32Bits	.\Static_Code\System\PE_Types.h	631;"	d
setReg8	.\Static_Code\System\PE_Types.h	532;"	d
setReg8Bit	.\Static_Code\System\PE_Types.h	526;"	d
setReg8BitGroupVal	.\Static_Code\System\PE_Types.h	552;"	d
setReg8Bits	.\Static_Code\System\PE_Types.h	538;"	d
setRegBit	.\Static_Code\System\PE_Types.h	505;"	d
setRegBitGroup	.\Static_Code\System\PE_Types.h	513;"	d
setRegBitVal	.\Static_Code\System\PE_Types.h	517;"	d
setRegBits	.\Static_Code\System\PE_Types.h	510;"	d
setRegMask	.\Static_Code\System\PE_Types.h	516;"	d
sine	.\Static_Code\System\PE_Types.h	/^        Frac16 sine;$/;"	m	struct:__anon79
size	.\Static_Code\System\PE_Types.h	/^  dword size;             \/* Image size *\/$/;"	m	struct:__anon64
testArray	.\Sources\main.c	/^const Int16 testArray[] = { \/* test array for section .p_flash_ROM_data *\/$/;"	v
testReg16Bit	.\Static_Code\System\PE_Types.h	575;"	d
testReg16BitGroup	.\Static_Code\System\PE_Types.h	597;"	d
testReg16Bits	.\Static_Code\System\PE_Types.h	582;"	d
testReg32Bit	.\Static_Code\System\PE_Types.h	622;"	d
testReg32BitGroup	.\Static_Code\System\PE_Types.h	643;"	d
testReg32Bits	.\Static_Code\System\PE_Types.h	629;"	d
testReg8Bit	.\Static_Code\System\PE_Types.h	529;"	d
testReg8BitGroup	.\Static_Code\System\PE_Types.h	550;"	d
testReg8Bits	.\Static_Code\System\PE_Types.h	536;"	d
w	.\Static_Code\System\PE_Types.h	/^   word w;$/;"	m	union:__anon65
width	.\Static_Code\System\PE_Types.h	/^  word width;             \/* Image width  *\/$/;"	m	struct:__anon64
word	.\Static_Code\System\PE_Types.h	/^typedef unsigned int word;$/;"	t
