/*!
\page DMA DMA (Init_DMA)
**          This file implements the DMA (DMA) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.

- \subpage DMA_settings
- \subpage DMA_regs_overview  
- \subpage DMA_regs_details
- \ref DMA_module "Component documentation" 

\page DMA_regs_overview Registers Initialization Overview
This page initialization values for the registers of the peripheral(s) configured
by the component. 
<table>
<tr><td colspan="4" class="ttitle1">DMA Initialization</td></tr>
<tr><td class="ttitle2">Address</td><td class="ttitle2">Register</td><td class="ttitle2">Register Value</td><td class="ttitle2">Register Description</td></tr>
<tr><td>0x0000C884</td><td>DMA_DSR_BCR0</td><td>
    0x01000100
 </td><td>DMA_DSR_BCR0 register, peripheral DMA.</td></tr>
<tr><td>0x0000C800</td><td>DMA_REQC</td><td>
    0x0B000000
 </td><td>DMA_REQC register, peripheral DMA.</td></tr>
<tr><td>0x0000C886</td><td>DMA_DCR0</td><td>
    0xE0655080
 </td><td>DMA_DCR0 register, peripheral DMA.</td></tr>
</table>
<br/>
\page DMA_regs_details Register Initialization Details
This page contains detailed description of initialization values for the 
registers of the peripheral(s) configured by the component. 

<div class="reghdr1">DMA_DSR_BCR0</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="1">CE</td>
<td colspan="1" rowspan="1">BES</td><td colspan="1" rowspan="1">BED</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="1">REQ</td><td colspan="1" rowspan="1">BSY</td><td colspan="1" rowspan="2">DONE</td>
<td colspan="8" rowspan="2">BCR</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1"></td><td colspan="1"></td><td colspan="1"></td><td colspan="1"></td><td colspan="1"></td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="24" rowspan="2">BCR</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x0000C884</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x01000100</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>30</td><td>CE</td><td>0x00</td><td>Configuration error</td>
<tr><td>29</td><td>BES</td><td>0x00</td><td>Bus error on source</td>
<tr><td>28</td><td>BED</td><td>0x00</td><td>Bus error on destination</td>
<tr><td>26</td><td>REQ</td><td>0x00</td><td>Request</td>
<tr><td>25</td><td>BSY</td><td>0x00</td><td>Busy</td>
<tr><td>24</td><td>DONE</td><td>0x01</td><td>Transactions done</td>
<tr><td>0 - 23</td><td>BCR</td><td>0x00</td><td>This field contains the number of bytes yet to be transferred for a given block</td>
</tr></table>
<div class="reghdr1">DMA_REQC</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1"></td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="4" rowspan="2">DMAC0</td><td colspan="1"></td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="4" rowspan="2">DMAC1</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1">CFSM0</td><td colspan="1">CFSM1</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1"></td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="4" rowspan="2">DMAC2</td><td colspan="1"></td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="4" rowspan="2">DMAC3</td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1">CFSM2</td><td colspan="1">CFSM3</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x0000C800</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0x0B000000</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>CFSM0</td><td>0x00</td><td>Clear state machine control 0</td>
<tr><td>24 - 27</td><td>DMAC0</td><td>0x08</td><td>DMA channel 0</td>
<tr><td>23</td><td>CFSM1</td><td>0x00</td><td>Clear state machine control 1</td>
<tr><td>16 - 19</td><td>DMAC1</td><td>0x00</td><td>DMA channel 1</td>
<tr><td>15</td><td>CFSM2</td><td>0x00</td><td>Clear state machine control 2</td>
<tr><td>8 - 11</td><td>DMAC2</td><td>0x00</td><td>DMA channel 2</td>
<tr><td>7</td><td>CFSM3</td><td>0x00</td><td>Clear state machine control 3</td>
<tr><td>0 - 3</td><td>DMAC3</td><td>0x00</td><td>DMA channel 3</td>
</tr></table>
<div class="reghdr1">DMA_DCR0</div>
<div class="regdiag">
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td>
<td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="1" rowspan="2">EINT</td><td colspan="1" rowspan="2">ERQ</td>
<td colspan="1" rowspan="2">CS</td><td colspan="1" rowspan="2">AA</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">-</td>
<td colspan="1" rowspan="2">-</td><td colspan="1" rowspan="2">SINC</td><td colspan="2" rowspan="2">SSIZE</td>
<td colspan="1" rowspan="2">DINC</td><td colspan="2" rowspan="2">DSIZE</td><td colspan="1"></td>
</tr>
<tr>
<td class="trd1c">W</td>
<td colspan="1">START</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
<table class="regtbl">
<tr class="trd1r">
<td class="trd1c">Bit</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td>
<td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td>
</tr>
<tr>
<td class="trd1c">R</td><td colspan="4" rowspan="2">SMOD</td><td colspan="4" rowspan="2">DMOD</td>
<td colspan="1" rowspan="2">D_REQ</td><td colspan="1" rowspan="2">-</td><td colspan="2" rowspan="2">LINKCC</td>
<td colspan="2" rowspan="2">LCH1</td><td colspan="2" rowspan="2">LCH2</td>
</tr>
<tr>
<td class="trd1c">W</td>
</tr>
<tr class="trd1r">
<td class="trd1c">Reset</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
        
</div>
<table class="regtbl2"><tr><td class="trowtit" colspan="2">Address</td><td colspan="2">0x0000C886</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">Initial value</td><td colspan="2">0xE0655080</td></tr>
<tr class="trowtit"><td  class="trowtit" colspan="2">After-reset value</td><td colspan="2">0x00000000</td></tr>
<tr><td class="ttitle2">Bit</td><td class="ttitle2">Field</td><td class="ttitle2">Value</td><td class="ttitle2">Description</td></tr>
<tr><td>31</td><td>EINT</td><td>0x01</td><td>Enable interrupt on completion of transfer</td>
<tr><td>30</td><td>ERQ</td><td>0x01</td><td>Enable peripheral request</td>
<tr><td>29</td><td>CS</td><td>0x01</td><td>Cycle steal</td>
<tr><td>28</td><td>AA</td><td>0x00</td><td>Auto-align</td>
<tr><td>22</td><td>SINC</td><td>0x01</td><td>Source increment</td>
<tr><td>20 - 21</td><td>SSIZE</td><td>0x02</td><td>Source size</td>
<tr><td>19</td><td>DINC</td><td>0x00</td><td>Destination increment</td>
<tr><td>17 - 18</td><td>DSIZE</td><td>0x02</td><td>Destination size</td>
<tr><td>16</td><td>START</td><td>0x01</td><td>Start transfer</td>
<tr><td>12 - 15</td><td>SMOD</td><td>0x00</td><td>Source address modulo</td>
<tr><td>8 - 11</td><td>DMOD</td><td>0x00</td><td>Destination address modulo</td>
<tr><td>7</td><td>D_REQ</td><td>0x01</td><td>Disable request</td>
<tr><td>4 - 5</td><td>LINKCC</td><td>0x00</td><td>Link channel control</td>
<tr><td>2 - 3</td><td>LCH1</td><td>0x00</td><td>Link channel 1</td>
<tr><td>0 - 1</td><td>LCH2</td><td>0x00</td><td>Link channel 2</td>
</tr></table>
*/
/*!
\page DMA_settings Component Settings
\code
**          Component name                                 : DMA
**          Device                                         : DMA
**          Channels                                       : 
**            Channel 0                                    : Initialize
**              Settings                                   : 
**                Transfer mode                            : Cycle-steal
**                Auto disable external request            : Enabled
**                Auto align                               : Disabled
**                Channel request source                   : Request source 11
**                Channel links settings                   : 
**                  Link channel control                   : No link
**                  Link channel 1 (LCH1)                  : DMA channel 0
**                  Link channel 2 (LCH2)                  : DMA channel 0
**                Data source                              : 
**                  External object declaration            : extern uint16_t DMA_Data[];
**                  Address                                : (uint32_t)DMA_Data*2
**                  Address increment                      : Enabled
**                  Transfer size                          : 16-bit
**                  Address modulo                         : 256 Bytes
**                Data destination                         : 
**                  External object declaration            : 
**                  Address                                : (uint32_t)0x0000E011 * 2
**                  Address increment                      : Disabled
**                  Transfer size                          : 16-bit
**                  Address modulo                         : Buffer disabled
**                Byte count                               : 256
**              Pins/Signals                               : 
**                External DMA request                     : Disabled
**              Interrupts                                 : 
**                DMA transfer done interrupt              : 
**                  Interrupt                              : INT_DMA0
**                  Interrupt priority                     : 0
**                  ISR Name                               : DMA_transfer_done_isr
**                  DMA transfer interrupt                 : Enabled
**              Initialization                             : 
**                External request                         : Enabled
**                Start DMA transfer                       : Yes
**            Channel 1                                    : Do not initialize
**            Channel 2                                    : Do not initialize
**            Channel 3                                    : Do not initialize
**          Initialization                                 : 
**            Call Init method                             : yes
**            Utilize after reset values                   : default
\endcode
*/
