/*
** ###################################################################
**     Processors:          LPC55S16JBD100
**                          LPC55S16JBD64
**                          LPC55S16JEV98
**
**     Compiler:            IAR ANSI C/C++ Compiler for ARM
**     Reference manual:    LPC55S1x/LPC551x User manual Rev.0.6  15 November 2019
**     Version:             rev. 1.1, 2019-12-03
**     Build:               b191204
**
**     Abstract:
**         Linker file for the IAR ANSI C/C++ Compiler for ARM
**
**     Copyright 2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2019 NXP
**     All rights reserved.
**
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
** ###################################################################
*/


/* Stack and Heap Sizes */
define symbol __size_cstack__                  = 0x1000;
define symbol __size_heap__                    = 0x1000;

define symbol m_interrupts_start               = 0x00000000;
define symbol m_interrupts_end                 = 0x000003FF;

define symbol m_text_start                     = 0x00000400;
define symbol m_text_end                       = 0x0003FFFF;

define symbol m_data_start                     = 0x20004400;
define symbol m_data_end                       = 0x2001BFFF - 0x400;

/* SRAM X - for Core Code */
define symbol m_sramx_start                    = 0x04000000;
define symbol m_sramx_end                      = 0x04003FFF;

define memory mem with size = 4G;

define region TEXT_region             = mem:[from m_interrupts_start to m_interrupts_end]
                                      | mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define region XCODE_region            = mem:[from m_sramx_start to m_sramx_end];

define block CSTACK    with alignment = 8, size = __size_cstack__   { };
define block HEAP      with alignment = 8, size = __size_heap__     { };
define block RW        { readwrite };
define block ZI        { zi };

/* initialize by copy { readonly, readwrite, section .textrw }; */
initialize by copy { readwrite, section .textrw };
do not initialize  { section .noinit };

if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
  /* Required in a multi-threaded application */
  initialize by copy with packing = none { section __DLIB_PERTHREAD };
}

place at address mem: m_interrupts_start    { readonly section .intvec };
place in TEXT_region                        { readonly };
place in DATA_region                        { block RW };
place in DATA_region                        { block ZI };
place in DATA_region                        { last block HEAP };
place in CSTACK_region                      { block CSTACK };

place in XCODE_region                       { section .critical_code };
initialize by copy                          { section .critical_code };
place in XCODE_region                       { rw object core_portme.o,
                                              rw object core_main.o,
                                              rw object core_list_join.o,
                                              rw object core_matrix.o,
                                              rw object core_state.o,
                                              rw object core_util.o,
                                              rw object ee_printf.o,
                                            };
initialize by copy                          { object core_portme.o,
                                              object core_main.o,
                                              object core_list_join.o,
                                              object core_matrix.o,
                                              object core_state.o,
                                              object core_util.o,
                                              object ee_printf.o,
                                            };




